JP2022036098A - Semiconductor device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can achieve high performance, mass productivity and cost reduction.

SOLUTION: A semiconductor device comprises: a first semiconductor substrate that has a transfer Tr, a reset Tr and an amplification Tr arranged on a pixel array; and a second semiconductor substrate that has a logic circuit processing signals. The first semiconductor substrate and the second semiconductor substrate are laminated so that a first multilayer wiring layer and a second multilayer wiring layer are opposed to each other. At least one or more wirings at a side closest to the second semiconductor substrate of the first multilayer wiring layer and at least one or more wirings at a side closest to the first semiconductor substrate of the second multilayer wiring layer are directly bonded with each other.

SELECTED DRAWING: Figure 3

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a solid-state image sensor.

As a solid-state image sensor, an amplified solid-state image sensor represented by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state image sensor represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state image sensors are widely used in digital still cameras, digital video cameras, and the like. In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped mobile phone or a PDA (Personal Digital Assistant), a MOS type image sensor is often used from the viewpoint of low power supply voltage and power consumption.

The MOS type solid-state image sensor is formed of a photodiode whose unit pixel is a photoelectric conversion unit and a plurality of pixel transistors, and a pixel array (pixel area) in which the plurality of unit pixels are arranged in a two-dimensional array and a periphery. It has a circuit area and is configured. The plurality of pixel transistors are formed of MOS transistors, and are composed of a transfer transistor, a reset transistor, three transistors of amplification and a transistor, or four transistors including a selection transistor.

Conventionally, in such a MOS type solid-state image sensor, one semiconductor chip in which a pixel region in which a plurality of pixels are arranged is electrically connected and a semiconductor chip in which a logic circuit for performing signal processing is formed. Various solid-state image sensors configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a back-illuminated image sensor chip having a micro pad for each pixel cell and a signal processing chip having a signal processing circuit formed and having a micro pad are connected by a micro bump. ing. In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state image sensor provided with an image pickup pixel portion, and a signal processing chip provided with a peripheral circuit for signal processing are mounted on an interposer (intermediate substrate). The device is disclosed. Patent Document 3 includes an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. A configuration is disclosed in which the thin film circuit board and the logic circuit board are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip via a through-hole via.

Further, Patent Document 4 discloses a solid-state image pickup device in which a through electrode is provided on a solid-state image sensor supported by a transparent substrate, and the solid-state image sensor is electrically connected to a flexible circuit board via the through electrode. Further, Patent Document 5 discloses a configuration in which a back-illuminated solid-state image sensor is provided with an electrode that penetrates a support substrate.

As shown in Patent Documents 1 to 3, various techniques for mounting different types of circuit chips such as an image sensor chip and a logic circuit have been proposed. In the conventional technique, the functional chips are almost completed, and a through connection hole is formed to enable interconnection between the chips, which is characterized by being formed on one chip. There is.

Japanese Unexamined Patent Publication No. 2006-49361 JP-A-2007-13089 Japanese Unexamined Patent Publication No. 2008-13603 Japanese Patent No. 4000507 Japanese Patent Application Laid-Open No. 2003-31785

As seen in the conventional solid-state image sensor described above, it has been known as an idea to connect different types of chips by a connecting conductor penetrating a substrate to form a semiconductor device. However, it is necessary to make a connection hole while ensuring insulation in a deep substrate, and it is difficult to put it into practical use due to the cost economy of the manufacturing process required for processing the connection hole and embedding the connection conductor.

On the other hand, in order to form a small contact hole of, for example, about 1 μm, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning the film and an increase in cost are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is inevitably required to use a CVD film having good coating properties such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

In order to have economic efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to make it easier to form, and it is processed in the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select the technology that can be used.

Further, in a solid-state image sensor or the like, it is desired that an image region and a logic circuit for performing signal processing are formed so as to sufficiently exhibit their respective performances, and high performance is achieved.
Not only solid-state image sensors but also semiconductor devices having other semiconductor integrated circuits are desired to be formed so that the performance of each semiconductor integrated circuit can be fully exhibited and the performance can be improved.

In view of the above points, the present invention provides a solid-state image pickup device that fully exhibits each performance, achieves high performance, and achieves mass productivity and cost reduction.

The solid-state imaging device of the present invention includes a pixel array including a photoelectric conversion unit, a first semiconductor substrate having at least one of a transfer transistor, a reset transistor, and an amplification transistor, and a logic circuit for performing signal processing. The second semiconductor substrate, the first multilayer wiring layer formed on the side opposite to the light incident surface of the first semiconductor substrate, and the second multilayer wiring formed on the light incident surface side of the second semiconductor substrate. Has a layer. The first semiconductor substrate and the second semiconductor substrate were laminated so that the first multilayer wiring layer and the second multilayer wiring layer faced each other, and the first semiconductor substrate and the second semiconductor substrate were laminated. In each of the pixel area including the pixel array and the area outside the pixel area of the chip, at least one or more wirings on the second semiconductor substrate side of the first multilayer wiring layer and the second multilayer wiring layer. At least one or more wirings on the first semiconductor substrate side are directly bonded.

According to the present invention, since a pixel array and a logic circuit that sufficiently exhibit their respective performances are formed in each chip portion, it is possible to provide a high-performance semiconductor device, that is, a back-illuminated solid-state image pickup device.

It is a schematic block diagram which shows an example of the MOS solid-state image sensor applied to this invention. It is a schematic diagram of the solid-state image sensor which concerns on embodiment of this invention. It is a schematic block diagram of the main part which shows the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 1) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 2) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (3) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 4) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 5) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 6) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (7) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (8) which shows the solid-state image sensor and the manufacturing method thereof which concerns on 1st Embodiment. It is a manufacturing process diagram (9) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 10) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a block diagram of the solid-state image pickup apparatus which concerns on 2nd Embodiment. It is a block diagram of the solid-state image pickup apparatus which concerns on 3rd Embodiment. It is a schematic block diagram of the main part which shows the solid-state image sensor which concerns on 4th Embodiment. It is a manufacturing process diagram (the 1) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 4th Embodiment. It is a manufacturing process diagram (the 2) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 4th Embodiment. It is a manufacturing process diagram (3) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 4th Embodiment. It is a manufacturing process diagram (the 4) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 4th Embodiment. It is a manufacturing process diagram (No. 5) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 4th Embodiment. It is a schematic block diagram of the main part of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process drawing (the 1) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process drawing (the 2) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process diagram (3) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process drawing (the 4th) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. 5 is a manufacturing process diagram (No. 5) showing an example of a manufacturing method of a semiconductor device according to a fifth embodiment. 6 is a manufacturing process diagram (No. 6) showing an example of a manufacturing method of a semiconductor device according to a fifth embodiment. It is a schematic block diagram which shows the electronic device which concerns on 6th Embodiment.

Hereinafter, embodiments for carrying out the invention (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. Schematic configuration example of a MOS solid-state image sensor 2. 1st Embodiment (Example of configuration of solid-state image sensor and example of manufacturing method thereof)
3. 3. 2nd Embodiment (Structure example of solid-state image sensor)
4. Third Embodiment (Structure example of solid-state image sensor)
5. Fourth Embodiment (Example of configuration of solid-state image sensor and example of manufacturing method thereof)
6. Fifth Embodiment (Example of configuration of semiconductor device and example of manufacturing method thereof)
7. 6th Embodiment (constituent example of electronic device)

<1. Schematic configuration example of MOS solid-state image sensor>
FIG. 1 shows a schematic configuration of a MOS solid-state image sensor applied to the semiconductor device of the present invention. This MOS solid-state image sensor is applied to the solid-state image sensor of each embodiment. In the solid-state image sensor 1 of this example, as shown in FIG. 1, a pixel region (so-called pixel array) in which pixels 2 including a plurality of photoelectric conversion units on a semiconductor substrate 11 such as a silicon substrate are regularly arranged in a two-dimensional array is used. ) 3 and a peripheral circuit unit. The pixel 2 includes, for example, a photodiode that serves as a photoelectric conversion unit, and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be composed of, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. In addition, it is possible to add a selection transistor and configure it with four transistors. Since the equivalent circuit of a unit pixel is the same as usual, detailed description thereof will be omitted. Pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor to be shared. That is, in the shared pixel, the photodiode and the transfer transistor constituting the plurality of unit pixels are configured by sharing the other pixel transistor.

The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

The control circuit 8 receives an input clock and data instructing an operation mode and the like, and outputs data such as internal information of the solid-state image sensor. That is, the control circuit 8 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. do. Then, these signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixel in row units. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in a row-by-row manner in the vertical direction, and passes through the vertical signal line 9 to be a photoelectric conversion unit of each pixel 2, for example, a photodiode according to the amount of light received. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is arranged for each column of the pixel 2, for example, and performs signal processing such as noise reduction for the signal output from the pixel 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS for removing the fixed pattern noise peculiar to the pixel 2 and signal amplification and AD conversion. A horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 5 so as to be connected to the horizontal signal line 10.

The horizontal drive circuit 6 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 5 is sequentially selected, and a pixel signal is output from each of the column signal processing circuits 5 as a horizontal signal line. Output to 10.

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals. For example, there are cases where only buffering is performed, black level adjustment, column variation correction, various digital signal processing, and the like are performed. The input / output terminal 12 exchanges signals with the outside.

FIG. 2 shows a basic schematic configuration of the MOS solid-state image sensor according to the present invention. As shown in FIG. 2A, the conventional MOS solid-state image sensor 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. .. Normally, the image sensor 156 is composed of the pixel area 153 and the control circuit 154. On the other hand, in the MOS solid-state image sensor 21 according to the embodiment of the present invention, as shown in FIG. 2B, the pixel region 23 and the control circuit 24 are mounted on the first semiconductor chip unit 22, and the second semiconductor is mounted. A logic circuit 25 including a signal processing circuit for signal processing is mounted on the chip unit 26. The first and second semiconductor chips 22 and 26 are electrically connected to each other to form a MOS solid-state image sensor 21 as one semiconductor chip. In the MOS solid-state image sensor 27 according to another embodiment of the present invention, as shown in FIG. 2C, the pixel region 23 is mounted on the first semiconductor chip unit 22, and the control circuit 24 is mounted on the second semiconductor chip unit 26. , A logic circuit 25 including a signal processing circuit is mounted. The first and second semiconductor chips 22 and 26 are electrically connected to each other to form a MOS solid-state image sensor 27 as one semiconductor chip.

As will be described later, the MOS solid-state image sensor according to the above-described embodiment is characterized by its manufacturing method and the configuration obtained based on this manufacturing method.

<2. First Embodiment>
[Example of configuration of solid-state image sensor and example of manufacturing method thereof]
A semiconductor device according to the first embodiment of the present invention, that is, a MOS solid-state image pickup device, will be described with reference to FIGS. 3 and 4 to 13 together with a manufacturing method thereof.

In the first embodiment, first, as shown in FIG. 4, a semi-finished image sensor, that is, a pixel array (hereinafter referred to as a pixel array) is provided in a region to be a chip portion of a first semiconductor wafer (hereinafter referred to as a semiconductor substrate) 31. Hereinafter, the control circuit 24 is formed with the 23 (referred to as a pixel region). That is, a photodiode (PD) to be a photoelectric conversion part of each pixel is formed in a region to be a chip portion of a semiconductor substrate (for example, a silicon substrate) 31, and a source / drain region of each pixel transistor is formed in the semiconductor well region 32. Form 33. The semiconductor well region 32 is formed by introducing a first conductive type, for example, p-type impurity, and the source / drain region 33 is formed by introducing a second conductive type, for example, n-type impurity. The photodiode (PD) and the source / drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

The photodiode (PD) is formed to have an n-type semiconductor region 34 and a p-type semiconductor region 35 on the surface side of the substrate. A gate electrode 36 is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by a source / drain region 33 paired with the gate electrode 36. In FIG. 4, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD). Each unit pixel 30 is separated by the element separation region 38. The element separation region 38 includes so-called LOCOS, which forms a silicon oxide film by oxidizing the semiconductor substrate 31, STI (Shallow Trench Isolation), which opens a groove in the semiconductor substrate 31 and fills the groove with the silicon oxide film. It is formed of a conductive type impurity diffusion layer different from the diffusion layer that serves as a node.

On the other hand, on the control circuit 24 side, a MOS transistor constituting the control circuit is formed on the semiconductor substrate 31. FIG. 3 shows MOS transistors constituting the control circuit 23, represented by MOS transistors Tr3 and Tr4. Each MOS transistor Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed via a gate insulating film.

Next, a first layer of the interlayer insulating film 39 is formed on the surface of the semiconductor substrate 31, and then a connection hole is formed in the interlayer insulating film 39 to form a connecting conductor 44 to be connected to a required transistor. When forming the connecting conductors 44 having different heights, the first insulating thin film 43a, for example, a silicon oxide film, and the contact opening (later, the connecting conductor 44) connected to the gate electrode 36 and the source / drain region 33 are formed on the entire surface including the upper surface of the transistor. A second insulating thin film 43b, for example, a silicon nitride film, which serves as an etching stopper in etching for filling), is laminated. The first interlayer insulating film 39 is formed on the second insulating thin film 43b. Then, connection holes having different depths are selectively formed in the interlayer insulating film 39 of the first layer up to the second insulating thin film 43b which serves as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each portion so as to be continuous with each connection hole to form the connection hole. Then, the connection conductor 44 is embedded in each connection hole. When the etching stopper at the contact opening is not required, it is possible not to form the second insulating thin film 43b.

Next, a plurality of layers, in this example, three layers of metal wiring 40 are formed via the interlayer insulating film 39 so as to be connected to each connecting conductor 44, to form a multilayer wiring layer 41. The metal wiring 40 is formed of copper (Cu) wiring. Normally, each copper wiring is covered with a barrier metal film that prevents Cu diffusion. Therefore, a cap film for copper wiring 40, a so-called protective film 42, is formed on the multilayer wiring layer 41. In the steps so far, the first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 in the semi-finished state is formed.

On the other hand, as shown in FIG. 5, a logic circuit 25 including a signal processing circuit for processing a signal in a semi-finished product state is formed in each chip portion of the second semiconductor substrate (semiconductor wafer) 45. That is, a plurality of MOS transistors constituting a logic circuit are formed in the p-type semiconductor well region 46 on the surface side of the semiconductor substrate (for example, a silicon substrate) 45 so as to be separated by the element separation region 50. Here, a plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, and Tr8. Each MOS transistor Tr6, Tr7, and Tr8 is formed to have a pair of n-type source / drain regions 47 and a gate electrode 48 formed via a gate insulating film. The logic circuit 25 can be composed of CMOS transistors.

Next, a first layer of the interlayer insulating film 49 is formed on the surface of the semiconductor substrate 45, and then a connection hole is formed in the interlayer insulating film 49 to form a connecting conductor 54 to be connected to a required transistor. When forming the connecting conductors 54 having different heights, the first insulating thin film film 43a, for example, a silicon oxide film, and the second insulating thin film film 43b, which serves as an etching stopper, for example, silicon nitride, are formed on the entire surface including the upper surface of the transistor, as described above. Laminate the membrane. The first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, connection holes having different depths are selectively formed in the interlayer insulating film 39 of the first layer up to the second insulating thin film 43b which serves as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each portion so as to be continuous with each connection hole to form the connection hole. Then, the connection conductor 44 is embedded in each connection hole.
On the other hand, at a required position in the region to be each chip portion, a connection hole is formed from the surface of the interlayer insulating film 49 of the first layer to a desired depth position in the semiconductor substrate 45, and a connection hole is formed in the connection hole for a take-out electrode. The connecting conductor 51 of is embedded. The connecting conductor 51 can be formed of, for example, copper (Cu), tungsten (W), polysilicon, or the like. Before embedding the connecting conductor 51, an insulating film 52 for insulating the connecting conductor 51 and the semiconductor substrate 45 is formed and placed on the inner wall surface of the connecting hole.

Next, a plurality of layers, in this example, a three-layer metal wiring 53 are formed via the interlayer insulating film 49 so as to be connected to each connection conductor 54 and the connection conductor 51 for taking out the electrodes to form the multilayer wiring layer 55. .. The metal wiring 53 is formed of copper (Cu) wiring. Similar to the above, the cap film of the copper wiring 53, the so-called protective film 56, is formed on the multilayer wiring layer 49. In the steps so far, the second semiconductor substrate 45 having the logic circuit 25 in the semi-finished state is formed.

Next, as shown in FIG. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other so that the multilayer wiring layers 41 and 55 face each other. The bonding includes, for example, plasma bonding and bonding with an adhesive. In the case of plasma bonding, as shown in FIG. 7, a plasma TEOS film, a plasma SiN film, a SiON film (block film), or a SiC film are formed on the bonding surfaces of the first semiconductor wafer 31 and the second semiconductor wafer 45, respectively. And the like to form a film 57. The bonding surfaces on which the film 57 is formed are plasma-treated and superposed, and then annealed to bond the two. The bonding process is preferably performed by a low temperature process of 400 ° C. or lower, which does not affect wiring or the like. In the case of adhesive bonding, as shown in FIG. 8, an adhesive layer 58 is formed on one of the bonding surfaces of the first and second semiconductor wafers 31 and 45, and the adhesive layer 58 is laminated via the adhesive layer 58. Join the two. In this example, they are bonded by plasma bonding.

Next, as shown in FIG. 9, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31b side of the first semiconductor substrate 31. This thin film is performed so that the photodiode (PD) faces. After thinning the film, a p-type semiconductor layer for suppressing dark current is formed on the back surface of the photodiode (PD). The thickness of the semiconductor substrate 31 is, for example, about 600 μm, but the thickness is thinned to, for example, about 1 μm to 10 μm, preferably about 1 μm to 5 μm. Conventionally, such thinning has been performed by laminating a separately prepared support substrate. However, in the present embodiment, the second semiconductor substrate 45 on which the logic circuit 25 is formed is also used as the support substrate, and the thinning of the first semiconductor substrate 31 is performed. After thinning, an interlayer insulating film 59 made of, for example, a silicon oxide film is formed on the back surface of the substrate. The back surface 31b of the first semiconductor substrate 31 is a light incident surface when configured as a back-illuminated solid-state image sensor.

Next, as shown in FIG. 10, with respect to the thinned first semiconductor substrate 31, the second semiconductor substrate 31 is passed through the first semiconductor substrate 31 from the back surface 31b side at a required position in the region to be each chip portion. A through connection hole 61 that reaches the wiring 53 on the uppermost layer of the semiconductor substrate 45 of the above is formed. At the same time, a connection hole 62 is formed in the first semiconductor substrate 31 in the vicinity of the through connection hole 61 to reach the wiring 40 of the first layer from the back surface 31b side to the first semiconductor substrate 31 side. The contact diameter of the through connection hole 61 and the connection hole 62 can be formed in a size of 1 to 5 μm. Since the through connection hole 61 and the connection hole 62 are formed after the first semiconductor substrate 31 is thinned, the aspect ratio is reduced and the connection hole 62 can be formed as fine holes. The contact depth of the through connection hole 61 and the connection hole 62 can be, for example, about 5 μm to 15 μm. Next, an insulating film 63 for electrically insulating from the semiconductor substrate 31 is formed on the inner wall surface of the through connection hole 61 and the connection hole 62.

At this point, the process of manufacturing the pixel array has not yet undergone the on-chip color filter and on-chip microlens processing processes, and is incomplete. At the same time, the connection holes 61 and 62 can be machined and formed as an extension of the conventional wafer process. On the other hand, even in the logic circuit, the process up to the wiring 53 of the uppermost layer, which is optimal as a circuit technique, is not completed. This makes it possible to reduce manufacturing costs.

Next, as shown in FIG. 11, the through connection conductor 64 and the connection conductor 65 are embedded in the through connection hole 61 and the connection hole 62. As the through-connecting conductor 64 and the connecting conductor 65, for example, a metal such as copper (Cu) or tungsten (W) can be used. After that, the insulating protective film 66 is formed on the entire back surface of the first semiconductor substrate 31. As the insulating protective film 66, for example, a SiCN film, a plasma / silicon nitride film, a SiC film, or the like can be used.

Next, as shown in FIG. 12, a light-shielding film 67 is formed on the region to be light-shielded. In the figure, it is schematically formed on the control circuit 24, but it is also formed on other pixel transistors. As the light-shielding film 67, a metal film such as tungsten can be used. The light-shielding film 67 can be electrically connected to the semiconductor well region 32 having a ground potential, and the light-shielding film 67 can be prevented from being electrically in a floating state. Further, by applying a ground potential to the light-shielding film 67 electrically connected to the semiconductor well region 32, it is possible to prevent the semiconductor well region 32 from being electrically in a floating state. A passivation film 68 is formed on the entire surface so as to cover the light-shielding film 67. As the passivation film 68, for example, a plasma / silicon nitride film, a CVD-SiV film, or the like is used. Next, a connection hole 69 is formed in a portion of the passivation film 68 and the insulation protection film 66 corresponding to the through connection conductor 64 and the connection conductor 65, and then the connection wiring 72 made of an aluminum film is formed via the barrier metal film 71. The barrier metal film 71 is formed of, for example, a Ti (bottom) / TiN (top) laminated film. The connection wiring 72 is connected to the through connection conductor 64 and the connection conductor 65 through the connection hole 71. The connection wiring 72 is used for connecting the pixel region 23 and the control circuit 24 to the logic circuit 25, and also serves as a take-out electrode from the upper surface, a so-called electrode pad. Hereinafter, the connection wiring 72 is referred to as an electrode pad.

Therefore, the image sensor composed of the pixel region 23 and the control circuit 24 formed on the first semiconductor substrate 31 and the logic circuit 25 formed on the second semiconductor substrate 45 are formed by the connection conductor 65, the electrode pad 72, and the penetration. It is electrically connected through the connecting conductor 64. After that, the flattening film 73 is formed.

Next, as shown in FIG. 13, for example, red (R), green (G), and blue (B) on-chip color filters 74 are formed on the flattening film 73 corresponding to each pixel, and the on-chip color filters 74 are formed on the on-chip color filters 74. The on-chip microlens 75 is formed. Each on-chip color filter 74 and on-chip microlens 75 are formed corresponding to each unit pixel of the pixel array. Note that FIG. 12 shows an enlarged substrate cross-sectional structure excluding the on-chip color filter 74 and the on-chip microlens 75 in order to facilitate understanding of the present embodiment. Therefore, the pitch dimensions of the on-chip color filter 74 and the on-chip microlens 75 are reduced and displayed with respect to the pitch dimension of the unit pixel.

Next, although not shown in FIG. 13, the lens material film 75a and the flattening film 73 are selectively removed by etching to expose the electrode pad 72. On the other hand, on the second semiconductor substrate 45 side, the surface is ground and polished to expose the surface of the connecting conductor 51 which is the take-out electrode. After the connecting conductor 51 of the second semiconductor substrate 45 forms the passivation film 76 on the exposed surface, an opening 77 corresponding to the connecting conductor 51 is formed, and a spherical electrode electrically connected to the connecting conductor 51 through the opening 77. The bump 78 is formed (see FIG. 3). In the first semiconductor substrate 31, the pixel region 23 and the control circuit 24 are in a finished product state. In the second semiconductor substrate 45, the logic circuit 25 is in a finished product state.

Next, each chip is divided into a back-illuminated solid-state image sensor 79 as shown in FIG.

In the solid-state image sensor 79 of the first embodiment, when the electrode pad 72 is used, it can be connected to the external wiring by wire bonding to the electrode pad 72, and when the electrode bump 78 is used, face-down bonding can be performed. Can be connected to external wiring at. The electrode pad 72 and the electrode bump 78 can be selected according to the user's wishes.

In the first embodiment, the inspection of the solid-state image sensor on the semiconductor wafer is performed by using the electrode pad 72. In addition, there are two inspections, one in the wafer state and the other in the final module state after cutting into chips.

According to the solid-state image sensor 79 and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control circuit 24 are formed in the chip portion from the first semiconductor substrate 31, and the chip from the second semiconductor substrate 45 is formed. A logic circuit 25 for signal processing is formed in the unit. Since the pixel array function and the logic function are formed on different chip portions in this way, the optimum process forming technique can be used for each of the pixel array and the logic circuit. Therefore, the performance of each of the pixel array and the logic circuit can be fully exhibited, and a high-performance solid-state image pickup device can be provided.

If the configuration of FIG. 2C is adopted, it is only necessary to form the pixel region 23 that receives light on the semiconductor chip portion 22, and the control circuit 24 and the logic circuit 25 can be separated and formed on the semiconductor chip portion 26. can. As a result, the optimum process technology for each functional chip can be independently selected, and the area of the product module can be reduced.

Since the conventional wafer process technology enables mixed mounting of a pixel array and a logic circuit, it is easy to manufacture.

The first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 and the second semiconductor substrate 45 having the logic circuit 25 are both bonded together in a semi-finished state, and the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate for thinning the first semiconductor substrate 31. As a result, it is possible to save parts and reduce the manufacturing process. Further, since the through connection hole is formed to reduce the thickness, the aspect ratio of the hole is reduced and the connection hole can be formed with high accuracy. Further, since the through connection conductor 61 and the connection conductor 62 are embedded in the through connection hole and the connection hole having a low impact ratio, not only a metal material such as tungsten (W) having a good covering property but also copper (for example, copper) having a poor covering property is used. A metal material such as Cu) can be used. That is, it is not restricted by the connecting conductor material. As a result, the pixel area and the control circuit can be electrically connected to the logic circuit with high accuracy. Therefore, it is possible to achieve mass productivity, reduce the manufacturing cost, and manufacture a high-performance solid-state image sensor.

<3. Second Embodiment>
[Configuration example of solid-state image sensor]
FIG. 14 shows a second embodiment of the semiconductor device according to the second embodiment of the present invention, that is, a MOS solid-state image sensor. In the solid-state image sensor 81 according to the second embodiment, the connection conductor 51, the insulating film 52, and the electrode bump 78 on the second semiconductor substrate 45 side in the first embodiment are omitted, and the solid-state image sensor 81 on the first semiconductor substrate 31 side is omitted. It is configured by forming only the electrode pad 72. A passivation film 76 is formed on the back surface of the second semiconductor substrate 45. Since other configurations are the same as those described in the first embodiment, the parts corresponding to those in FIG. 3 are designated by the same reference numerals and duplicate description will be omitted. Further, the solid-state image sensor 81 is manufactured in the first embodiment shown in FIGS. 4 to 13 except for the steps of not forming the connection hole for forming the connection conductor 51, the connection conductor 51, the insulating film 52, and the electrode bump 78. The manufacturing method of the form can be applied.

According to the solid-state image pickup device 81 according to the second embodiment, the solid-state image pickup device 81 is configured in the same manner as in the first embodiment except for the electrode bump 78, and therefore has the same effect as described in the first embodiment. In the second embodiment, it can be expected that the cost can be reduced by not forming the connection hole, the insulating film 62, and the connection conductor 61 on the circuit side of the logic in advance.

<4. Third Embodiment>
[Configuration example of solid-state image sensor]
FIG. 15 shows a third embodiment of the semiconductor device according to the third embodiment of the present invention, that is, the MOS solid-state image sensor. The solid-state image sensor 83 according to the third embodiment has a pixel region 23 and a control circuit 24 on the first semiconductor substrate 31 side and a second through connection conductor 84 formed on the first semiconductor substrate 31. It is configured by electrically connecting to the logic circuit 25 on the semiconductor substrate 45 side.

That is, from the back surface 31b side of the first semiconductor substrate, the wiring 53 of the uppermost layer of the second semiconductor substrate 45 is reached through the first semiconductor substrate 31, and partly of the uppermost layer of the first semiconductor substrate 31. A through connection hole 85 that reaches the wiring 40 is formed. After forming the insulating film 63 on the inner wall surface of the through connection hole 85, the through insulating film family connecting the wiring 40 on the pixel region 23 and the control circuit 24 side and the wiring 53 on the logic circuit 25 side in the through connection hole 85. The conductor 84 is embedded. In the first embodiment described above, the connecting conductor 65 is connected to the wiring 40 with the wiring 40 of the first layer serving as a connection end. However, in the second embodiment, since the through connection conductor 84 is connected to the wiring 40 of the uppermost layer, the wiring 40 of each layer is connected to each other so that the wiring 40 of the uppermost layer to be connected becomes the connection end. The wiring.

In the present embodiment, since the pixel region 23, the control circuit 24, and the logic circuit 25 are connected by one through connection conductor 84, the electrode pad 72 which is the uppermost connection wiring shown in the first embodiment is formed. The electrode pad 72 is omitted.

Since other configurations are the same as those described in the first embodiment, the parts corresponding to those in FIG. 3 are designated by the same reference numerals and duplicate description will be omitted. Further, the solid-state imaging device 83 is manufactured according to the first embodiment shown in FIGS. 4 to 13 except for the steps of forming the connecting conductor 65, the electrode pad 72, and the selective etching step of the lens material film 75a and the flattening film 73. The manufacturing method can be applied.

In the third embodiment, the inspection of the solid-state image sensor is performed using the electrode bumps from the connecting conductor 51.

According to the solid-state imaging device 83 according to the third embodiment, the pixel region 23 and the control circuit 24 are electrically connected to the logic circuit 25 by one through connection conductor 84, and the electrode pad 72 is omitted. Therefore, the configuration is simplified as compared with the first embodiment. In addition, the manufacturing man-hours are reduced. Therefore, the manufacturing cost can be further reduced. Other than that, the same effect as described in the first embodiment is obtained.

<5. Fourth Embodiment>
[Example of configuration of solid-state image sensor and example of manufacturing method thereof]
A semiconductor device according to a fourth embodiment of the present invention, that is, a MOS solid-state image pickup device, will be described with reference to FIGS. 16 and 17 to 21 together with a manufacturing method thereof.

In the fourth embodiment, first, as shown in FIG. 17, a semi-finished image sensor, that is, a pixel region 23 and a control circuit 24 are formed in a region to be a chip portion of the first semiconductor substrate 31. .. Since this forming step is the same as that of FIG. 4 in the above-described first embodiment, the same reference numerals are given to the portions corresponding to those in FIG. 4, and duplicate description will be omitted. However, in the present embodiment, the multilayer wiring layer 41 is formed on the first semiconductor substrate 31, but the process ends when the uppermost wiring 40 is formed. That is, the uppermost layer wiring 40 is exposed, and the protective film 42 shown in FIG. 4 is not formed on the exposed wiring 40.

On the other hand, as shown in FIG. 18, a logic circuit 25 for processing a signal in a semi-finished product state is formed in a region to be a chip portion of the second semiconductor substrate 45. Since this forming step is the same as that of FIG. 5 in the above-described first embodiment, the same reference numerals are given to the portions corresponding to those in FIG. 5, and duplicate description will be omitted. However, in the present embodiment, the multilayer wiring layer 55 is formed on the second semiconductor substrate 45, but the process ends when the uppermost wiring 53 is formed. That is, the wiring 53 on the uppermost layer is exposed, and the protective film 56 shown in FIG. 4 is not formed on the wiring 53.

Next, as shown in FIG. 19, the first semiconductor substrate 31 and the second semiconductor substrate 45 are placed between each other's wirings 40 and 53 so that the multilayer wiring layers 41 and 55 face each other. The insulating films 39 and 49 are bonded together so as to be bonded to each other. In this bonding step, the wirings 40 and 53 are copper (Cu) wirings, and the interlayer insulating films 39 and 49 are silicon oxide films. Then, both semiconductor substrates 31 and 45 are overlapped with each other so that the Cu wirings 40 and 53 are in direct contact with each other, heated while applying a required load, and both the Cu wirings 40 and 53 are directly joined. At the same time, the interlayer insulating films 39 and 49 are also bonded to each other. The heating temperature at this time is a temperature at which the Cu wiring is not damaged, for example, about 300 ° C.

Next, as shown in FIG. 20, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31b side of the first semiconductor substrate 31. This thin film is performed so that the photodiode (PD) faces. After thinning, an interlayer insulating film 59 made of, for example, a silicon oxide film is formed on the back surface of the substrate. Next, with respect to the thinned first semiconductor substrate 31, a connection hole 88 reaching the wiring 40 of the first layer from the back surface 31b side is formed at a required position in the region to be each chip portion, and the connection hole 88 is formed. An insulating film 63 is formed on the inner wall surface. After that, the connection hole 62 and the through connection hole 61 reaching the wiring 53 on the uppermost layer on the second semiconductor substrate 45 side are formed. Then, the connection conductor 65 and the through connection conductor 64 are embedded in the connection hole 62 and the through connection hole 61. After that, the insulating protective film 66 is formed on the entire surface surface of the first semiconductor substrate 31 on the back surface 31b side. The process of FIG. 20 is the same as that described in the above-mentioned steps of FIGS. 9 to 11, and the parts corresponding to those of FIGS. 9 to 11 are designated by the same reference numerals and duplicate description is omitted.

Next, as shown in FIG. 21, on the first semiconductor substrate 31 side, an electrode pad 72 and a light-shielding film 67 connected to the connecting conductor 62 and the through-connecting conductor 61 are formed, and further, a flattening film 73 and an on-chip are formed. The color filter 74 and the on-chip microlens 74 are formed. On the other hand, on the second semiconductor substrate side, the back surface of the substrate is ground and polished to expose the connecting conductor 51, a passivation film 76 is formed, and then an electrode bump 78 is formed on the connecting conductor 51 (see FIG. 16). The process of FIG. 21 is the same as that described in the process of FIG. 13 described above, and the same reference numerals are given to the portions corresponding to those of FIG. 13, and duplicate description is omitted.

Next, each chip is divided into a back-illuminated solid-state image sensor 91 as shown in FIG. In the present embodiment, the configuration shown in FIG. 2B is used, but the configuration shown in FIG. 2C can also be used.

According to the solid-state image sensor 91 and the manufacturing method thereof according to the fourth embodiment, the wirings 40 and 53 are directly bonded at the same time in the bonding step of the first and second semiconductor substrates 31 and 45, and the pixel region 23 and the pixel region 23 and The electrical connection between the control circuit 24 and the logic circuit 25 is completed. As a result, the number of manufacturing processes can be further reduced, and the manufacturing cost can be further reduced. Other than that, the same effect as described in the first embodiment is obtained.

<6. Fifth Embodiment>
[Semiconductor device configuration example and its manufacturing method example]
A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 22 and 23 to 28 together with a manufacturing method thereof. The semiconductor device of the present embodiment is a semiconductor device in which a first semiconductor integrated circuit and a second semiconductor integrated circuit are mixedly mounted.

In the fifth embodiment, first, as shown in FIG. 23, a semi-finished first semiconductor integrated circuit, in this example, is provided in a region to be a chip portion of the first semiconductor substrate (semiconductor wafer) 101. The logic circuit 102 is formed. That is, a plurality of MOS transistors Tr11, Tr12, and Tr13 are formed in each chip portion of the semiconductor well region 104 formed on the semiconductor substrate (for example, a silicon substrate) 103. Each of the MOS transistors Tr11 to Tr13 is configured to have a pair of source / drain regions 105 and a gate electrode 106 formed via a gate insulating film. Each MOS transistor Tr11 to Tr13 is separated by the element separation region 107.
The MOS transistors Tr11 to Tr13 are shown as representatives. The logic circuit 102 can be configured with a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when forming an n-channel MOS transistor, an n-type source / drain region is formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, a p-type source / drain region is formed in the n-type semiconductor well region.

As the first semiconductor integrated circuit, for example, a semiconductor memory circuit may be used instead of the logic circuit 102. In this case, the logic circuit, which is the second semiconductor integrated circuit described later, is used for signal processing of the semiconductor memory circuit.

Next, a multilayer wiring layer 111 in which a plurality of layers, in this example, three layers of metal wiring 109 are laminated via an interlayer insulating film 108 is formed on the conductor substrate 103. The metal wiring 109 can be, for example, copper (Cu) wiring. The MOS transistors Tr11 to Tr13 are connected to the required first layer wiring 109 via the continuation conductor 112. Further, the three-layer wiring 109 is connected to each other via a connecting conductor. A cap film for suppressing the diffusion of the copper wiring 109, a so-called protective film 114, is formed on the multilayer wiring layer 113.

On the other hand, as shown in FIG. 24, a semi-finished second semiconductor integrated circuit, in this example, a logic circuit 117 is formed in each chip portion of the second semiconductor substrate (semiconductor wafer) 116. That is, similarly to FIG. 20, a plurality of n-channel MOS transistors Tr21, Tr22, and Tr23 are formed in each chip portion of the semiconductor well region 119 formed on the semiconductor substrate (for example, a silicon substrate) 118. Each of the MOS transistors Tr21 to Tr23 is configured to have a pair of source / drain regions 121 and a gate electrode 122 formed via a gate insulating film. Each MOS transistor Tr21 to Tr23 is separated by the element separation region 123.
The MOS transistors Tr21 to Tr23 are shown as representatives. The logic circuit 117 can be configured with a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when forming an n-channel MOS transistor, an n-type source / drain region is formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, a p-type source / drain region is formed in the n-type semiconductor well region.

Next, a multilayer wiring layer 126 in which a plurality of layers, in this example, three layers of metal wiring 125 are laminated via an interlayer insulating film 124 is formed on the semiconductor substrate 118. The metal wiring 125 may be, for example, copper (Cu) wiring. The MOS transistors Tr21 to Tr23 are connected to the required first layer wiring 125 via the connecting conductor 112. Further, the three-layer wiring 125 is connected to each other via a connecting conductor.

Further, in the semiconductor substrate 118, a connection hole is formed from the surface of the interlayer insulating film 124 of the first layer to a desired depth position in the semiconductor substrate 118 at a required position in a region to be a chip portion, and this connection is formed. A connection conductor 128 for a take-out electrode is embedded in the hole. The connecting conductor 128 can be formed of, for example, copper (Cu), tungsten (W), polysilicon, or the like. Before embedding the connecting conductor 128, an insulating film 129 for insulating the connecting conductor 128 and the semiconductor substrate 118 is formed and placed on the inner wall surface of the connecting hole. Then, a cap film for suppressing the diffusion of the copper wiring 125, a so-called protective film 127, is formed on the multilayer wiring layer 126.

Next, as shown in FIG. 25, the first semiconductor substrate 101 and the second semiconductor substrate 116 are bonded to each other so that the multilayer wiring layers 111 and 126 face each other. The bonding can be performed by plasma bonding or adhesive bonding in the same manner as described above. In this example, a film 129 such as a plasma TEOS film, a plasma SiN film, a SiON film (block film), or a SiC film is formed on the bonded surfaces of the first and second semiconductor substrates 101 and 116, respectively, and plasma-bonded. Paste with.

Next, as shown in FIG. 26, one of the first semiconductor substrates 101 is ground and polished from the back surface side to form a thin film. When the thickness of the semiconductor substrate 101 is, for example, about 600 μm, the film thickness is reduced to, for example, about 5 to 10 μm.

Next, as shown in FIG. 27, with respect to the thinned first semiconductor substrate 101, the second semiconductor substrate 101 is passed through the first semiconductor substrate 101 from the back surface 101b side at a required position in a region to be a chip portion. A through connection hole 131 that reaches the wiring 125 on the uppermost layer of the semiconductor substrate 116 is formed. At the same time, a connection hole 132 is formed in the first semiconductor substrate 101 in the vicinity of the through connection hole 131 to reach the wiring 109 of the first layer from the back surface 101b side to the first semiconductor substrate 101 side. Since the through connection hole 131 and the connection hole 132 are formed after the first semiconductor substrate 101 is thinned, the aspect ratio is reduced and the connection holes 132 can be formed as fine holes. Next, an insulating film 133 for electrically insulating from the semiconductor substrate 101 is formed on the inner wall surface of the through connection hole 131 and the connection hole 132.

Then, the through connection conductor 134 and the connection conductor 135 are embedded in the through connection hole 131 and the connection hole 132. As the through-connecting conductor 134 and the connecting conductor 135, for example, a metal such as copper (Cu) or tungsten (W) can be used.

Next, as shown in FIG. 28, a connection wiring 136 for connecting the through connection conductor 134 and the connection conductor 135 is formed on the back surface of the first semiconductor substrate 101. The first semiconductor integrated circuit 102 and the second semiconductor integrated circuit 117 are electrically connected through the connecting conductor 135, the through connecting conductor 134, and the connecting wiring 136. The connection wiring 136 is an electrode pad that serves as a take-out electrode. An overcoat film 139 with an insulating film is formed on the surface excluding the connection wiring 136. As the overcoat film 139, for example, a plasma silicon nitride film can be used. On the other hand, on the side of the second semiconductor substrate 116, the surface is ground and polished to expose the surface of the connecting conductor 128 which is the take-out electrode. After the connecting conductor 128 of the second semiconductor substrate 116 forms the passivation film 137 on the exposed surface, a spherical electrode bump 138 connected to the connecting conductor 128 is formed (see FIG. 22).

Next, each chip is divided into the target semiconductor device 140 shown in FIG. 22.

According to the semiconductor device 140 and the manufacturing method thereof according to the fifth embodiment, the first semiconductor integrated circuit and the second semiconductor integrated circuit are formed on different chip portions by the optimum process technology, respectively, as described above. It is possible to provide a high-performance semiconductor integrated circuit. In addition, the manufacturing cost is reduced by laminating the first and second semiconductor wafers in a semi-finished state, thinning them, and after electrical connection of the first and second semiconductor integrated circuits, making them into chips as a finished product. It can be reduced.

In the fifth embodiment as well, it is also possible to bond the first and second semiconductor substrates so as to directly join the wirings of the multilayer wiring layer to each other, as in the fourth embodiment described above. .. With this configuration, the number of manufacturing processes can be further reduced, and the manufacturing cost can be further reduced.

In the solid-state image pickup apparatus according to the first to fourth embodiments described above, the thickness of the semiconductor substrate of only the upper semiconductor well region 32 to which light is incident is the semiconductor substrate including the lower semiconductor well region 46. Thinner than the thickness of. The thickness of the first semiconductor substrate 31 including the upper semiconductor substrate and the multilayer wiring layer 41 is also thicker than the thickness of the second semiconductor substrate 45 including the semiconductor substrate and the multilayer wiring layer 55 on the lower side.
In the semiconductor device according to the fifth embodiment described above, the thickness of the upper semiconductor substrate 104 is thicker than the thickness of the lower semiconductor substrate 118. The thickness of the first semiconductor substrate 101 including the upper semiconductor substrate 104 and the multilayer wiring layer 111 is also thicker than the thickness of the second semiconductor substrate 116 including the lower semiconductor substrate 118 and the multilayer wiring layer 126.

In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductive type is a p-type, and the second conductive type is an n-type. Can also be applied to. In this case, the conductive type of each semiconductor substrate, semiconductor well region or semiconductor region is reversed, and the n-type is the first conductive type and the p-type is the second conductive type.

<7. 6th Embodiment>
[Example of electronic device configuration]
The solid-state imaging device according to the present invention described above can be applied to an electronic device such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. ..

FIG. 29 shows a sixth embodiment applied to a camera as an example of the electronic device according to the present invention. The camera according to the present embodiment is an example of a video camera capable of shooting a still image or a moving image. The camera 141 of the present embodiment includes a solid-state image pickup device 142, an optical system 143 that guides incident light to a light receiving sensor portion of the solid-state image pickup device 142, and a shutter device 144. Further, the camera 141 has a drive circuit 145 for driving the solid-state image pickup device 142 and a signal processing circuit 146 for processing the output signal of the solid-state image pickup device 142.

As the solid-state image sensor 142, any of the solid-state image sensors of each of the above-described embodiments is applied. The optical system (optical lens) 143 forms an image of image light (incident light) from the subject on the image pickup surface of the solid-state image pickup device 142. As a result, the signal charge is accumulated in the solid-state image sensor 142 for a certain period of time. The optical system 143 may be an optical lens system composed of a plurality of optical lenses. The shutter device 144 controls the light irradiation period and the light blocking period for the solid-state image pickup device 142. The drive circuit 145 supplies a drive signal that controls the transfer operation of the solid-state image sensor 142 and the shutter operation of the shutter device 144. The signal transfer of the solid-state image sensor 142 is performed by the drive signal (timing signal) supplied from the drive circuit 145. The signal processing circuit 146 performs various signal processing. The video signal that has undergone signal processing is stored in a storage medium such as a memory, or is output to a monitor.

According to the electronic device such as the camera according to the sixth embodiment, the solid-state image sensor 142 can be improved in performance and the manufacturing cost can be reduced, so that an inexpensive and highly reliable electronic device can be provided. Can be done.

1 ... Solid-state imaging device, 2 ... Pixels, 3 ... Pixel array (pixel area), 4 ... Vertical drive circuit, 5 ... Column signal processing circuit, 6 ... Horizontal drive circuit, 7 ... Output circuit, 8 ... Control circuit, 9 ... Vertical signal line, 10 ... Horizontal signal line, 12 ... Input / output terminal, 21 ... MOS solid-state imager, 22 ... First semiconductor chip section, 23 ... Pixel area , 24 ... control circuit, 25 ... logic circuit, 26 ... second semiconductor chip section, 31 ... first semiconductor wafer, PD ... photodiode, 39 ... interlayer insulating film, 40 ... wiring, 41 ... Multilayer wiring layer, 45 ... Second semiconductor wafer, 49 ... Interlayer insulation film, 53 ... Wiring, 49 ... Multilayer wiring layer, 61 ... Through connection hole, 62 ... Connection hole, 64 ...・ Through connection conductor, 65 ・ ・ Connection conductor, 72 ・ ・ Connection wiring (electrode pad), 74 ・ ・ On-chip color filter, 75 ・ ・ On-chip microlens, 78 ・ ・ Electrode bump, 79, 81, 83 ・ ・Back-illuminated solid-state imaging device, 140 ... semiconductor device, 141 ... camera

The present invention relates to semiconductor devices and electronic devices .

In view of the above points, the present invention provides a semiconductor device and an electronic device that fully exhibit their respective performances to improve their performance, and are capable of mass productivity and cost reduction.

The semiconductor device of the present invention has a first semiconductor substrate having a photoelectric conversion unit and a pixel transistor, a second semiconductor substrate having a logic circuit for performing signal processing, and the optical incident surface of the first semiconductor substrate. The first multilayer wiring layer formed on the side, the first wiring formed on the uppermost layer of the first multilayer wiring layer, and the first wiring formed on the first multilayer wiring layer are formed below the first wiring. The second wiring, the second multilayer wiring layer formed on the light incident surface side of the second semiconductor substrate, and the third wiring and the fourth wiring formed on the uppermost layer of the second multilayer wiring layer. The third wiring of the second multilayer wiring layer, the fifth wiring formed in the layer below the fourth wiring, and the first semiconductor substrate and the first semiconductor substrate from the light incident surface side of the first semiconductor substrate. It includes a first connection hole formed through the one multilayer wiring layer, and a first connection conductor embedded in the first connection hole. The first semiconductor substrate and the second semiconductor substrate are laminated so that the first multilayer wiring layer and the second multilayer wiring layer face each other, and the first wiring of the first multilayer wiring layer and the second The third wiring of the multilayer wiring layer is directly joined, and the first connecting conductor and the fourth wiring of the second multilayer wiring layer are directly joined.
Further, the electronic device of the present invention includes the semiconductor device, an optical system for guiding incident light to the photoelectric conversion unit of the semiconductor device, and a signal processing circuit for processing the output signal of the semiconductor device.

According to the present invention, since a pixel array and a logic circuit that sufficiently exhibit their respective performances are formed in each chip portion, a high-performance semiconductor device, that is, a back-illuminated semiconductor device and an electronic device are provided. Can be done.

Claims (1)

A pixel array including a photoelectric conversion unit, and a first semiconductor substrate having at least one of a transfer transistor, a reset transistor, and an amplification transistor.
A second semiconductor substrate having a logic circuit that performs signal processing,
The first multilayer wiring layer formed on the side opposite to the light incident surface of the first semiconductor substrate,
It has a second multilayer wiring layer formed on the light incident surface side of the second semiconductor substrate, and has.
The first semiconductor substrate and the second semiconductor substrate are laminated so that the first multilayer wiring layer and the second multilayer wiring layer face each other.
The first of the first multilayer wiring layers in each of the pixel region including the pixel array and the region outside the pixel region of the chip on which the first semiconductor substrate and the second semiconductor substrate are laminated. A solid-state imaging device in which at least one or more wirings on the semiconductor substrate side of 2 and at least one or more wirings on the first semiconductor substrate side of the second multilayer wiring layer are directly bonded.

Images