JP2015156516A - Semiconductor device, and backside-illumination semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which high performance is achieved by exhibiting each performance sufficiently, while achieving mass productivity and cost reduction.

SOLUTION: In a semiconductor device having a backside-illumination solid-state imaging device including a first semiconductor wafer including a pixel array, a second semiconductor wafer including a logic circuit, and a first coupling conductor for connecting the pixel array and the logic circuit electrically, the first semiconductor wafer and second semiconductor wafer are bonded integrally, the pixel array and logic circuit are connected electrically, and the first coupling conductor connects the lowermost layer of the first semiconductor wafer and the uppermost layer of the second semiconductor wafer.

COPYRIGHT: (C)2015,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a solid-state imaging device and a back-illuminated semiconductor device.

  As a solid-state imaging device, an amplification-type solid-state imaging device represented by a MOS type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is known. In addition, a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) from the viewpoint of low power supply voltage and power consumption.

  The MOS type solid-state imaging device includes a pixel array (pixel region) in which unit pixels are formed by a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors, and the unit pixels are arranged in a two-dimensional array, and a peripheral area. It has a circuit area. The plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.

  Conventionally, in such a MOS type solid-state imaging device, a semiconductor chip in which a pixel region in which a plurality of pixels are arranged is formed and a semiconductor chip in which a logic circuit for performing signal processing is electrically connected to each other. Various solid-state imaging devices configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a back-illuminated image sensor chip having a micropad for each pixel cell and a signal processing chip in which a signal processing circuit is formed and having a micropad are connected by microbumps. ing. In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state imaging device provided with an imaging pixel unit, and a signal processing chip provided with a peripheral circuit for signal processing are mounted on an interposer (intermediate substrate). A device is disclosed. Patent Document 3 has a configuration including an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. A configuration is disclosed in which the thin film circuit board and the logic circuit chip are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip through a through-hole via.

  Patent Document 4 discloses a solid-state imaging device in which a through-electrode is provided in a solid-state imaging device supported by a transparent substrate, and the solid-state imaging device is electrically connected to a flexible circuit board via the through-electrode. Furthermore, Patent Document 5 discloses a configuration in which an electrode penetrating a support substrate is provided in a back-illuminated solid-state imaging device.

  As shown in Patent Documents 1 to 3, various techniques for mounting different types of circuit chips such as an image sensor chip and a logic circuit have been proposed. The conventional technique is characterized in that the functional chips are almost completed, and through-holes are formed so that the chips can be interconnected on one chip. Yes.

JP 2006-49361 A JP 2007-13089 A JP 2008-130603 A Japanese Patent No. 40000507 JP 2003-31785 A

  As seen in the above-described conventional solid-state imaging device, it has been known as an idea to configure a semiconductor device by connecting different types of chips with a connection conductor penetrating the substrate. However, it is necessary to open a connection hole while ensuring insulation on a deep substrate, and it has been difficult to put it to practical use because of the cost efficiency of the manufacturing process required for processing the connection hole and embedding the connection conductor.

  On the other hand, in order to form a small contact hole of about 1 μm, for example, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning the film and cost increase are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is necessary to use a CVD film having good coverage such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

  In order to have economic efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to make it easier to form, and it is processed within the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select a technology that can be used.

Further, in a solid-state imaging device or the like, it is desired that an image region and a logic circuit that performs signal processing are formed so as to sufficiently exhibit their respective performances, thereby improving performance.
It is desired that not only the solid-state imaging device but also a semiconductor device having another semiconductor integrated circuit be formed so that the performance of each semiconductor integrated circuit can be sufficiently exerted to improve the performance.

  In view of the above points, the present invention provides a semiconductor device such as a solid-state imaging device, which achieves high performance by sufficiently exhibiting the respective performances, and achieves mass productivity and cost reduction.

  A semiconductor device of the present invention includes a first semiconductor wafer including a pixel array, a second semiconductor wafer including a logic circuit, and a first connection conductor that electrically connects the pixel array and the logic circuit. A semiconductor device having a back-illuminated solid-state imaging device, wherein the first semiconductor wafer and the second semiconductor wafer are joined together, and the pixel array and the logic circuit are electrically connected, The first connecting conductor connects the lowermost layer of the first semiconductor wafer and the uppermost layer of the second semiconductor wafer.

  The back-illuminated semiconductor device of the present invention includes a first semiconductor wafer having a pixel array, a second semiconductor wafer having a logic circuit, and a first connecting conductor that electrically connects the pixel array and the logic circuit. A semiconductor device having a back-illuminated solid-state imaging device, wherein the first semiconductor wafer and the second semiconductor wafer are integrally bonded, and one surface is the first and second The pixel array and the logic circuit are electrically connected by a conductor so as to be exposed at any bonding surface of the wafer, and the first coupling conductor is connected to the bottom layer of the first semiconductor wafer and the second layer. The uppermost layer of the semiconductor wafer is connected.

  According to the present invention, since a pixel array and a logic circuit that sufficiently exhibit each performance are formed in each chip portion, a high-performance semiconductor device, that is, a back-illuminated solid-state imaging device can be provided. In addition, a high-performance back-illuminated semiconductor device that is excellent in mass productivity and low in cost can be provided.

It is a schematic block diagram which shows an example of the MOS solid-state imaging device applied to this invention. 1 is a schematic diagram of a solid-state imaging device according to an embodiment of the present invention. It is a schematic block diagram of the principal part which shows the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 1) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 2) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 3) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 4) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 5) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 6) which shows the example of a manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 7) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 8) which shows the solid-state imaging device which concerns on 1st Embodiment, and its manufacturing method. It is a manufacturing process figure (the 9) which shows the example of a manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 10) which shows the example of a manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a block diagram of the solid-state imaging device which concerns on 2nd Embodiment. It is a block diagram of the solid-state imaging device which concerns on 3rd Embodiment. It is a schematic block diagram of the principal part which shows the solid-state imaging device which concerns on 4th Embodiment. It is a manufacturing process figure (the 1) which shows the example of a manufacturing method of the solid imaging device concerning a 4th embodiment. It is a manufacturing-process figure (the 2) which shows the example of a manufacturing method of the solid-state imaging device which concerns on 4th Embodiment. It is a manufacturing process figure (the 3) which shows the example of a manufacturing method of the solid-state imaging device concerning a 4th embodiment. It is a manufacturing process figure (the 4) which shows the example of a manufacturing method of the solid-state imaging device concerning a 4th embodiment. It is a manufacturing process figure (the 5) which shows the example of a manufacturing method of the solid-state imaging device concerning 4th Embodiment. It is a schematic block diagram of the principal part of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process figure (the 1) which shows the example of a manufacturing method of the semiconductor device concerning a 5th embodiment. It is a manufacturing process figure (the 2) which shows the example of the manufacturing method of the semiconductor device concerning a 5th embodiment. It is a manufacturing process figure (the 3) which shows the example of the manufacturing method of the semiconductor device concerning a 5th embodiment. It is a manufacturing process figure (the 4) which shows the example of a manufacturing method of the semiconductor device concerning a 5th embodiment. It is a manufacturing process figure (the 5) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a manufacturing process figure (the 6) which shows the example of the manufacturing method of the semiconductor device which concerns on 5th Embodiment. It is a schematic block diagram which shows the electronic device which concerns on 6th Embodiment.

Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Schematic configuration example of MOS solid-state imaging device First Embodiment (Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same)
3. Second Embodiment (Configuration Example of Solid-State Imaging Device)
4). Third embodiment (configuration example of solid-state imaging device)
5. Fourth Embodiment (Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same)
6). Fifth Embodiment (Configuration Example of Semiconductor Device and Method for Manufacturing the Same)
7). Sixth Embodiment (Configuration Example of Electronic Device)

<1. Schematic configuration example of MOS solid-state imaging device>
FIG. 1 shows a schematic configuration of a MOS solid-state imaging device applied to the semiconductor device of the present invention. This MOS solid-state imaging device is applied to the solid-state imaging device of each embodiment. As shown in FIG. 1, the solid-state imaging device 1 of this example includes a pixel region (a so-called pixel array) in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a semiconductor substrate 11, for example, a silicon substrate. ) 3 and a peripheral circuit section. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors. Since the equivalent circuit of the unit pixel is the same as usual, the detailed description is omitted. The pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other shared pixel transistor. That is, in the shared pixel, a photodiode and a transfer transistor that constitute a plurality of unit pixels are configured by sharing each other pixel transistor.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows, and according to the amount of light received in, for example, a photodiode serving as a photoelectric conversion unit of each pixel 2 through the vertical signal line 9. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, and AD conversion for removing fixed pattern noise unique to the pixel 2. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

  FIG. 2 shows a basic schematic configuration of a MOS solid-state imaging device according to the present invention. As shown in FIG. 2A, a conventional MOS solid-state imaging device 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. . Normally, the image sensor 156 is configured by the pixel region 153 and the control circuit 154. On the other hand, as shown in FIG. 2B, the MOS solid-state imaging device 21 according to the embodiment of the present invention includes the pixel region 23 and the control circuit 24 mounted on the first semiconductor chip unit 22, and the second semiconductor A logic circuit 25 including a signal processing circuit for signal processing is mounted on the chip unit 26. The first and second semiconductor chips 22 and 26 are electrically connected to each other to configure the MOS solid-state imaging device 21 as one semiconductor chip. In the MOS solid-state imaging device 27 according to another embodiment of the present invention, as shown in FIG. 2C, the pixel region 23 is mounted on the first semiconductor chip portion 22, and the control circuit 24 is connected to the second semiconductor chip portion 26. A logic circuit 25 including a signal processing circuit is mounted. The first and second semiconductor chips 22 and 26 are electrically connected to each other to constitute a MOS solid-state imaging device 27 as one semiconductor chip.

  As will be described later, the MOS solid-state imaging device according to the above-described embodiment has a feature in its manufacturing method and the configuration obtained based on this manufacturing method.

<2. First Embodiment>
[Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same]
The semiconductor device according to the first embodiment of the present invention, that is, the MOS solid-state imaging device will be described together with the manufacturing method thereof with reference to FIGS. 3 and 4 to 13.

  In the first embodiment, first, as shown in FIG. 4, an image sensor, that is, a pixel array (in a semi-finished state) is formed in each chip portion of a first semiconductor wafer (hereinafter referred to as a semiconductor substrate) 31. The pixel area 23) and the control circuit 24 are formed. That is, a photodiode (PD) serving as a photoelectric conversion unit of each pixel is formed in a region serving as each chip unit of a semiconductor substrate (for example, a silicon substrate) 31, and a source / drain region of each pixel transistor is formed in the semiconductor well region 32. 33 is formed. The semiconductor well region 32 is formed by introducing a first conductivity type, for example, a p-type impurity, and the source / drain region 33 is formed by introducing a second conductivity type, for example, an n-type impurity. The photodiode (PD) and the source / drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

  The photodiode (PD) is formed having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side. A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by the source / drain regions 33 paired with the gate electrode. In FIG. 4, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. A pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD). Each unit pixel 30 is separated by an element isolation region 38. The element isolation region 38 is so-called LOCOS in which the semiconductor substrate 31 is oxidized to form a silicon oxide film, STI (Shallow Trench Isolation) in which a groove is opened in the semiconductor substrate 31 and the silicon oxide film is buried in the groove, It is formed of an impurity diffusion layer having a conductivity type different from that of the diffusion layer to be a node.

  On the other hand, on the control circuit 24 side, a MOS transistor constituting the control circuit is formed on the semiconductor substrate 31. In FIG. 3, the MOS transistors constituting the control circuit 23 are represented by the MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed through a gate insulating film.

  Next, a first interlayer insulating film 39 is formed on the surface of the semiconductor substrate 31, and then a connection hole is formed in the interlayer insulating film 39 to form a connection conductor 44 connected to a required transistor. When the connection conductors 44 having different heights are formed, the first insulating thin film 43a, for example, a silicon oxide film, and contact openings connected to the gate electrodes 36 and the source / drain regions 33 (later connected conductors 44) are formed on the entire surface including the transistor upper surface. A second insulating thin film 43b, for example, a silicon nitride film, which serves as an etching stopper in the etching for filling is laminated. A first interlayer insulating film 39 is formed on the second insulating thin film 43b. Then, connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched at each portion so as to be continuous with each connection hole, thereby forming a connection hole. Then, the connection conductor 44 is embedded in each connection hole. When the etching stopper in the contact opening is not necessary, the second insulating thin film 43b can be omitted.

  Next, a multilayer wiring layer 41 is formed by forming a plurality of layers, in this example, three layers of metal wirings 40 via an interlayer insulating film 39 so as to be connected to each connection conductor 44. The metal wiring 40 is formed of a copper (Cu) wiring. Normally, each copper wiring is covered with a barrier metal film that prevents Cu diffusion. Therefore, a cap film for the copper wiring 40, a so-called protective film 42 is formed on the multilayer wiring layer 41. The first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 in a semi-finished product state is formed by the steps so far.

  On the other hand, as shown in FIG. 5, a logic circuit 25 including a signal processing circuit for signal processing in a semi-finished product state is formed in a region to be each chip portion of the second semiconductor substrate (semiconductor wafer) 45. That is, a plurality of MOS transistors constituting a logic circuit are formed in the p-type semiconductor well region 46 on the surface side of the semiconductor substrate (for example, silicon substrate) 45 so as to be isolated by the element isolation region 50. Here, the plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, Tr8. Each of the MOS transistors Tr6, Tr7, Tr8 is formed having a pair of n-type source / drain regions 47 and a gate electrode 48 formed through a gate insulating film. The logic circuit 25 can be composed of CMOS transistors.

Next, a first interlayer insulating film 49 is formed on the surface of the semiconductor substrate 45, and then a connection hole is formed in the interlayer insulating film 49 to form a connection conductor 54 connected to a required transistor. When the connection conductors 54 having different heights are formed, the first insulating thin film film 43a, eg, a silicon oxide film, and the second insulating thin film film 43b serving as an etching stopper, eg, silicon nitride are formed on the entire surface including the upper surface of the transistor, as described above. Laminate the films. A first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched at each portion so as to be continuous with each connection hole, thereby forming a connection hole. Then, the connection conductor 44 is embedded in each connection hole.
On the other hand, a connection hole is formed from the surface of the first-layer interlayer insulating film 49 to a desired depth position in the semiconductor substrate 45 at a required position in each chip portion region. The connecting conductor 51 is embedded. The connection conductor 51 can be formed of, for example, copper (Cu), tungsten (W), polysilicon, or the like. Before the connection conductor 51 is embedded, an insulating film 52 for insulating the connection conductor 51 and the semiconductor substrate 45 is formed on the inner wall surface of the connection hole.

  Next, a multilayer wiring layer 55 is formed by forming a plurality of layers, in this example, three layers of metal wirings 53 via an interlayer insulating film 49 so as to be connected to each connection conductor 54 and electrode connection connection conductor 51. . The metal wiring 53 is formed of a copper (Cu) wiring. Similarly to the above, a cap film of the copper wiring 53, a so-called protective film 56 is formed on the multilayer wiring layer 49. Through the above steps, the second semiconductor substrate 45 having the logic circuit 25 in a semi-finished product is formed.

  Next, as shown in FIG. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded together so that the multilayer wiring layers 41 and 55 face each other. The bonding includes, for example, plasma bonding and bonding with an adhesive. In the case of plasma bonding, as shown in FIG. 7, a plasma TEOS film, plasma SiN film, SiON film (block film), or SiC film is formed on the bonding surface of the first semiconductor wafer 31 and the second semiconductor wafer 45, respectively. A film 57 such as is formed. The bonding surface on which the film 57 is formed is overlapped by plasma treatment, and then annealed to bond the two. The bonding process is preferably performed by a low-temperature process of 400 ° C. or lower that does not affect the wiring or the like. In the case of adhesive bonding, an adhesive layer 58 is formed on one of the bonding surfaces of the first and second semiconductor wafers 31 and 45 as shown in FIG. Join them together. In this example, bonding is performed by plasma bonding.

  Next, as shown in FIG. 9, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31 b side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. After thinning, a p-type semiconductor layer for dark current suppression is formed on the back surface of the photodiode (PD). The thickness of the semiconductor substrate 31 is, for example, about 600 μm, but it is thinned to be, for example, about 1 μm to 10 μm, preferably about 1 μm to 5 μm. Conventionally, such thinning has been performed by attaching a separately prepared support substrate. However, in the present embodiment, the first semiconductor substrate 31 is thinned by using the second semiconductor substrate 45 on which the logic circuit 25 is formed as a supporting substrate. After the thinning, an interlayer insulating film 59 made of, for example, a silicon oxide film is formed on the back surface of the substrate. The back surface 31b of the first semiconductor substrate 31 is a light incident surface when configured as a back-illuminated solid-state imaging device.

  Next, as shown in FIG. 10, the second semiconductor substrate 31 is penetrated through the first semiconductor substrate 31 from the back surface 31b side at a required position in the region to be the chip portion with respect to the thinned first semiconductor substrate 31. A through connection hole 61 reaching the uppermost wiring 53 of the semiconductor substrate 45 is formed. At the same time, a connection hole 62 is formed in the first semiconductor substrate 31 so as to be close to the through-connection hole 61 and reach the first layer wiring 40 on the first semiconductor substrate 31 side from the back surface 31b side. The contact diameters of the through-connection hole 61 and the connection hole 62 can be formed with a size of 1 to 5 μm. Since the through-connection hole 61 and the connection hole 62 are formed after the first semiconductor substrate 31 is thinned, the aspect ratio becomes small and can be formed as fine holes. The contact depth of the through-hole 61 or the connection hole 62 can be set to a depth of about 5 μm to 15 μm, for example. Next, an insulating film 63 for electrically insulating the semiconductor substrate 31 is formed on the inner wall surfaces of the through connection hole 61 and the connection hole 62.

  At this time, the manufacturing process of the pixel array has not yet been completed by the on-chip color filter and on-chip microlens processing steps. At the same time, the connection holes 61 and 62 can be processed and formed by extension of the conventional wafer process. On the other hand, in the logic circuit, the process up to the uppermost wiring 53, which is optimum as a circuit technology, is incomplete. This makes it possible to reduce manufacturing costs.

  Next, as shown in FIG. 11, the through connection conductor 64 and the connection conductor 65 are embedded in the through connection hole 61 and the connection hole 62. For example, a metal such as copper (Cu) or tungsten (W) can be used for the through connection conductor 64 and the connection conductor 65. Thereafter, an insulating protective film 66 is formed on the entire back surface of the first semiconductor substrate 31. As the insulating protective film 66, for example, a SiCN film, a plasma / silicon nitride film, a SiC film, or the like can be used.

  Next, as shown in FIG. 12, a light shielding film 67 is formed on the region to be shielded from light. In the figure, it is schematically formed on the control circuit 24, but it is also formed on the other pixel transistors. As the light shielding film 67, for example, a metal film such as tungsten can be used. The light shielding film 67 can be electrically connected to the semiconductor well region 32 having a ground potential, so that the light shielding film 67 can be prevented from being in an electrically floating state. In addition, by applying a ground potential to the light shielding film 67 electrically connected to the semiconductor well region 32, the semiconductor well region 32 can be prevented from being in an electrically floating state. A passivation film 68 is formed on the entire surface so as to cover the light shielding film 67. As the passivation film 68, for example, a plasma silicon nitride film, a CVD-SiV film, or the like is used. Next, after a connection hole 69 is formed in a portion of the passivation film 68 and the insulating protective film 66 corresponding to the through connection conductor 64 and the connection conductor 65, a connection wiring 72 made of an aluminum film is formed through the barrier metal film 71. The barrier metal film 71 is formed of, for example, a laminated film of Ti (lower) / TiN (upper). The connection wiring 72 is connected to the through connection conductor 64 and the connection conductor 65 through the connection hole 71. The connection wiring 72 is used to connect the pixel region 23 and the control circuit 24 to the logic circuit 25, and also serves as an extraction electrode from the upper surface, that is, a so-called electrode pad. Hereinafter, the connection wiring 72 is referred to as an electrode pad.

  Therefore, the image sensor composed of the pixel region 23 and the control circuit 24 formed on the first semiconductor substrate 31 and the logic circuit 25 formed on the second semiconductor substrate 45 are connected to the connection conductor 65, the electrode pad 72, and the through-hole. It is electrically connected through the connection conductor 64. Thereafter, a planarizing film 73 is formed.

  Next, as shown in FIG. 13, on-chip color filters 74 of, for example, red (R), green (G), and blue (B) are formed on the planarizing film 73 corresponding to the respective pixels, and on that, An on-chip microlens 75 is formed. Each on-chip color filter 74 and on-chip microlens 75 are formed corresponding to each unit pixel of the pixel array. In FIG. 12, in order to facilitate understanding of the present embodiment, the substrate cross-sectional structure excluding the on-chip color filter 74 and the on-chip microlens 75 is shown enlarged. Therefore, the pitch dimensions of the on-chip color filter 74 and the on-chip microlens 75 are reduced and displayed with respect to the pitch dimension of the unit pixel.

  Next, although not shown in FIG. 13, the lens material film 75a and the planarizing film 73 are selectively etched away to expose the electrode pads 72. On the other hand, on the second semiconductor substrate 45 side, the surface of the connection conductor 51 serving as an extraction electrode is exposed by grinding and polishing the surface. After forming the passivation film 76 on the exposed surface of the connection conductor 51 of the second semiconductor substrate 45, an opening 77 corresponding to the connection conductor 51 is formed, and a spherical electrode electrically connected to the connection conductor 51 through the opening 77. Bumps 78 are formed (see FIG. 3). In the first semiconductor substrate 31, the pixel region 23 and the control circuit 24 are in a finished product state. In the second semiconductor substrate 45, the logic circuit 25 is in a finished product state.

  Next, the chip is divided into chips to obtain the target back-illuminated solid-state imaging device 79 shown in FIG.

  In the solid-state imaging device 79 of the first embodiment, when the electrode pad 72 is used, the electrode pad 72 can be connected to an external wiring by wire bonding, and when the electrode bump 78 is used, face-down bonding is performed. Can be connected to external wiring. The electrode pad 72 and the electrode bump 78 can be selected according to the user's request.

  In the first embodiment, the inspection of the solid-state imaging device on the semiconductor wafer is performed using the electrode pad 72. The inspection is performed twice, that is, inspection in a wafer state and inspection in a final module state after cutting into chips.

  According to the solid-state imaging device 79 and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control circuit 24 are formed in the chip portion from the first semiconductor substrate 31, and the chip from the second semiconductor substrate 45 is formed. A logic circuit 25 for signal processing is formed in the part. As described above, since the pixel array function and the logic function are formed in different chip portions, an optimum process forming technique can be used for each of the pixel array and the logic circuit. Therefore, the performance of each of the pixel array and the logic circuit can be sufficiently exhibited, and a high-performance solid-state imaging device can be provided.

  If the configuration of FIG. 2C is adopted, it is only necessary to form the pixel region 23 that receives light on the semiconductor chip portion 22 side, and the control circuit 24 and the logic circuit 25 may be separated and formed in the semiconductor chip portion 26. it can. As a result, the optimum process technology for each functional chip can be selected independently, and the area of the product module can be reduced.

  Since the pixel array and the logic circuit can be mixedly mounted by the conventional wafer process technology, manufacturing is also easy.

  The first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 and the second semiconductor substrate 45 having the logic circuit 25 are bonded together in a semi-finished state, so that the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate when the first semiconductor substrate 31 is thinned. As a result, the members can be saved and the manufacturing process can be saved. Furthermore, since the through-connection hole is formed for thinning, the aspect ratio of the hole is reduced, and a highly accurate connection hole can be formed. Further, since the through connection conductor 61 and the connection conductor 62 are embedded in the through connection hole and the connection hole having a low aspect ratio, not only a metal material such as tungsten (W) with good coverage but also copper (for example, copper ( A metal material such as Cu) can be used. That is, the connection conductor material is not restricted. Thereby, the electrical connection between the pixel region and the control circuit and the logic circuit can be performed with high accuracy. Therefore, it is possible to manufacture a high-performance solid-state imaging device while achieving mass productivity, suppressing manufacturing costs.

<3. Second Embodiment>
[Configuration example of solid-state imaging device]
FIG. 14 shows a semiconductor device according to a second embodiment of the present invention, that is, a MOS solid-state imaging device according to a second embodiment. In the solid-state imaging device 81 according to the second embodiment, the connection conductor 51, the insulating film 52, and the electrode bump 78 on the second semiconductor substrate 45 side in the first embodiment are omitted, and the first semiconductor substrate 31 side is omitted. Only the electrode pad 72 is formed. A passivation film 76 is formed on the back surface of the second semiconductor substrate 45. Since the other configuration is the same as that described in the first embodiment, portions corresponding to those in FIG. The solid-state imaging device 81 is manufactured in the first embodiment shown in FIGS. 4 to 13 except for the step of not forming the connection hole for forming the connection conductor 51, the connection conductor 51, the insulating film 52, and the electrode bump 78. The manufacturing method of the form can be applied.

  Since the solid-state imaging device 81 according to the second embodiment is configured in the same manner as in the first embodiment except for the electrode bumps 78, the same effects as described in the first embodiment can be obtained. In the second embodiment, the cost can be expected to be reduced by not forming the connection hole, the insulating film 62 and the connection conductor 61 in advance on the logic circuit side.

<4. Third Embodiment>
[Configuration example of solid-state imaging device]
FIG. 15 shows a semiconductor device according to a third embodiment of the present invention, that is, a third embodiment of a MOS solid-state imaging device. The solid-state imaging device 83 according to the third embodiment includes the pixel region 23 and the control circuit 24 on the first semiconductor substrate 31 side, the second through-connection conductor 84 formed on the first semiconductor substrate 31, and the second It is configured by electrically connecting the logic circuit 25 on the semiconductor substrate 45 side.

  That is, the first semiconductor substrate 31 is penetrated from the back surface 31 b side of the first semiconductor substrate to reach the uppermost layer wiring 53 of the second semiconductor substrate 45, and a part of the uppermost layer of the first semiconductor substrate 31 is formed. A through-connection hole 85 reaching the wiring 40 is formed. After forming the insulating film 63 on the inner wall surface of the through-connection hole 85, the through-insulation film group connecting the wiring 40 on the pixel region 23 and the control circuit 24 side and the wiring 53 on the logic circuit 25 side in the through-connection hole 85. A conductor 84 is embedded. In the first embodiment described above, the connection conductor 65 is connected to the wiring 40 with the first-layer wiring 40 serving as a connection end. However, in the second embodiment, since the through connection conductor 84 is connected to the uppermost layer wiring 40, the wirings 40 of the respective layers are connected to each other so that the uppermost layer wiring 40 to be connected becomes a connection end. The

  In the present embodiment, since the pixel region 23 and the control circuit 24 are connected to the logic circuit 25 by one through connection conductor 84, the electrode pad 72 serving as the uppermost connection wiring shown in the first embodiment is formed. The electrode pad 72 is omitted.

  Since the other configuration is the same as that described in the first embodiment, portions corresponding to those in FIG. The solid-state imaging device 83 is manufactured in accordance with the first embodiment shown in FIGS. 4 to 13 except for the connection conductor 65 and the electrode pad 72 formation process and the lens material film 75a and the planarization film 73 selective etching process. A manufacturing method can be applied.

  In the third embodiment, the inspection for the solid-state imaging device is performed using the electrode bumps from the connection conductor 51.

  According to the solid-state imaging device 83 according to the third embodiment, the pixel region 23, the control circuit 24, and the logic circuit 25 are electrically connected by one through connection conductor 84, and the electrode pad 72 is omitted. Therefore, the configuration is simplified as compared with the first embodiment. In addition, the number of manufacturing steps can be reduced. Therefore, the manufacturing cost can be further reduced. In addition, the same effects as described in the first embodiment can be obtained.

<5. Fourth Embodiment>
[Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same]
A semiconductor device according to a fourth embodiment of the present invention, that is, a MOS solid-state imaging device will be described together with a manufacturing method thereof with reference to FIGS. 16 and 17 to 21.

  In the fourth embodiment, first, as shown in FIG. 17, an image sensor in a semi-finished state, that is, a pixel region 23 and a control circuit 24 are formed in the regions to be the chip portions of the first semiconductor substrate 31. . Since this formation process is the same as that of FIG. 4 in the first embodiment described above, the same reference numerals are given to portions corresponding to those of FIG. However, in the present embodiment, the multilayer wiring layer 41 is formed on the first semiconductor substrate 31, but the process ends when the uppermost wiring 40 is formed. That is, the uppermost wiring 40 is exposed, and the protective film 42 shown in FIG. 4 is not formed thereon.

  On the other hand, as shown in FIG. 18, a logic circuit 25 for signal processing in a semi-finished product state is formed in a region to be each chip portion of the second semiconductor substrate 45. Since this formation process is the same as that of FIG. 5 in the first embodiment described above, the same reference numerals are given to the portions corresponding to those of FIG. However, in the present embodiment, the multilayer wiring layer 55 is formed on the second semiconductor substrate 45, but the process ends when the uppermost layer wiring 53 is formed. That is, the uppermost wiring 53 is exposed, and the protective film 56 shown in FIG. 4 is not formed thereon.

  Next, as shown in FIG. 19, the first semiconductor substrate 31 and the second semiconductor substrate 45 are connected to each other between the wirings 40 and 53, and between the layers so that the multilayer wiring layers 41 and 55 face each other. The insulating films 39 and 49 are bonded together so that they are bonded to each other. In this bonding step, the wirings 40 and 53 are copper (Cu) wirings, and the interlayer insulating films 39 and 49 are silicon oxide films. Then, both the semiconductor substrates 31 and 45 are overlapped so that the Cu wirings 40 and 53 are in direct contact with each other, and heated while applying a required weight, so that both the Cu wirings 40 and 53 are directly joined. At the same time, the interlayer insulating films 39 and 49 are bonded together. The heating temperature at this time is set to a temperature at which the Cu wiring is not impaired, for example, about 300 ° C.

  Next, as shown in FIG. 20, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31 b side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. After the thinning, an interlayer insulating film 59 made of, for example, a silicon oxide film is formed on the back surface of the substrate. Next, a connection hole 88 reaching the first-layer wiring 40 from the back surface 31b side is formed at a required position in a region to be each chip portion with respect to the first semiconductor substrate 31 having a reduced thickness. An insulating film 63 is formed on the inner wall surface. After that, the connection hole 62 and the through-connection hole 61 reaching the uppermost layer wiring 53 on the second semiconductor substrate 45 side are formed. Then, the connection conductor 65 and the through connection conductor 64 are embedded in the connection hole 62 and the through connection hole 61. Thereafter, an insulating protective film 66 is formed on the entire surface on the back surface 31 b side of the first semiconductor substrate 31. The process of FIG. 20 is the same as that described in the process of FIGS. 9 to 11 described above, and portions corresponding to those of FIGS.

  Next, as shown in FIG. 21, on the first semiconductor substrate 31 side, an electrode pad 72 and a light shielding film 67 connected to the connection conductor 62 and the through connection conductor 61 are formed, and further, a planarization film 73 and an on-chip are formed. A color filter 74 and an on-chip microlens 74 are formed. On the other hand, on the second semiconductor substrate side, the back surface of the substrate is ground and polished to expose the connection conductor 51, and after forming the passivation film 76, electrode bumps 78 are formed on the connection conductor 51 (see FIG. 16). The process of FIG. 21 is the same as that described in the process of FIG. 13 described above, and portions corresponding to those in FIG.

  Next, the chip is divided into chips to obtain a target back-illuminated solid-state imaging device 91 shown in FIG. In the present embodiment, the configuration shown in FIG. 2B is used, but the configuration shown in FIG. 2C may be used.

  According to the solid-state imaging device 91 and the manufacturing method thereof according to the fourth embodiment, in the bonding process of the first and second semiconductor substrates 31 and 45, the wirings 40 and 53 are directly bonded simultaneously, and the pixel region 23 and The electrical connection between the control circuit 24 and the logic circuit 25 is completed. Thereby, the number of manufacturing steps can be further reduced, and the manufacturing cost can be further reduced. In addition, the same effects as described in the first embodiment can be obtained.

<6. Fifth embodiment>
[Configuration example of semiconductor device and manufacturing method thereof]
A semiconductor device according to a fifth embodiment of the present invention will be described together with a manufacturing method thereof with reference to FIGS. 22 and 23 to 28. The semiconductor device of this embodiment is a semiconductor device in which a first semiconductor integrated circuit and a second semiconductor integrated circuit are mixedly mounted.

In the fifth embodiment, first, as shown in FIG. 23, the first semiconductor integrated circuit in the semi-finished state, in this example, is formed in each chip portion of the first semiconductor substrate (semiconductor wafer) 101. A logic circuit 102 is formed. That is, a plurality of MOS transistors Tr11, Tr12, and Tr13 are formed in regions that become the chip portions of the semiconductor well region 104 formed on the semiconductor substrate (eg, silicon substrate) 103. Each of the MOS transistors Tr11 to Tr13 includes a pair of source / drain regions 105 and a gate electrode 106 formed through a gate insulating film. The MOS transistors Tr11 to Tr13 are isolated by the element isolation region 107.
The MOS transistors Tr11 to Tr13 are shown as representatives. The logic circuit 102 can be composed of CMOS transistors. Therefore, the plurality of MOS transistors can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, p-type source / drain regions are formed in the n-type semiconductor well region.

  The first semiconductor integrated circuit may be a semiconductor memory circuit, for example, instead of the logic circuit 102. In this case, a logic circuit serving as a second semiconductor integrated circuit described later is used for signal processing of the semiconductor memory circuit.

  Next, a multilayer wiring layer 111 is formed by laminating a plurality of layers, in this example, three layers of metal wirings 109, on the conductive substrate 103 via an interlayer insulating film 108. The metal wiring 109 can be a copper (Cu) wiring, for example. Each of the MOS transistors Tr11 to Tr13 is connected to a required first-layer wiring 109 via a connection 112. Further, the three layers of wiring 109 are connected to each other through a connection conductor. A cap film for suppressing diffusion of the copper wiring 109, a so-called protective film 114, is formed on the multilayer wiring layer 113.

On the other hand, as shown in FIG. 24, a second semiconductor integrated circuit in a semi-finished product state, in this example, a logic circuit 117 is formed in a region to be each chip portion of the second semiconductor substrate (semiconductor wafer) 116. That is, as in FIG. 20, a plurality of n-channel MOS transistors Tr21, Tr22, and Tr23 are formed in regions to be the chip portions of the semiconductor well region 119 formed on the semiconductor substrate (eg, silicon substrate) 118. Each of the MOS transistors Tr21 to Tr23 includes a pair of source / drain regions 121 and a gate electrode 122 formed through a gate insulating film. The MOS transistors Tr21 to Tr23 are isolated by an element isolation region 123.
The MOS transistors Tr21 to Tr23 are shown as representatives. The logic circuit 117 can be composed of a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, p-type source / drain regions are formed in the n-type semiconductor well region.

  Next, a multilayer wiring layer 126 in which a plurality of layers, in this example, three layers of metal wirings 125 are stacked on the semiconductor substrate 118 through an interlayer insulating film 124 is formed. The metal wiring 125 can be a copper (Cu) wiring, for example. Each of the MOS transistors Tr21 to Tr23 is connected to a required first-layer wiring 125 via a connection conductor 112. Further, the three layers of wiring 125 are connected to each other through a connection conductor.

  In addition, a connection hole is formed in the semiconductor substrate 118 from a surface of the interlayer insulating film 124 of the first layer to a desired depth position in the semiconductor substrate 118 at a required position in a region to be a chip portion. A connecting conductor 128 for the extraction electrode is embedded in the hole. The connection conductor 128 can be formed of, for example, copper (Cu), tungsten (W), polysilicon, or the like. Before the connection conductor 128 is embedded, an insulating film 129 for insulating the connection conductor 128 and the semiconductor substrate 118 is formed on the inner wall surface of the connection hole. Then, a cap film for suppressing diffusion of the copper wiring 125, a so-called protective film 127 is formed on the multilayer wiring layer 126.

  Next, as shown in FIG. 25, the first semiconductor substrate 101 and the second semiconductor substrate 116 are bonded so that the multilayer wiring layers 111 and 126 face each other. Bonding can be performed by plasma bonding or adhesive bonding in the same manner as described above. In this example, a film 129 such as a plasma TEOS film, a plasma SiN film, a SiON film (block film), or a SiC film is formed on the bonding surfaces of the first and second semiconductor substrates 101 and 116, respectively, and plasma bonding is performed. Paste together.

  Next, as shown in FIG. 26, one first semiconductor substrate 101 is thinned by grinding and polishing from the back surface side. When the thickness of the semiconductor substrate 101 is, for example, about 600 μm, the semiconductor substrate 101 is thinned so that the film thickness is, for example, about 5-10 μm.

  Next, as shown in FIG. 27, with respect to the thinned first semiconductor substrate 101, the second semiconductor substrate 101 penetrates the first semiconductor substrate 101 from the back surface 101 b side to a required position in a region to be a chip portion. A through-connection hole 131 reaching the uppermost wiring 125 of the semiconductor substrate 116 is formed. At the same time, a connection hole 132 is formed in the first semiconductor substrate 101 so as to be close to the through-connection hole 131 and reach from the back surface 101b side to the first-layer wiring 109 on the first semiconductor substrate 101 side. Since the through-connection hole 131 and the connection hole 132 are formed after the first semiconductor substrate 101 is thinned, the aspect ratio becomes small and can be formed as a fine hole. Next, an insulating film 133 for electrically insulating the semiconductor substrate 101 is formed on the inner wall surfaces of the through-connection hole 131 and the connection hole 132.

  Then, the through connection conductor 134 and the connection conductor 135 are embedded in the through connection hole 131 and the connection hole 132. For example, a metal such as copper (Cu) or tungsten (W) can be used for the through connection conductor 134 and the connection conductor 135.

  Next, as shown in FIG. 28, connection wiring 136 that connects the through connection conductor 134 and the connection conductor 135 is formed on the back surface of the first semiconductor substrate 101. The first semiconductor integrated circuit 102 and the second semiconductor integrated circuit 117 are electrically connected through the connection conductor 135, the through connection conductor 134, and the connection wiring 136. The connection wiring 136 serves as an electrode pad serving as an extraction electrode. An overcoat film 139 made of an insulating film is formed on the surface excluding the connection wiring 136. As this overcoat film 139, for example, a plasma silicon nitride film can be used. On the other hand, on the second semiconductor substrate 116 side, the surface is ground and polished to expose the surface of the connection conductor 128 serving as an extraction electrode. After forming the passivation film 137 on the exposed surface of the connection conductor 128 of the second semiconductor substrate 116, spherical electrode bumps 138 connected to the connection conductor 128 are formed (see FIG. 22).

  Next, the semiconductor device 140 is divided into chips to obtain the target semiconductor device 140 shown in FIG.

  According to the semiconductor device 140 and the manufacturing method thereof according to the fifth embodiment, the first semiconductor integrated circuit and the second semiconductor integrated circuit are respectively formed on different chip portions by the optimum process technology as described above. And a high-performance semiconductor integrated circuit can be provided. In addition, the first and second semiconductor wafers are bonded together in a semi-finished product state to form a thin film, and after electrical connection of the first and second semiconductor integrated circuits, a finished product state is formed into a chip, thereby reducing the manufacturing cost. Reduction can be achieved.

  In the fifth embodiment, as in the fourth embodiment described above, the first and second semiconductor substrates can be bonded together so that the wirings of the multilayer wiring layer are directly bonded to each other. . In this configuration, the number of manufacturing steps can be further reduced, and the manufacturing cost can be further reduced.

In the solid-state imaging device according to the first to fourth embodiments described above, the thickness of the semiconductor substrate including only the upper semiconductor well region 32 to which light is incident includes the semiconductor substrate including the lower semiconductor well region 46. Thinner than the thickness. The thickness of the first semiconductor substrate 31 including the upper semiconductor substrate and the multilayer wiring layer 41 is also thicker than the thickness of the second semiconductor substrate 45 including the lower semiconductor substrate and the multilayer wiring layer 55.
In the semiconductor device according to the fifth embodiment described above, the upper semiconductor substrate 104 is thicker than the lower semiconductor substrate 118. The thickness of the first semiconductor substrate 101 including the upper semiconductor substrate 104 and the multilayer wiring layer 111 is also thicker than the thickness of the second semiconductor substrate 116 including the lower semiconductor substrate 118 and the multilayer wiring layer 126.

  In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductivity type is a p-type, and the second conductivity type is an n-type, but the signal charge is a hole. It can also be applied to. In this case, the conductivity type of each semiconductor substrate, semiconductor well region or semiconductor region is reversed, n-type being the first conductivity type and p-type being the second conductivity type.

<7. Sixth Embodiment>
[Configuration example of electronic equipment]
The above-described solid-state imaging device according to the present invention can be applied to electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function. .

  FIG. 29 shows a sixth embodiment applied to a camera as an example of an electronic apparatus according to the invention. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 141 according to this embodiment includes a solid-state imaging device 142, an optical system 143 that guides incident light to a light receiving sensor unit of the solid-state imaging device 142, and a shutter device 144. Further, the camera 141 includes a drive circuit 145 that drives the solid-state imaging device 142 and a signal processing circuit 146 that processes an output signal of the solid-state imaging device 142.

  Any of the solid-state imaging devices of the above-described embodiments is applied to the solid-state imaging device 142. The optical system (optical lens) 143 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 142. As a result, signal charges are accumulated in the solid-state imaging device 142 for a certain period. The optical system 143 may be an optical lens system including a plurality of optical lenses. The shutter device 144 controls a light irradiation period and a light shielding period for the solid-state imaging device 142. The drive circuit 145 supplies a drive signal that controls the transfer operation of the solid-state imaging device 142 and the shutter operation of the shutter device 144. Signal transfer of the solid-state imaging device 142 is performed by a drive signal (timing signal) supplied from the drive circuit 145. The signal processing circuit 146 performs various types of signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic apparatus such as the camera according to the sixth embodiment, the solid-state imaging device 142 is improved in performance and the manufacturing cost is reduced, so that an inexpensive and highly reliable electronic apparatus is provided. Can do.

  1 .... Solid-state imaging device 2 .... Pixel 3 .... Pixel array (pixel area) 4 .... Vertical drive circuit 5 .... Column signal processing circuit 6 .... Horizontal drive circuit 7 .... Output circuit 8 .. Control circuit, 9... Vertical signal line, 10... Horizontal signal line, 12... I / O terminal, 21 .. MOS solid-state image pickup device, 22. 24..Control circuit 25..Logic circuit 26..Second semiconductor chip part 31..First semiconductor wafer PD..Photodiode 39..Interlayer insulating film 40..Wiring 41 .. Multi-layer wiring layer, 45 .. Second semiconductor wafer, 49 .. Interlayer insulating film, 53 .. Wiring, 49 .. Multi-layer wiring layer, 61 .. Through connection hole, 62.・ Penetration connection conductor, 65 ..Connection conductor, 72 ..Connection wiring (electrode pad), 74 On-chip color filter, 75 ... on-chip microlens, 78 ... electrode bump, 79,81,83 ... back-illuminated solid-state imaging device, 140 ... semiconductor device, 141 ... camera

A semiconductor device of the present invention includes a first semiconductor wafer including a pixel array, a second semiconductor wafer including a logic circuit, and a first connection conductor that electrically connects the pixel array and the logic circuit. A semiconductor device having a back-illuminated solid-state imaging device, wherein the first semiconductor wafer and the second semiconductor wafer are joined together, and the pixel array and the logic circuit are electrically connected, The first connection conductor connects the lowermost layer of the first semiconductor wafer and the uppermost layer of the second semiconductor wafer.

A back-illuminated semiconductor device according to the present invention includes a first semiconductor wafer having a pixel array, a second semiconductor wafer having a logic circuit, and a first connection conductor for electrically connecting the pixel array and the logic circuit. A semiconductor device having a back-illuminated solid-state imaging device, wherein the first semiconductor wafer and the second semiconductor wafer are integrally bonded, and one surface is the first and second The pixel array and the logic circuit are electrically connected by a conductor so as to be exposed at any bonding surface of the wafer, and the first connection conductor is connected to the bottom layer of the first semiconductor wafer and the second layer. The uppermost layer of the semiconductor wafer is connected.

Claims (18)

A first semiconductor wafer including a pixel array;
A second semiconductor wafer including a logic circuit;
A semiconductor device having a back-illuminated solid-state imaging device, comprising: a first connecting conductor that electrically connects the pixel array and the logic circuit;
Bonding the first semiconductor wafer and the second semiconductor wafer together;
The pixel array and the logic circuit are electrically connected;
The first connecting conductor is a semiconductor device that connects the lowermost layer of the first semiconductor wafer and the uppermost layer of the second semiconductor wafer.   The semiconductor device according to claim 1, wherein the first connection conductor passes through the first semiconductor wafer.   The semiconductor device according to claim 1, further comprising a second connecting conductor connected to the logic circuit.   The semiconductor device according to claim 3, wherein a surface of the second connecting conductor is exposed on a surface of the second semiconductor wafer.   The semiconductor device according to claim 4, comprising an electrode bump connected to the second connecting conductor.   The semiconductor device according to claim 3, wherein the second connecting conductor is connected to a lowermost layer of the second semiconductor wafer.   The semiconductor device according to claim 2, further comprising a second coupling conductor connected to the first coupling conductor in the first semiconductor wafer.   The semiconductor device according to claim 7, wherein the first connection conductor is connected to an uppermost layer of the second semiconductor wafer, and the second connection conductor is connected to an uppermost layer of the first semiconductor wafer.   The semiconductor device according to claim 7, wherein a surface of the first connection conductor or the second connection conductor is exposed on the first semiconductor wafer.   The semiconductor device according to claim 9, further comprising a pad that connects the first coupling conductor and the second coupling conductor.   The semiconductor device according to claim 7, further comprising a third connection conductor connected to the logic circuit, wherein a surface of the third connection conductor is exposed on a surface of the second semiconductor wafer.   The semiconductor device according to claim 11, comprising an electrode bump connected to the third connecting conductor.   The semiconductor device according to claim 11, wherein the third connecting conductor is connected to a lowermost layer of the second semiconductor wafer.   The semiconductor device according to claim 2, wherein a surface of the first connecting conductor is exposed on an upper side of the first semiconductor wafer.   The semiconductor device according to claim 14, further comprising a pad connected to the first coupling conductor.   The semiconductor device according to claim 1, wherein the first connection conductor is located outside a pixel region in which the pixel array is located.   The semiconductor device according to claim 1, wherein the first semiconductor wafer has a thickness smaller than a thickness of the second semiconductor wafer. A first semiconductor wafer having a pixel array;
A second semiconductor wafer having a logic circuit;
A semiconductor device having a back-illuminated solid-state imaging device, comprising: a first connecting conductor that electrically connects the pixel array and the logic circuit;
Bonding the first semiconductor wafer and the second semiconductor wafer together;
The pixel array and the logic circuit are electrically connected by a conductor such that one surface is exposed to a bonding surface of either of the first and second wafers,
The first connection conductor is a back-illuminated semiconductor device that connects the lowermost layer of the first semiconductor wafer and the uppermost layer of the second semiconductor wafer.

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