JP2007013089A - Solid imaging element and its manufacturing method - Google Patents

Solid imaging element and its manufacturing method Download PDF

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JP2007013089A
JP2007013089A JP2006012106A JP2006012106A JP2007013089A JP 2007013089 A JP2007013089 A JP 2007013089A JP 2006012106 A JP2006012106 A JP 2006012106A JP 2006012106 A JP2006012106 A JP 2006012106A JP 2007013089 A JP2007013089 A JP 2007013089A
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wiring
substrate
semiconductor layer
support substrate
main surface
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JP4940667B2 (en
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Makoto Iwabuchi
信 岩淵
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Sony Corp
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Priority to JP2006012106A priority Critical patent/JP4940667B2/en
Priority to US11/368,756 priority patent/US8049293B2/en
Priority to TW95107659A priority patent/TWI306663B/en
Priority to KR20060021336A priority patent/KR101222761B1/en
Priority to CN2006100793691A priority patent/CN1838423B/en
Publication of JP2007013089A publication Critical patent/JP2007013089A/en
Priority to US12/262,805 priority patent/US7947528B2/en
Priority to US12/263,085 priority patent/US8440499B2/en
Priority to US12/829,173 priority patent/US8309392B2/en
Priority to US12/829,114 priority patent/US9117710B2/en
Priority to US12/929,985 priority patent/US8841743B2/en
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Publication of JP4940667B2 publication Critical patent/JP4940667B2/en
Priority to US14/803,561 priority patent/US9673249B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid imaging element manufacturing method which simply, easily manufactures a back-irradiating CMOS solid imaging element composed so that an electrode extrudes from the surface of opposite side of the exposure surface, and to provide a solid imaging element manufactured by the manufacturing method. <P>SOLUTION: A plurality of pixels which contain a photoelectric conversion element 14 and a field effect transistor 15 are formed on one main surface of a semiconductor layer 12, a wiring 21 buried connected with the plurality of pixels is formed on the main surface of the semiconductor layer 12, a supporting substrate 30 is put on the main surface of the semiconductor layer 12, and the through wiring 31 is formed through the supporting substrate 30 so as to connect to the buried wiring 21. The solid imaging element is a back irradiating element where another main surface side of the semiconductor layer 12 is the light receiving surface of the photoelectric conversion element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、固体撮像素子及びその製造方法に関し、特に、裏面照射型のＣＭＯＳ固体撮像素子及びその製造方法に関する。   The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a back-illuminated CMOS solid-state imaging device and a manufacturing method thereof.

近年、ビデオカメラや電子カメラが広く普及しており、これらのカメラには、ＣＣＤ型や増幅型の固体撮像素子が使用されている。このうち増幅型固体撮像素子（ＣＭＯＳイメージセンサ）は、１つの半導体チップに複数の画素を２次元配列して構成される撮像画素部と、この撮像画素部の外側に配置される周辺回路部とを設けたものである。   In recent years, video cameras and electronic cameras have become widespread, and CCD and amplification type solid-state imaging devices are used for these cameras. Among these, an amplification type solid-state imaging device (CMOS image sensor) includes an imaging pixel unit configured by two-dimensionally arranging a plurality of pixels on one semiconductor chip, and a peripheral circuit unit disposed outside the imaging pixel unit. Is provided.

撮像画素部の各画素内にＦＤ（フローティングディフュージョン）部や転送、増幅等の各種ＣＭＯＳトランジスタが形成されており、各画素に入射した光をフォトダイオードによって光電変換して信号電荷を生成し、この信号電荷を転送トランジスタによってＦＤ部に転送し、このＦＤ部の電位変動を増幅トランジスタによって検出し、これを電気信号に変換、増幅することにより、画素毎の信号を信号線より周辺回路部に出力するものである。   In each pixel of the imaging pixel unit, an FD (floating diffusion) unit and various CMOS transistors such as transfer and amplification are formed, and light incident on each pixel is photoelectrically converted by a photodiode to generate a signal charge. The signal charge is transferred to the FD portion by the transfer transistor, the potential fluctuation of the FD portion is detected by the amplification transistor, converted into an electric signal, and amplified, and the signal for each pixel is output from the signal line to the peripheral circuit portion. To do.

また、周辺回路部には、撮像画素部からの画素信号に所定の信号処理、例えばＣＤＳ（相関二重サンプリング）、利得制御、Ａ／Ｄ変換等を施す信号処理回路、ならびに撮像画素部の各画素を駆動して画素信号の出力を制御する駆動制御回路、例えば垂直、水平の各スキャナやタイミングジェネレータ（ＴＧ）等が設けられている。   The peripheral circuit section includes a signal processing circuit that performs predetermined signal processing, such as CDS (correlated double sampling), gain control, A / D conversion, and the like on the pixel signal from the imaging pixel section, and each of the imaging pixel section. Drive control circuits that drive the pixels and control the output of the pixel signals, such as vertical and horizontal scanners and timing generators (TG), are provided.

小型ＣＭＯＳカメラモジュールを作るために、ＣＭＯＳ固体撮像素子と信号処理デバイスを接続して１チップ化する方法が開発されている。ここで、感度やシェーディング特性を向上させるために光電変換素子からの信号を読み出す回路が形成された表面とは反対の裏面から光を入射させる構造をもつ、いわゆる裏面照射型のＣＭＯＳイメージセンサが開発されている。   In order to make a small CMOS camera module, a method of connecting a CMOS solid-state imaging device and a signal processing device into one chip has been developed. Here, in order to improve sensitivity and shading characteristics, a so-called back-illuminated CMOS image sensor has been developed, which has a structure in which light is incident from the back surface opposite to the surface on which a circuit for reading a signal from a photoelectric conversion element is formed Has been.

図１１は、上記の裏面照射型ＣＭＯＳ固体撮像素子を実装したイメージセンサの構成を示す模式断面図である。
例えば、インタポーザ（中間基板）１０３上に、撮像画素部が設けられたセンサチップ１０１と、信号処理などの周辺回路部が設けられた信号処理チップ１０２が実装されている。 FIG. 11 is a schematic cross-sectional view showing a configuration of an image sensor on which the back-illuminated CMOS solid-state imaging device is mounted.
For example, a sensor chip 101 provided with an imaging pixel unit and a signal processing chip 102 provided with a peripheral circuit unit such as signal processing are mounted on an interposer (intermediate substrate) 103.

センサチップ１０１は、支持基板７０上に層間絶縁層６０が形成されており、内部に配線層６１が埋め込まれている。その上層に半導体層５２が形成されており、その表面に表面絶縁膜５１が形成されている。
半導体層５２中には、光電変換素子であるフォトダイオード５４及びテスト用電極５３などが形成されている。また、配線層６１の一部が半導体層５２に対してゲート絶縁膜を介して形成されたゲート電極となり、ＣＭＯＳトランジスタ５５が構成される。
さらに、半導体層５２を貫通して配線層６１に接続する半導体層貫通配線５６が形成されており、半導体層貫通配線５６が形成された近傍で表面絶縁膜５１の一部が除去されており、半導体層貫通配線５６に接続してパッド電極５７が形成されている。 In the sensor chip 101, an interlayer insulating layer 60 is formed on a support substrate 70, and a wiring layer 61 is embedded therein. A semiconductor layer 52 is formed thereon, and a surface insulating film 51 is formed on the surface thereof.
In the semiconductor layer 52, a photodiode 54, which is a photoelectric conversion element, a test electrode 53, and the like are formed. A part of the wiring layer 61 becomes a gate electrode formed on the semiconductor layer 52 via a gate insulating film, and the CMOS transistor 55 is configured.
Further, a semiconductor layer through wiring 56 that penetrates the semiconductor layer 52 and is connected to the wiring layer 61 is formed, and a part of the surface insulating film 51 is removed in the vicinity of the semiconductor layer through wiring 56 formed. A pad electrode 57 is formed in connection with the semiconductor layer through wiring 56.

上記の構成のセンサチップ１０１は、半導体層５２中に形成されたフォトダイオード５４に対して、表面絶縁膜５１側から光が照射されると信号電荷が発生し、フォトダイオードに蓄積される、いわゆる裏面照射型のＣＭＯＳ固体撮像素子である。ＣＭＯＳトランジスタ５５は、フォトダイオード５４に蓄積された信号電荷のＦＤ部への転送や信号増幅、あるいはリセットなどの機能を有する。
上記の構成において、半導体層は半導体基板の裏面を薄膜化して得られたものであり、基板形状を安定させるために支持基板７０と貼り合わせた構造となっている。 The sensor chip 101 configured as described above generates a signal charge when light is irradiated from the surface insulating film 51 side to the photodiode 54 formed in the semiconductor layer 52, and is accumulated in the photodiode. This is a back-illuminated CMOS solid-state imaging device. The CMOS transistor 55 has functions such as transfer of signal charges accumulated in the photodiode 54 to the FD portion, signal amplification, or reset.
In the above configuration, the semiconductor layer is obtained by thinning the back surface of the semiconductor substrate, and has a structure in which the semiconductor layer is bonded to the support substrate 70 in order to stabilize the substrate shape.

上記のセンサチップ１０１は、光照射側の反対側である支持基板７０側から、表面に配線８０及びそれらを絶縁する絶縁層８１が形成されたインタポーザ１０３上に、接着層などにより実装され、ワイヤボンディング８２ａにより配線８０とパッド電極５７が電気的に接続される。
一方、周辺回路部が形成された信号処理チップ１０２は、例えばバンプを介してフリップチップでインタポーザ上に実装されている。
このような構成の電子装置が、インタポーザごと他の実装基板に実装され、例えばワイヤボンディング８２ｂなどにより電気的に接続されて用いられる。 The sensor chip 101 is mounted by an adhesive layer or the like on the interposer 103 on the surface of which the wiring 80 and the insulating layer 81 for insulating them are formed from the support substrate 70 side opposite to the light irradiation side. The wiring 80 and the pad electrode 57 are electrically connected by the bonding 82a.
On the other hand, the signal processing chip 102 in which the peripheral circuit portion is formed is mounted on the interposer by flip chip through bumps, for example.
The electronic device having such a configuration is mounted on another mounting substrate together with the interposer, and is used by being electrically connected by, for example, wire bonding 82b.

上記の従来の裏面照射型ＣＭＯＳ固体撮像素子を実装基板に実装して構成されるイメージセンサの製造方法について説明する。
まず、図１２（ａ）に示すように、シリコンなどからなる半導体基板５０の表面に、酸化シリコンなどからなり、後工程で表面絶縁膜となる絶縁膜５１を形成し、その上層にシリコンなどの半導体層５２が形成されてなるＳＯＩ（semiconductor on insulator）基板を形成し、テスト用電極５３を形成しておく。 A method for manufacturing an image sensor configured by mounting the above-described conventional back-illuminated CMOS solid-state imaging device on a mounting substrate will be described.
First, as shown in FIG. 12A, an insulating film 51 made of silicon oxide or the like is formed on the surface of a semiconductor substrate 50 made of silicon or the like and becomes a surface insulating film in a later step, and silicon or the like is formed thereon. An SOI (semiconductor on insulator) substrate formed with the semiconductor layer 52 is formed, and a test electrode 53 is formed.

次に、図１２（ｂ）に示すように、導電性不純物をイオン注入して、半導体層５２中にフォトダイオード５４を形成し、さらに半導体層５２の表面にゲート絶縁膜を介してゲート電極を形成し、フォトダイオード５４などに接続してＣＭＯＳトランジスタ５５を形成する。さらに、ＣＭＯＳトランジスタを被覆する層間絶縁層６０を形成する。このとき、トランジスタや半導体層５２などに接続するように配線層６１を層間絶縁層６０中に埋め込みながら形成する。   Next, as shown in FIG. 12B, conductive impurities are ion-implanted to form a photodiode 54 in the semiconductor layer 52, and a gate electrode is formed on the surface of the semiconductor layer 52 through a gate insulating film. Then, a CMOS transistor 55 is formed by connecting to the photodiode 54 or the like. Further, an interlayer insulating layer 60 that covers the CMOS transistor is formed. At this time, the wiring layer 61 is formed while being embedded in the interlayer insulating layer 60 so as to be connected to the transistor, the semiconductor layer 52 and the like.

次に、図１２（ｃ）に示すように、層間絶縁層６０の上層に支持基板７０を貼り合わせる。   Next, as shown in FIG. 12C, the support substrate 70 is bonded to the upper layer of the interlayer insulating layer 60.

次に、図１３（ａ）に示すように、支持基板７０を貼り合わせた側の反対側の表面から、絶縁膜５１が露出するまで半導体基板５０を研磨して除去する。表面に露出した絶縁膜５１を表面絶縁膜と称する。以降の工程では、図面上、図１２（ｃ）に対して上下関係を逆にして図示している。   Next, as shown in FIG. 13A, the semiconductor substrate 50 is removed by polishing from the surface opposite to the side to which the support substrate 70 is bonded until the insulating film 51 is exposed. The insulating film 51 exposed on the surface is referred to as a surface insulating film. In the subsequent steps, the vertical relationship is shown in the drawing with respect to FIG.

次に、図１３（ｂ）に示すように、表面絶縁膜５１の一部を除去し、半導体層５２を貫通して配線層６１に接続する貫通配線５６を形成し、貫通配線５６に接続するようにパッド電極５７を形成する。
以上のようにして、従来の裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１０１が形成される。 Next, as shown in FIG. 13B, a part of the surface insulating film 51 is removed, a through wiring 56 that penetrates the semiconductor layer 52 and is connected to the wiring layer 61 is formed, and is connected to the through wiring 56. Thus, the pad electrode 57 is formed.
As described above, the conventional back-illuminated CMOS solid-state imaging device (sensor chip) 101 is formed.

上記のように形成された裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１０１を、光照射側の反対側である支持基板７０側から接着剤層などによりインタポーザ１０３上に実装し、ワイヤボンディング８２ａで接続する。
一方、周辺回路部が形成された信号処理チップ１０２は、バンプを介してフリップチップでインタポーザ上に実装し、裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１０１と信号処理チップ１０２とをインタポーザ１０３に形成された配線を介して接続する。
以上のようにして、上記の従来の裏面照射型ＣＭＯＳ固体撮像素子をインタポーザに実装したイメージセンサを製造することができる。 The back-illuminated CMOS solid-state imaging device (sensor chip) 101 formed as described above is mounted on the interposer 103 by an adhesive layer or the like from the support substrate 70 side opposite to the light irradiation side, and wire bonding 82a is used. Connecting.
On the other hand, the signal processing chip 102 in which the peripheral circuit portion is formed is mounted on the interposer by flip chip via bumps, and the backside illumination type CMOS solid-state imaging device (sensor chip) 101 and the signal processing chip 102 are used as the interposer 103. The connection is made through the formed wiring.
As described above, an image sensor in which the conventional back-illuminated CMOS solid-state imaging device is mounted on an interposer can be manufactured.

上記の構成の裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１０１において、パッド電極としてワイヤボンディングが可能な大きさが必要なため、チップ面積が増大することと、チップ内に形成できる電極数も限られ、高抵抗なワイヤボンディングを用いることから、センサチップから信号処理デバイスに伝える信号のスピード劣化などの問題があった。   In the back-illuminated CMOS solid-state imaging device (sensor chip) 101 having the above-described configuration, the pad electrode needs to have a size capable of wire bonding, so that the chip area increases and the number of electrodes that can be formed in the chip is limited. In addition, since high-resistance wire bonding is used, there is a problem such as a deterioration in speed of a signal transmitted from the sensor chip to the signal processing device.

一方で、照射面の反対側の面から電極を取り出す構成となっている裏面照射型のＣＭＯＳ固体撮像素子が開発されている。この場合、照射面を上に向け、その反対の面の電極形成面側から実装基板などに実装して用いられる。
照射面の反対の面に電極が形成されている裏面照射型のＣＭＯＳ固体撮像素子としては、例えば特許文献１及び特許文献２に記載がある。
特開２００３−３１７８５号公報 特開２００３−２７３３４３号公報 On the other hand, a back-illuminated CMOS solid-state imaging device has been developed in which an electrode is extracted from a surface opposite to the irradiation surface. In this case, it is used by being mounted on a mounting substrate or the like from the opposite side of the electrode forming surface with the irradiation surface facing upward.
For example, Patent Document 1 and Patent Document 2 describe back-illuminated CMOS solid-state imaging devices in which electrodes are formed on the surface opposite to the irradiation surface.
JP 2003-31785 A JP 2003-273343 A

本発明が解決しようとする課題は、照射面の反対側の面から電極を取り出す構成の裏面照射型のＣＭＯＳ固体撮像素子をより簡便、容易に製造できる固体撮像素子の製造方法と、当該製造方法により製造した固体撮像素子を提供することである。   A problem to be solved by the present invention is a method for manufacturing a solid-state imaging device capable of more easily and easily manufacturing a back-illuminated CMOS solid-state imaging device having a configuration in which an electrode is extracted from the surface opposite to the irradiation surface, and the manufacturing method. It is providing the solid-state image sensor manufactured by this.

本発明の固体撮像素子は、一方の主面に光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層と、前記半導体層の前記一方の主面に形成され、前記複数の画素に接続して形成された埋め込み配線と、前記半導体層の前記一方の主面に貼り合わされた支持基板と、前記埋め込み配線に接続するように前記支持基板を貫通して形成された貫通配線とを有し、前記半導体層の他方の主面側が前記光電変換素子の受光面となる裏面照射型である。   The solid-state imaging device of the present invention includes a semiconductor layer in which a plurality of pixels including a photoelectric conversion element and a field effect transistor are formed on one main surface, and the plurality of pixels formed on the one main surface of the semiconductor layer. Embedded wiring formed connected to the semiconductor substrate, a support substrate bonded to the one main surface of the semiconductor layer, and a through wiring formed through the support substrate so as to be connected to the embedded wiring. And having the other main surface side of the semiconductor layer as a light receiving surface of the photoelectric conversion element.

上記の本発明の固体撮像素子は、半導体層の一方の主面に光電変換素子と電界効果トランジスタを含む複数の画素が形成されており、半導体層の一方の主面に複数の画素に接続して埋め込み配線が形成され、半導体層の一方の主面に支持基板が貼り合わされており、埋め込み配線に接続するように支持基板を貫通して貫通配線が形成されている。ここで、半導体層の他方の主面側が光電変換素子の受光面となる裏面照射型となっている。   In the solid-state imaging device of the present invention, a plurality of pixels including a photoelectric conversion element and a field effect transistor are formed on one main surface of a semiconductor layer, and the plurality of pixels are connected to one main surface of the semiconductor layer. The embedded wiring is formed, the support substrate is bonded to one main surface of the semiconductor layer, and the through wiring is formed through the support substrate so as to be connected to the embedded wiring. Here, the other main surface side of the semiconductor layer is a backside illumination type in which the light receiving surface of the photoelectric conversion element is formed.

また、本発明の固体撮像素子の製造方法は、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に前記複数の画素に接続する埋め込み配線が形成され、前記半導体層の他方の面が前記光電変換素子の受光面となる裏面照射型固体撮像素子の製造方法であって、半導体基板の一方の主面に前記光電変換素子と電界効果トランジスタを含む複数の画素を形成する工程と、前記半導体基板の一方の主面に前記複数の画素に接続する埋め込み配線を形成する工程と、前記半導体基板の一方の主面に支持基板を貼り合わせる工程と、貼り合わせ面の反対側から前記支持基板を薄膜化する工程と、前記埋め込み配線に接続するように前記支持基板を貫通する貫通配線を形成する工程と、前記半導体基板の他方の主面側から前記光電変換素子が受光可能となるまで、前記半導体基板の他方の主面側から前記半導体基板を薄膜化して前記半導体層とする工程とを有する。   In the solid-state imaging device manufacturing method of the present invention, the embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed. A method of manufacturing a back-illuminated solid-state imaging device in which the other surface of the semiconductor layer is a light-receiving surface of the photoelectric conversion device, and a plurality of pixels including the photoelectric conversion device and a field effect transistor on one main surface of a semiconductor substrate A step of forming embedded wiring connected to the plurality of pixels on one main surface of the semiconductor substrate, a step of bonding a support substrate to one main surface of the semiconductor substrate, and a bonding surface Thinning the support substrate from the opposite side, forming a through-wiring through the support substrate so as to connect to the embedded wiring, and the other main surface side of the semiconductor substrate Et until said photoelectric conversion element is capable of receiving, and a step of said semiconductor layer by thinning the semiconductor substrate from the other principal surface side of the semiconductor substrate.

上記の本発明の固体撮像素子の製造方法は、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に複数の画素に接続する埋め込み配線が形成され、半導体層の他方の面が光電変換素子の受光面となる裏面照射型固体撮像素子を製造する方法である。
まず、半導体基板の一方の主面に光電変換素子と電界効果トランジスタを含む複数の画素を形成し、さらに複数の画素に接続する埋め込み配線を形成する。
次に、半導体基板の一方の主面に支持基板を貼り合わせ、貼り合わせ面の反対側から支持基板を薄膜化し、埋め込み配線に接続するように支持基板を貫通する貫通配線を形成する。
次に、半導体基板の他方の主面側から光電変換素子が受光可能となるまで、半導体基板の他方の主面側から半導体基板を薄膜化して半導体層とする。 In the method for manufacturing a solid-state imaging device according to the present invention, the embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed. This is a method for manufacturing a back-illuminated solid-state imaging device in which the other surface is the light receiving surface of the photoelectric conversion device.
First, a plurality of pixels including a photoelectric conversion element and a field effect transistor are formed on one main surface of a semiconductor substrate, and a buried wiring connected to the plurality of pixels is formed.
Next, the supporting substrate is bonded to one main surface of the semiconductor substrate, the supporting substrate is thinned from the opposite side of the bonding surface, and a through wiring penetrating the supporting substrate is formed so as to be connected to the embedded wiring.
Next, the semiconductor substrate is thinned from the other main surface side of the semiconductor substrate to form a semiconductor layer until the photoelectric conversion element can receive light from the other main surface side of the semiconductor substrate.

また、本発明の固体撮像素子の製造方法は、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に前記複数の画素に接続する埋め込み配線が形成され、前記半導体層の他方の面が前記光電変換素子の受光面となる裏面照射型固体撮像素子の製造方法であって、半導体基板の一方の主面に前記光電変換素子と電界効果トランジスタを含む複数の画素を形成する工程と、前記半導体基板の一方の主面に前記複数の画素に接続する埋め込み配線を形成する工程と、支持基板の一方の主面の表面から少なくとも所定の深さにまで至る支持基板配線を形成する工程と、前記半導体基板の一方の主面と前記支持基板の一方の主面を貼り合わせる工程と、前記半導体基板の他方の主面側から前記光電変換素子が受光可能となるまで、前記半導体基板の他方の主面側から前記半導体基板を薄膜化して前記半導体層とする工程と、前記支持基板配線と前記埋め込み配線を接続する接続配線を形成する工程と、前記支持基板配線が露出するまで前記支持基板の他方の面側から前記支持基板を薄膜化して、前記支持基板配線を、前記支持基板を貫通する貫通配線とする工程とを有する。   In the solid-state imaging device manufacturing method of the present invention, the embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed. A method of manufacturing a back-illuminated solid-state imaging device in which the other surface of the semiconductor layer is a light-receiving surface of the photoelectric conversion device, and a plurality of pixels including the photoelectric conversion device and a field effect transistor on one main surface of a semiconductor substrate A step of forming embedded wiring connected to the plurality of pixels on one main surface of the semiconductor substrate, and a support substrate extending from the surface of one main surface of the support substrate to at least a predetermined depth The step of forming wiring, the step of bonding one main surface of the semiconductor substrate and one main surface of the support substrate, and the photoelectric conversion element can receive light from the other main surface side of the semiconductor substrate Until the step, the step of thinning the semiconductor substrate from the other main surface side of the semiconductor substrate to form the semiconductor layer, the step of forming a connection wiring for connecting the support substrate wiring and the embedded wiring, the support substrate Forming the support substrate into a thin film from the other surface side of the support substrate until the wiring is exposed, and using the support substrate wiring as a through wiring penetrating the support substrate.

上記の本発明の固体撮像素子の製造方法は、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に複数の画素に接続する埋め込み配線が形成され、半導体層の他方の面が光電変換素子の受光面となる裏面照射型固体撮像素子を製造する方法である。
まず、半導体基板の一方の主面に光電変換素子と電界効果トランジスタを含む複数の画素を形成し、さらに複数の画素に接続する埋め込み配線を形成する。
一方、支持基板の一方の主面の表面から少なくとも所定の深さにまで至る支持基板配線を形成し、次に、半導体基板の一方の主面と支持基板の一方の主面を貼り合わせる。
次に、半導体基板の他方の主面側から光電変換素子が受光可能となるまで、半導体基板の他方の主面側から半導体基板を薄膜化して半導体層とする。
次に、支持基板配線と埋め込み配線を接続する接続配線を形成し、支持基板配線が露出するまで支持基板の他方の面側から支持基板を薄膜化して、支持基板配線を、支持基板を貫通する貫通配線とする。 In the method for manufacturing a solid-state imaging device according to the present invention, the embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed. This is a method for manufacturing a back-illuminated solid-state imaging device in which the other surface is the light receiving surface of the photoelectric conversion device.
First, a plurality of pixels including a photoelectric conversion element and a field effect transistor are formed on one main surface of a semiconductor substrate, and a buried wiring connected to the plurality of pixels is formed.
On the other hand, support substrate wiring extending from the surface of one main surface of the support substrate to at least a predetermined depth is formed, and then one main surface of the semiconductor substrate and one main surface of the support substrate are bonded together.
Next, the semiconductor substrate is thinned from the other main surface side of the semiconductor substrate to form a semiconductor layer until the photoelectric conversion element can receive light from the other main surface side of the semiconductor substrate.
Next, a connection wiring connecting the support substrate wiring and the embedded wiring is formed, and the support substrate is thinned from the other surface side of the support substrate until the support substrate wiring is exposed, and the support substrate wiring penetrates the support substrate. Use through wiring.

本発明の固体撮像素子は、本発明の固体撮像装置の製造方法により簡便、容易に製造可能な、照射面の反対側の面から電極を取り出す構成の裏面照射型のＣＭＯＳ固体撮像素子である。   The solid-state imaging device of the present invention is a back-illuminated CMOS solid-state imaging device having a configuration in which an electrode is taken out from the surface opposite to the irradiation surface, which can be easily and easily manufactured by the method for manufacturing a solid-state imaging device of the present invention.

本発明の固体撮像素子の製造方法によれば、支持基板を貼り合わせて強度を確保してから半導体基板を薄膜化し、また、支持基板を薄膜化して貫通配線を形成するので、簡便、容易に、照射面の反対側の面から電極を取り出す構成の裏面照射型のＣＭＯＳ固体撮像素子を製造することができる。   According to the method for manufacturing a solid-state imaging device of the present invention, a semiconductor substrate is thinned after securing a support substrate to ensure strength, and a through wiring is formed by thinning the support substrate, so that it is simple and easy. A back-illuminated CMOS solid-state imaging device having a configuration in which an electrode is taken out from the surface opposite to the irradiation surface can be manufactured.

以下に、本発明の実施の形態に係るＣＭＯＳ固体撮像素子及びその製造方法について、図面を参照して説明する。   A CMOS solid-state imaging device and a method for manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings.

第１実施形態
図１は、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を実装した電子装置の構成を示す模式断面図である。
例えば、インタポーザ（中間基板）３上に、撮像画素部が設けられた裏面照射型ＣＭＯＳ固体撮像素子であるセンサチップ１ａと、信号処理などの周辺回路部が設けられた信号処理チップ２が実装されている。 First Embodiment FIG. 1 is a schematic cross-sectional view showing the configuration of an electronic device mounted with a backside illumination type CMOS solid-state imaging device according to this embodiment.
For example, on the interposer (intermediate substrate) 3, a sensor chip 1 a that is a back-illuminated CMOS solid-state imaging device provided with an imaging pixel unit and a signal processing chip 2 provided with a peripheral circuit unit such as signal processing are mounted. ing.

センサチップ１ａは、支持基板３０上に層間絶縁層２０が形成されており、内部に埋め込み配線層２１が埋め込まれている。その上層に半導体層１２が形成されており、その表面に表面絶縁膜１１が形成されている。
半導体層１２中には、フォトダイオード１４及び電極などからなるアライメントマーク１３などが形成されている。アライメントマーク１３は、半導体層１２の表面絶縁膜１１側のパターニングを行う際の位置決めの基準となるほか、電極で構成することでテスト用電極としても機能できる。
また、埋め込み配線層２１の一部が半導体層１２に対してゲート絶縁膜を介して形成されたゲート電極となり、ＣＭＯＳトランジスタ１５が構成される。
さらに、支持基板３０を貫通して埋め込み配線層２１に接続する支持基板貫通配線３１が形成されており、支持基板３０の表面から突出する突起電極（バンプ）３２が支持基板貫通配線３１の表面に形成されている。バンプ（マイクロバンプ）は、ワイヤボンディングに用いる通常のパッド電極よりも小さいパッド上に、電解メッキなどで形成された突起状金属電極である。 In the sensor chip 1a, an interlayer insulating layer 20 is formed on a support substrate 30, and an embedded wiring layer 21 is embedded therein. A semiconductor layer 12 is formed as an upper layer, and a surface insulating film 11 is formed on the surface thereof.
In the semiconductor layer 12, an alignment mark 13 including a photodiode 14 and an electrode is formed. The alignment mark 13 serves as a reference for positioning when performing patterning on the surface insulating film 11 side of the semiconductor layer 12, and can also function as a test electrode by being composed of electrodes.
A part of the buried wiring layer 21 becomes a gate electrode formed on the semiconductor layer 12 via a gate insulating film, and the CMOS transistor 15 is configured.
Further, a support substrate through wiring 31 that penetrates the support substrate 30 and is connected to the embedded wiring layer 21 is formed, and protruding electrodes (bumps) 32 protruding from the surface of the support substrate 30 are formed on the surface of the support substrate through wiring 31. Is formed. A bump (micro bump) is a protruding metal electrode formed by electrolytic plating or the like on a pad smaller than a normal pad electrode used for wire bonding.

上記の構成のセンサチップ１ａは、半導体層１２中に形成されたフォトダイオード１４に対して、表面絶縁膜１１側から光が照射されると信号電荷が発生し、フォトダイオードに蓄積される、いわゆる裏面照射型のＣＭＯＳ固体撮像素子である。ＣＭＯＳトランジスタ１５は、フォトダイオード１４に蓄積された信号電荷のＦＤ部への転送や信号増幅、あるいはリセットなどの機能を有する。
上記の構成において、半導体層は半導体基板の裏面を薄膜化して得られたものであり、基板形状を安定させるために支持基板３０と貼り合わせた構造となっている。 The sensor chip 1a having the above-described configuration generates a signal charge when the photodiode 14 formed in the semiconductor layer 12 is irradiated with light from the surface insulating film 11 side, and is accumulated in the photodiode. This is a back-illuminated CMOS solid-state imaging device. The CMOS transistor 15 has functions such as transfer of signal charges accumulated in the photodiode 14 to the FD portion, signal amplification, and reset.
In the above configuration, the semiconductor layer is obtained by thinning the back surface of the semiconductor substrate, and has a structure in which the semiconductor layer is bonded to the support substrate 30 in order to stabilize the substrate shape.

上記のように、本実施形態のＣＭＯＳ固体撮像素子は、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に複数の画素に接続する埋め込み配線が形成され、半導体層の他方の面が光電変換素子の受光面となる裏面照射型の固体撮像素子である。   As described above, in the CMOS solid-state imaging device of the present embodiment, the embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer in which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed. This is a back-illuminated solid-state imaging device in which the other surface of the semiconductor layer is the light receiving surface of the photoelectric conversion device.

上記のセンサチップ１ａは、光照射側の反対側である支持基板３０側から、表面に配線４０及びそれらを絶縁する絶縁層４１が形成されたインタポーザ３上に、絶縁層の開口部から配線の表面の一部が露出してなるランドとバンプが接合するようにフリップチップで実装される。
一方、周辺回路部が形成された信号処理チップ２は、例えばバンプを介してフリップチップでインタポーザ上に実装されている。
このような構成の電子装置が、インタポーザごと他の実装基板に実装され、例えばワイヤボンディング４２などにより電気的に接続されて用いられる。
例えば、インタポーザ上には上記センサチップ（ＣＭＯＳ固体撮像素子）と信号処理チップを接続して１チップ化した機能を評価する電極ＰＡＤが形成されている。 The sensor chip 1a is connected to the interposer 3 on the surface of which the wiring 40 and the insulating layer 41 for insulating them are formed from the support substrate 30 side opposite to the light irradiation side. It is mounted by flip chip so that the lands formed by exposing a part of the surface and the bumps are joined.
On the other hand, the signal processing chip 2 in which the peripheral circuit portion is formed is mounted on the interposer by flip chip through bumps, for example.
The electronic device having such a configuration is mounted on another mounting substrate together with the interposer, and is used by being electrically connected, for example, by wire bonding 42 or the like.
For example, an electrode PAD is formed on the interposer to evaluate the function obtained by connecting the sensor chip (CMOS solid-state imaging device) and the signal processing chip into one chip.

図２は本実施形態に係るＣＭＯＳ固体撮像素子を組み込んだイメージセンサの構成を示すブロック図であり、図３は本実施形態に係るＣＭＯＳ固体撮像素子の画素の構成を示す等価回路図である。
本実施形態に係るイメージセンサは、撮像画素部１１２、Ｖ選択手段１１４、Ｈ選択手段１１６、タイミングジェネレータ（ＴＧ）１１８、Ｓ／Ｈ・ＣＤＳ回路部１２０、ＡＧＣ部１２２、Ａ／Ｄ変換部１２４、デジタルアンプ部１２６等から構成されている。
例えば、撮像画素部１１２と、Ｖ選択手段１１４、Ｈ選択手段１１６及びＳ／Ｈ・ＣＤＳ回路部１２０を１チップ上にまとめて図１におけるセンサチップ１ａとし、残りの回路部分を信号処理チップ２上にまとめた形態とすることができる。あるいは、センサチップ１ａには撮像画素部１１２のみが形成されている構成とすることもできる。 FIG. 2 is a block diagram showing a configuration of an image sensor incorporating the CMOS solid-state imaging device according to the present embodiment, and FIG. 3 is an equivalent circuit diagram showing a configuration of pixels of the CMOS solid-state imaging device according to the present embodiment.
The image sensor according to the present embodiment includes an imaging pixel unit 112, a V selection unit 114, an H selection unit 116, a timing generator (TG) 118, an S / H / CDS circuit unit 120, an AGC unit 122, and an A / D conversion unit 124. The digital amplifier unit 126 and the like.
For example, the imaging pixel unit 112, the V selection unit 114, the H selection unit 116, and the S / H / CDS circuit unit 120 are integrated on one chip to form the sensor chip 1a in FIG. It can be set as the form put together above. Alternatively, only the imaging pixel unit 112 may be formed on the sensor chip 1a.

撮像画素部１１２は、多数の画素が２次元マトリクス状に配列されており、各画素には、図３に示すように、受光量に応じた信号電荷を生成し蓄積する光電変換素子であるフォトダイオード（ＰＤ）２００が設けられ、さらに、このフォトダイオード２００が変換して蓄積した信号電荷をフローティングディフュージョン部（ＦＤ部）２１０に転送する転送トランジスタ２２０と、ＦＤ部２１０の電圧をリセットするリセットトランジスタ２３０と、ＦＤ部２１０の電圧に対応する出力信号を出力する増幅トランジスタ２４０と、この増幅トランジスタ２４０の出力信号を垂直信号線２６０に出力する選択（アドレス）トランジスタ２５０の４つのＭＯＳトランジスタが設けられている。   The imaging pixel unit 112 includes a large number of pixels arranged in a two-dimensional matrix, and each pixel is a photo-electric conversion element that generates and accumulates signal charges according to the amount of received light as shown in FIG. A diode (PD) 200 is provided, and further, a transfer transistor 220 that transfers signal charges converted and accumulated by the photodiode 200 to a floating diffusion portion (FD portion) 210, and a reset transistor that resets the voltage of the FD portion 210 230, an amplification transistor 240 that outputs an output signal corresponding to the voltage of the FD section 210, and a selection (address) transistor 250 that outputs the output signal of the amplification transistor 240 to the vertical signal line 260 are provided. ing.

このような構成の画素では、フォトダイオード２００で光電変換された信号電荷を転送トランジスタ２２０によってＦＤ部２１０に転送する。ＦＤ部２１０は、増幅トランジスタ２４０のゲートにつながっており、増幅トランジスタ２４０は撮像画素部１１２の外部に設けられた定電流源２７０とソースフォロアを構成するので、アドレストランジスタ２５０をＯＮすると、ＦＤ部２１０の電圧に応じた電圧が垂直信号線２６０に出力される。また、リセットトランジスタ２３０は、ＦＤ部２１０の電圧を信号電荷によらない定電圧（図３では駆動電圧Ｖｄｄ）にリセットする。
また、撮像画素部１１２には各ＭＯＳトランジスタを駆動制御するための各種駆動配線が水平方向に配線されており、撮像画素部１１２の各画素は、Ｖ選択手段１１４によって垂直方向に水平ライン（画素行）単位で順次選択され、タイミングジェネレータ１１８からの各種パルス信号によって各画素のＭＯＳトランジスタが制御されることにより、各画素の信号が垂直信号線２６０を通して画素列毎にＳ／Ｈ・ＣＤＳ部１２０に読み出される。 In the pixel having such a configuration, the signal charge photoelectrically converted by the photodiode 200 is transferred to the FD unit 210 by the transfer transistor 220. The FD unit 210 is connected to the gate of the amplification transistor 240. The amplification transistor 240 forms a source follower with a constant current source 270 provided outside the imaging pixel unit 112. Therefore, when the address transistor 250 is turned on, the FD unit A voltage corresponding to the voltage 210 is output to the vertical signal line 260. Further, the reset transistor 230 resets the voltage of the FD unit 210 to a constant voltage (drive voltage Vdd in FIG. 3) that does not depend on the signal charge.
In addition, various drive wirings for driving and controlling each MOS transistor are wired in the imaging pixel unit 112 in the horizontal direction, and each pixel in the imaging pixel unit 112 is horizontally lined (pixels) by the V selection unit 114. Each pixel is sequentially selected, and the MOS transistor of each pixel is controlled by various pulse signals from the timing generator 118, so that the signal of each pixel passes through the vertical signal line 260 for each S / H / CDS unit 120 for each pixel column. Is read out.

Ｓ／Ｈ・ＣＤＳ部１２０は、撮像画素部１１２の画素列毎にＳ／Ｈ・ＣＤＳ回路を設けたものであり、撮像画素部１１２の各画素列から読み出された画素信号に対し、ＣＤＳ（相関二重サンプリング）等の信号処理を行うものである。
Ｈ選択手段１１６は、Ｓ／Ｈ・ＣＤＳ部１２０からの画素信号をＡＧＣ部１２２に出力する。
ＡＧＣ部１２２は、Ｈ選択手段１１６によって選択されたＳ／Ｈ・ＣＤＳ部１２０からの画素信号に対して所定のゲインコントロールを行い、その画素信号をＡ／Ｄ変換部１２４に出力する。
Ａ／Ｄ変換部１２４は、ＡＧＣ部１２２からの画素信号をアナログ信号からデジタル信号に変換してデジタルアンプ部１２６に出力する。
デジタルアンプ部１２６は、Ａ／Ｄ変換部１２４からのデジタル信号出力について必要な増幅やバッファリングを行い、図示しない外部端子より出力するものである。
タイミングジェネレータ１１８は、上述した撮像画素部１１２の各画素以外の各部にも各種のタイミング信号を供給する。 The S / H • CDS unit 120 is provided with an S / H • CDS circuit for each pixel column of the imaging pixel unit 112, and performs CDS on the pixel signal read from each pixel column of the imaging pixel unit 112. Signal processing such as (correlated double sampling) is performed.
The H selection unit 116 outputs the pixel signal from the S / H • CDS unit 120 to the AGC unit 122.
The AGC unit 122 performs predetermined gain control on the pixel signal from the S / H • CDS unit 120 selected by the H selection unit 116 and outputs the pixel signal to the A / D conversion unit 124.
The A / D conversion unit 124 converts the pixel signal from the AGC unit 122 from an analog signal to a digital signal and outputs the converted signal to the digital amplifier unit 126.
The digital amplifier 126 performs necessary amplification and buffering for the digital signal output from the A / D converter 124 and outputs it from an external terminal (not shown).
The timing generator 118 supplies various timing signals to each part other than each pixel of the imaging pixel part 112 described above.

上記の構成のＣＭＯＳイメージセンサは、従来のように画素から出力される信号を画素周辺回路に出力してからチップ周辺のパッド電極から出力信号を信号処理デバイスに入力することなく、ＣＭＯＳイメージセンサの画素から出力される信号を画素単位もしくは複数の画素単位ごとに直接マイクロバンプを介して信号処理デバイスに入力させることが可能となる。これによって、デバイス間の信号処理スピードが高く高性能で、イメージセンサと信号処理デバイスを１チップ化した高機能なデバイスを提供することが可能となる。   The CMOS image sensor having the above-described configuration is a conventional CMOS image sensor without outputting a signal output from a pixel to a pixel peripheral circuit and then inputting an output signal from a pad electrode around the chip to a signal processing device. It becomes possible to input a signal output from a pixel directly to the signal processing device via a micro bump for each pixel unit or a plurality of pixel units. As a result, it is possible to provide a high-performance device in which the signal processing speed between devices is high and the performance is high, and the image sensor and the signal processing device are integrated into one chip.

上記の本実施形態に係る裏面照射型のＣＭＯＳ固体撮像素子の製造方法について説明する。
まず、図４（ａ）に示すように、例えば、シリコンなどからなる半導体基板１０の表面に、熱酸化法あるいはＣＶＤ（化学気相成長）法などにより、酸化シリコンなどからなり、後工程で表面絶縁膜となる絶縁膜１１を形成する。
さらに、例えば、絶縁膜１１の上層に、例えば貼り合わせ法あるいはエピタキシャル成長法などにより、シリコンなどの半導体層１２を形成し、ＳＯＩ（semiconductor on insulator）基板とする。ここで、半導体層１２にテスト用電極として機能するアライメントマーク１３を形成しておく。アライメントマークとしては、後工程で半導体層１２の絶縁膜１１側のパターニングを行う際の位置決めの基準となるマークである。 A manufacturing method of the backside illumination type CMOS solid-state imaging device according to the present embodiment will be described.
First, as shown in FIG. 4A, for example, the surface of a semiconductor substrate 10 made of silicon or the like is made of silicon oxide or the like by a thermal oxidation method or a CVD (chemical vapor deposition) method. An insulating film 11 to be an insulating film is formed.
Further, for example, a semiconductor layer 12 such as silicon is formed on the insulating film 11 by, for example, a bonding method or an epitaxial growth method to form an SOI (semiconductor on insulator) substrate. Here, an alignment mark 13 functioning as a test electrode is formed on the semiconductor layer 12. The alignment mark is a mark that serves as a positioning reference when patterning the insulating layer 11 side of the semiconductor layer 12 in a later step.

次に、図４（ｂ）に示すように、例えば、ｎ型の半導体層１２にｐ型の導電性不純物をイオン注入してｐｎ接合を形成することにより、半導体層１２中に光電変換素子としてフォトダイオード１４を形成し、さらに半導体層１２の表面にゲート絶縁膜を介してゲート電極を形成し、フォトダイオード１４などに接続してＣＭＯＳトランジスタ１５を形成して、上記の構成の複数の画素を形成する。
さらに、例えばＣＭＯＳトランジスタを被覆する層間絶縁層２０を形成する。このとき、トランジスタや半導体層１２などに接続するように埋め込み配線層２１を層間絶縁層２０中に埋め込みながら形成する。 Next, as shown in FIG. 4B, for example, a p-type conductive impurity is ion-implanted into the n-type semiconductor layer 12 to form a pn junction, thereby forming a photoelectric conversion element in the semiconductor layer 12. A photodiode 14 is formed, a gate electrode is formed on the surface of the semiconductor layer 12 via a gate insulating film, and a CMOS transistor 15 is formed by connecting to the photodiode 14 and the like, and a plurality of pixels having the above-described configuration are formed. Form.
Further, for example, an interlayer insulating layer 20 covering the CMOS transistor is formed. At this time, the buried wiring layer 21 is formed while being buried in the interlayer insulating layer 20 so as to be connected to the transistor, the semiconductor layer 12 and the like.

次に、図４（ｃ）に示すように、例えば、熱硬化樹脂を接着剤とした熱圧着などにより、層間絶縁層２０の上層に、シリコン基板あるいは絶縁性の樹脂基板などからなる支持基板３０を貼り合わせる。   Next, as shown in FIG. 4C, for example, a support substrate 30 made of a silicon substrate or an insulating resin substrate is formed on the interlayer insulating layer 20 by thermocompression bonding using a thermosetting resin as an adhesive. Paste together.

次に、図５（ａ）に示すように、例えば機械的研削などにより、貼り合わせ面の反対側から支持基板３０を薄膜化する。   Next, as shown in FIG. 5A, the support substrate 30 is thinned from the opposite side of the bonding surface by, for example, mechanical grinding.

次に、図５（ｂ）に示すように、埋め込み配線層２１に接続するように、支持基板３０を貫通する支持基板貫通配線３１を形成する。これは、例えば、フォトリソグラフィー工程によりレジスト膜をパターン形成し、ドライエッチングなどのエッチングを行うことで、埋め込み配線層２１に達する開口部を支持基板３０に形成し、銅などの低抵抗金属で埋め込むことで形成することができる。   Next, as shown in FIG. 5B, a support substrate through wiring 31 that penetrates the support substrate 30 is formed so as to be connected to the embedded wiring layer 21. For example, a resist film is patterned by a photolithography process, and etching such as dry etching is performed to form an opening reaching the embedded wiring layer 21 in the support substrate 30 and embedded with a low-resistance metal such as copper. Can be formed.

次に、図６（ａ）に示すように、例えば金属メッキ処理などにより、支持基板３０の表面から突出するバンプ３２を支持基板貫通配線３１の表面に形成する。   Next, as shown in FIG. 6A, bumps 32 protruding from the surface of the support substrate 30 are formed on the surface of the support substrate through wiring 31 by, for example, metal plating.

次に、図６（ｂ）に示すように、例えばＳＯＩ基板の半導体基板１０側からフォトダイオード１４が受光可能となるまで、半導体基板１０を薄膜化する。例えば、絶縁膜１１をストッパとし、絶縁膜１１が露出するまで半導体基板１０の裏面側から機械的研削またはウェットエッチング処理などにより行う。これにより、ＳＯＩ基板の半導体層１２が残される構成となる。ここで、表面に露出した絶縁膜１１を表面絶縁膜と称する。図面上、図６（ａ）に対して上下関係を逆にして図示している。
以上のようにして、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１ａが形成される。必要に応じて半導体層１２の絶縁膜１１側のパターニングを行う際に、位置決めの基準としてアライメントマーク１３を用いる。
さらに、薄膜化して得られた半導体基板（半導体層１２）の裏面上に、例えばＣＶＤ法によって絶縁膜を成膜することが好ましい。この絶縁膜は裏面のシリコン面を保護する目的と入射光に対して反射防止膜として機能することも兼ねることができる。 Next, as shown in FIG. 6B, the semiconductor substrate 10 is thinned until, for example, the photodiode 14 can receive light from the semiconductor substrate 10 side of the SOI substrate. For example, the insulating film 11 is used as a stopper, and mechanical grinding or wet etching is performed from the back side of the semiconductor substrate 10 until the insulating film 11 is exposed. As a result, the semiconductor layer 12 of the SOI substrate is left. Here, the insulating film 11 exposed on the surface is referred to as a surface insulating film. In the drawing, the vertical relationship is reversed with respect to FIG.
As described above, the backside illuminated CMOS solid-state imaging device (sensor chip) 1a according to the present embodiment is formed. The alignment mark 13 is used as a positioning reference when patterning the insulating layer 11 side of the semiconductor layer 12 as necessary.
Furthermore, it is preferable to form an insulating film on the back surface of the semiconductor substrate (semiconductor layer 12) obtained by thinning, for example, by the CVD method. This insulating film can serve both as a purpose of protecting the silicon surface on the back surface and as an antireflection film against incident light.

上記のように形成された裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１ａを、受光面側を上向きにしてバンプ３２を介してフリップチップでインタポーザ上に実装する。例えば、インタポーザの配線上のランドやバンプと、センサチップの支持基板上のバンプ同士を、センサチップや信号処理チップ内に使用されている配線融点よりも低い温度で、かつバンプが電気的に安定に接続する温度で、圧着させる。また、例えば信号処理チップ上に直接センサチップを実装してモジュール化することも可能であり、この場合も上記と同様に行うことができる。
一方、周辺回路部が形成された信号処理チップ２も同様に、バンプを介してフリップチップでインタポーザ上に実装する。これにより、裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１ａと信号処理チップ２とをインタポーザ３に形成された配線を介して接続する。
以上のようにして、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を組み込んだイメージセンサを製造することができる。
また、フリップチップで実装した後も、アライメントマーク１３をテスト用電極として用いてセンサチップの回路を試験することができる。 The back-illuminated CMOS solid-state imaging device (sensor chip) 1a formed as described above is mounted on the interposer by flip chip through the bumps 32 with the light receiving surface side facing upward. For example, the land and bump on the wiring of the interposer and the bump on the support substrate of the sensor chip are electrically stable at a temperature lower than the melting point of the wiring used in the sensor chip and signal processing chip. Crimp at the temperature to connect to. Further, for example, the sensor chip can be directly mounted on the signal processing chip to be modularized, and in this case, the same process as described above can be performed.
On the other hand, the signal processing chip 2 on which the peripheral circuit portion is formed is similarly mounted on the interposer by flip chip through bumps. As a result, the back-illuminated CMOS solid-state imaging device (sensor chip) 1 a and the signal processing chip 2 are connected via the wiring formed in the interposer 3.
As described above, an image sensor incorporating the backside illumination type CMOS solid-state imaging device according to the present embodiment can be manufactured.
Even after mounting by flip chip, the circuit of the sensor chip can be tested using the alignment mark 13 as a test electrode.

上記のように、本実施形態の裏面照射型ＣＭＯＳ固体撮像素子の製造方法によれば、支持基板を貼り合わせて強度を確保してから半導体基板を薄膜化し、また、支持基板を薄膜化して貫通配線を形成するので、半導体基板の裏面から電極を取らずに支持基板から電極を取り出すことができ、簡便、容易に、照射面の反対側の面から電極を取り出す構成の裏面照射型のＣＭＯＳ固体撮像素子を製造することができる。
また、光が入射する面とは反対側の支持基板側に電極を形成できることから、電極の配置の自由度があがり、ＣＭＯＳイメージセンサの開口率を損なうことなく、多数のマイクロバンプを画素直下や画素の周辺直下に形成することが可能となる。
このように、半導体基板の裏面を薄膜化することと、バンプが形成されたインタポーザなどの実装基板や信号処理チップなどの他の半導体チップとバンプ同士で接続することにより、高性能、高機能なデバイスを製造することが可能となる。 As described above, according to the manufacturing method of the backside illuminated CMOS solid-state imaging device of the present embodiment, the semiconductor substrate is thinned after the supporting substrates are bonded together to ensure strength, and the supporting substrate is thinned and penetrated. Since the wiring is formed, it is possible to take out the electrode from the support substrate without taking the electrode from the back surface of the semiconductor substrate, and the backside irradiation type CMOS solid structure in which the electrode is taken out from the surface opposite to the irradiation surface simply and easily. An image sensor can be manufactured.
In addition, since the electrode can be formed on the side of the support substrate opposite to the surface on which the light is incident, the degree of freedom of electrode arrangement is increased, and a large number of micro bumps can be placed directly below the pixel without impairing the aperture ratio of the CMOS image sensor. It can be formed immediately below the periphery of the pixel.
In this way, by reducing the thickness of the back surface of the semiconductor substrate and connecting the bumps to other semiconductor chips such as mounting substrates such as interposers and signal processing chips on which bumps are formed, high performance and high functionality are achieved. A device can be manufactured.

半導体基板としては、例えばＳＯＩ基板のように基板中に酸化膜が予め形成されているものが好ましく、半導体基板の薄膜化におけるウェットエッチングのストッパとしてＳＯＩ基板中の酸化膜を用いることができ、薄膜化後に均一で平坦な半導体基板を得ることができるので好ましい。   As the semiconductor substrate, for example, an oxide film previously formed in the substrate, such as an SOI substrate, is preferable, and the oxide film in the SOI substrate can be used as a stopper for wet etching in thinning the semiconductor substrate. This is preferable because a uniform and flat semiconductor substrate can be obtained after fabrication.

第２実施形態
図７は、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を実装した電子装置の構成を示す模式断面図である。
第１実施形態と同様に、例えば、インタポーザ（中間基板）３上に、撮像画素部が設けられた裏面照射型ＣＭＯＳ固体撮像素子であるセンサチップ１ｂと、信号処理などの周辺回路部が設けられた信号処理チップ２が実装されている。 Second Embodiment FIG. 7 is a schematic cross-sectional view showing the configuration of an electronic device mounted with a backside illumination type CMOS solid-state imaging device according to this embodiment.
Similar to the first embodiment, for example, on the interposer (intermediate substrate) 3, a sensor chip 1 b that is a back-illuminated CMOS solid-state imaging device provided with an imaging pixel unit and a peripheral circuit unit such as signal processing are provided. The signal processing chip 2 is mounted.

センサチップ１ｂは、支持基板３０上に層間絶縁層２０が形成されており、内部に埋め込み配線層２１が埋め込まれている。その上層に半導体層１２が形成されており、その表面に表面絶縁膜（１１，１９）が形成されている。
半導体層１２中には、フォトダイオード１４及びテスト用電極として機能するアライメントマーク１３などが形成されている。また、埋め込み配線層２１の一部が半導体層１２に対してゲート絶縁膜を介して形成されたゲート電極となり、ＣＭＯＳトランジスタ１５が構成される。
また、半導体層１２を貫通して埋め込み配線層２１に接続する半導体層貫通配線１６が形成されている。 In the sensor chip 1b, an interlayer insulating layer 20 is formed on a support substrate 30, and an embedded wiring layer 21 is embedded therein. A semiconductor layer 12 is formed as an upper layer, and surface insulating films (11, 19) are formed on the surface thereof.
In the semiconductor layer 12, a photodiode 14, an alignment mark 13 that functions as a test electrode, and the like are formed. A part of the buried wiring layer 21 becomes a gate electrode formed on the semiconductor layer 12 via a gate insulating film, and the CMOS transistor 15 is configured.
In addition, a semiconductor layer through wiring 16 that penetrates the semiconductor layer 12 and is connected to the buried wiring layer 21 is formed.

さらに、支持基板３０を貫通する支持基板貫通配線３１が形成されており、支持基板３０の表面から突出する突起電極（バンプ）３２が支持基板貫通配線３１の表面に形成されている。
一方で、例えば半導体層１２及び層間絶縁層２０を貫通して支持基板貫通配線３１に接続する半導体層絶縁層貫通配線１７が形成されており、半導体層貫通配線１６と半導体層絶縁層貫通配線１７とが表面絶縁膜１１上に形成された接続配線１８により接続されている。
支持基板貫通配線３１は、本実施形態では上記のように半導体層絶縁層貫通配線１７、接続配線１８、半導体層貫通配線１６を介して埋め込み配線層２１に接続する構成となっているが、これに限らず、これらの内の一部を介して、あるいはこれらを介さず直接、埋め込み配線層２１に接続するような構成であってもよい。 Further, a support substrate through wiring 31 penetrating the support substrate 30 is formed, and protruding electrodes (bumps) 32 protruding from the surface of the support substrate 30 are formed on the surface of the support substrate through wiring 31.
On the other hand, for example, a semiconductor layer insulating layer through wiring 17 that penetrates the semiconductor layer 12 and the interlayer insulating layer 20 and is connected to the support substrate through wiring 31 is formed. The semiconductor layer through wiring 16 and the semiconductor layer insulating layer through wiring 17 are formed. Are connected by a connection wiring 18 formed on the surface insulating film 11.
In this embodiment, the support substrate through wiring 31 is configured to be connected to the embedded wiring layer 21 through the semiconductor layer insulating layer through wiring 17, the connection wiring 18, and the semiconductor layer through wiring 16, as described above. However, the present invention is not limited thereto, and may be configured to be connected to the embedded wiring layer 21 through a part of them or directly without them.

上記の構成のセンサチップ１ｂは、半導体層１２中に形成されたフォトダイオード１４に対して、表面絶縁膜（１１，１９）側から光が照射されると信号電荷が発生し、フォトダイオードに蓄積される構成であり、光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に複数の画素に接続する埋め込み配線が形成され、半導体層の他方の面が光電変換素子の受光面となる裏面照射型の固体撮像素子である。   In the sensor chip 1b configured as described above, when the photodiode 14 formed in the semiconductor layer 12 is irradiated with light from the surface insulating film (11, 19) side, a signal charge is generated and accumulated in the photodiode. The embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer where the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed, and the other surface of the semiconductor layer is the photoelectric conversion. This is a back-illuminated solid-state imaging device that serves as a light-receiving surface of the device.

上記のセンサチップ１ｂは、光照射側の反対側である支持基板３０側から、表面に配線４０及びそれらを絶縁する絶縁層４１が形成されたインタポーザ３上に、絶縁層の開口部から配線の表面の一部が露出してなるランドなどとバンプが接合するようにフリップチップで実装されている。
一方、周辺回路部が形成された信号処理チップ２は、例えばバンプを介してフリップチップでインタポーザ上に実装されている。
このような構成の電子装置が、インタポーザごと他の実装基板に実装され、例えばワイヤボンディング４２などにより電気的に接続されて用いられる。
本実施形態に係るＣＭＯＳ固体撮像素子を組み込んだイメージセンサの構成及び画素の構成は、第１実施形態と同様である。 The above-described sensor chip 1b is formed on the interposer 3 on the surface of which the wiring 40 and the insulating layer 41 for insulating them are formed from the support substrate 30 side opposite to the light irradiation side. Flip chips are mounted so that bumps are bonded to lands or the like that are partially exposed on the surface.
On the other hand, the signal processing chip 2 in which the peripheral circuit portion is formed is mounted on the interposer by flip chip through bumps, for example.
The electronic device having such a configuration is mounted on another mounting substrate together with the interposer, and is used by being electrically connected, for example, by wire bonding 42 or the like.
The configuration of the image sensor and the pixel configuration incorporating the CMOS solid-state imaging device according to this embodiment are the same as those in the first embodiment.

上記の本実施形態に係る裏面照射型のＣＭＯＳ固体撮像素子の製造方法について説明する。
まず、図８（ａ）に示すように、例えば、シリコンなどからなる半導体基板１０の表面に、熱酸化法あるいはＣＶＤ（化学気相成長）法などにより、酸化シリコンなどからなり、後工程で表面絶縁膜となる絶縁膜１１を形成する。
さらに、例えば、絶縁膜１１の上層に、例えば貼り合わせ法あるいはエピタキシャル成長法などにより、シリコンなどの半導体層１２を形成し、ＳＯＩ基板とする。ここで、半導体層１２にテスト用電極として機能可能なアライメントマーク１３を形成しておく。 A manufacturing method of the backside illumination type CMOS solid-state imaging device according to the present embodiment will be described.
First, as shown in FIG. 8A, for example, the surface of a semiconductor substrate 10 made of silicon or the like is made of silicon oxide or the like by a thermal oxidation method or a CVD (chemical vapor deposition) method. An insulating film 11 to be an insulating film is formed.
Further, for example, a semiconductor layer 12 such as silicon is formed on the insulating film 11 by, for example, a bonding method or an epitaxial growth method to form an SOI substrate. Here, an alignment mark 13 that can function as a test electrode is formed on the semiconductor layer 12.

次に、図８（ｂ）に示すように、例えば導電性不純物をイオン注入して、半導体層１２中に光電変換素子としてフォトダイオード１４を形成し、さらに半導体層１２の表面にゲート絶縁膜を介してゲート電極を形成し、フォトダイオード１４などに接続してＣＭＯＳトランジスタ１５を形成して、上記の構成の複数の画素を形成する。
さらに、例えばＣＭＯＳトランジスタを被覆する層間絶縁層２０を形成する。このとき、トランジスタや半導体層１２などに接続するように埋め込み配線層２１を層間絶縁層２０中に埋め込みながら形成する。 Next, as shown in FIG. 8B, for example, conductive impurities are ion-implanted to form a photodiode 14 as a photoelectric conversion element in the semiconductor layer 12, and a gate insulating film is formed on the surface of the semiconductor layer 12. A gate electrode is formed, and connected to a photodiode 14 or the like to form a CMOS transistor 15 to form a plurality of pixels having the above-described configuration.
Further, for example, an interlayer insulating layer 20 covering the CMOS transistor is formed. At this time, the buried wiring layer 21 is formed while being buried in the interlayer insulating layer 20 so as to be connected to the transistor, the semiconductor layer 12 and the like.

一方で、シリコン基板あるいは絶縁性の樹脂基板などからなる支持基板３０の一方の主面の表面から少なくとも所定の深さにまで至る支持基板貫通配線となる支持基板配線３１を形成し、次に、図８（ｃ）に示すように、層間絶縁層２０の上層に、支持基板３０を支持基板配線３１の形成面側から貼り合わせる。   On the other hand, a support substrate wiring 31 serving as a support substrate through wiring extending from the surface of one main surface of the support substrate 30 made of a silicon substrate or an insulating resin substrate to at least a predetermined depth is formed. As shown in FIG. 8C, the support substrate 30 is bonded to the upper layer of the interlayer insulating layer 20 from the formation surface side of the support substrate wiring 31.

次に、図９（ａ）に示すように、例えばＳＯＩ基板の半導体基板１０側からフォトダイオード１４が受光可能となるまで、半導体基板１０を薄膜化する。例えば、絶縁膜１１をストッパとし、絶縁膜１１が露出するまで半導体基板１０の裏面側から機械的研削またはウェットエッチングなどにより行う。これにより、ＳＯＩ基板の半導体層１２が残される構成となる。図面上、図８（ｃ）に対して上下関係を逆にして図示している。   Next, as shown in FIG. 9A, the semiconductor substrate 10 is thinned until, for example, the photodiode 14 can receive light from the semiconductor substrate 10 side of the SOI substrate. For example, the insulating film 11 is used as a stopper, and mechanical grinding or wet etching is performed from the back side of the semiconductor substrate 10 until the insulating film 11 is exposed. As a result, the semiconductor layer 12 of the SOI substrate is left. In the drawing, the vertical relationship is reversed with respect to FIG.

次に、図９（ｂ）に示すように、支持基板配線３１と埋め込み配線層２１を接続する接続配線を形成する。
具体的には、例えば、半導体層１２を貫通して埋め込み配線層２１に接続する半導体層貫通配線１６を形成し、半導体層１２及び層間絶縁層２０を貫通して支持基板貫通配線３１に接続する半導体層絶縁層貫通配線１７を形成し、半導体層貫通配線１６と半導体層絶縁層貫通配線１７とを接続する接続配線１８を形成する。この後、保護膜となる表面絶縁膜１９を形成する。 Next, as shown in FIG. 9B, a connection wiring for connecting the support substrate wiring 31 and the embedded wiring layer 21 is formed.
Specifically, for example, the semiconductor layer through wiring 16 that penetrates the semiconductor layer 12 and is connected to the embedded wiring layer 21 is formed, and the semiconductor layer 12 and the interlayer insulating layer 20 are connected to the support substrate through wiring 31. The semiconductor layer insulating layer through wiring 17 is formed, and the connection wiring 18 for connecting the semiconductor layer through wiring 16 and the semiconductor layer insulating layer through wiring 17 is formed. Thereafter, a surface insulating film 19 serving as a protective film is formed.

次に、図１０（ａ）に示すように、例えば機械的研削などにより、支持基板配線３１が露出するまで貼り合わせ面の反対側から支持基板３０を薄膜化して、支持基板配線３１を、支持基板３０を貫通する支持基板貫通配線とする。   Next, as shown in FIG. 10A, the support substrate wiring 31 is supported by thinning the support substrate 30 from the opposite side of the bonding surface until the support substrate wiring 31 is exposed, for example, by mechanical grinding or the like. A support substrate through wiring penetrating the substrate 30 is used.

次に、図１０（ｂ）に示すように、例えば金属メッキ処理などにより、支持基板３０の表面から突出するバンプ３２を支持基板貫通配線３１の表面に形成する。
以上のようにして、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１ｂが形成される。 Next, as shown in FIG. 10B, bumps 32 protruding from the surface of the support substrate 30 are formed on the surface of the support substrate through wiring 31 by, for example, metal plating.
As described above, the backside illumination type CMOS solid-state imaging device (sensor chip) 1b according to the present embodiment is formed.

上記のように形成された裏面照射型ＣＭＯＳ固体撮像素子（センサチップ）１ｂを、受光面側を上向きにしてバンプ３２を介してフリップチップでインタポーザ上に実装し、信号処理チップ２も同様にフリップチップで実装し、裏面照射型ＣＭＯＳ固体撮像素子(センサチップ)１ｂと信号処理チップ２とをインタポーザ３に形成された配線を介して接続する。
以上のようにして、本実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を組み込んだイメージセンサを製造することができる。 The back-illuminated CMOS solid-state imaging device (sensor chip) 1b formed as described above is mounted on the interposer by flip chip through the bump 32 with the light receiving surface facing upward, and the signal processing chip 2 is similarly flipped. The backside illumination type CMOS solid-state imaging device (sensor chip) 1b and the signal processing chip 2 are connected via a wiring formed on the interposer 3.
As described above, an image sensor incorporating the backside illumination type CMOS solid-state imaging device according to the present embodiment can be manufactured.

本実施形態においては、半導体基板上に形成された埋め込み配線と支持基板中の貫通電極を直接接続するのではなく、半導体基板の裏面の薄膜化後に、配線によって貫通電極と埋め込み配線とを接続する。この方法では信号処理デバイスと支持基板の裏面に形成したマイクロバンプで接続するためにワイヤボンディングを行う必要がなく、１チップ化したときのサイズをより小さくすることができる。
上記のように、本実施形態の裏面照射型ＣＭＯＳ固体撮像素子の製造方法によれば、支持基板を貼り合わせて強度を確保してから半導体基板を薄膜化しており、また、支持基板を薄膜化して貫通配線を形成するので、簡便、容易に、照射面の反対側の面から電極を取り出す構成の裏面照射型のＣＭＯＳ固体撮像素子を製造することができる。 In the present embodiment, the embedded wiring formed on the semiconductor substrate and the through electrode in the support substrate are not directly connected, but the through electrode and the embedded wiring are connected by the wiring after the back surface of the semiconductor substrate is thinned. . In this method, it is not necessary to perform wire bonding in order to connect the signal processing device to the micro-bump formed on the back surface of the support substrate, and the size when it is made into one chip can be further reduced.
As described above, according to the backside illumination type CMOS solid-state imaging device manufacturing method of the present embodiment, the semiconductor substrate is thinned after the supporting substrates are bonded together to ensure strength, and the supporting substrate is thinned. Therefore, a backside illumination type CMOS solid-state imaging device having a configuration in which an electrode is taken out from the surface opposite to the irradiation surface can be manufactured easily and easily.

上記のように、本実施形態のＣＭＯＳ固体撮像素子を組み込んだＣＭＯＳイメージセンサでは、画素から出力される信号を画素単位もしくは複数の画素単位ごとに直接マイクロバンプを介して信号処理デバイスに入力させることが可能となる。これによって、デバイス間の信号処理スピードが速く高性能で、イメージセンサと信号処理デバイスを１チップ化した高機能なデバイスを提供することが可能となる。またワイヤボンディングによってチップやウェハーに接続する必要がないため、チップサイズを縮小することができ、ウェハーの収率が上がり、チップコストを下げることができる。   As described above, in the CMOS image sensor incorporating the CMOS solid-state imaging device of the present embodiment, a signal output from a pixel is directly input to a signal processing device via a micro bump for each pixel unit or a plurality of pixel units. Is possible. Accordingly, it is possible to provide a high-performance device in which the signal processing speed between devices is high and the performance is high, and the image sensor and the signal processing device are integrated into one chip. Further, since there is no need to connect to a chip or wafer by wire bonding, the chip size can be reduced, the yield of the wafer can be increased, and the chip cost can be reduced.

本発明は、上記の実施形態の説明に限定されない。
例えば、上記の実施形態においては半導体基板としてＳＯＩ基板を使用しているが、これに限らず、通常の半導体基板を用いて、フォトダイオードやトランジスタの形成面の反対側の面から薄膜化することも可能である。
また、支持基板から突出して形成されるバンプはチップ面積全体に形成でき、例えばＣＭＯＳイメージセンサの画素ごとに独立したバンプを形成してインタポーザなどに接続し、画素ごとに読み出すことができるようにしてもよい。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。 The present invention is not limited to the description of the above embodiment.
For example, in the above embodiment, an SOI substrate is used as a semiconductor substrate. However, the present invention is not limited to this, and a normal semiconductor substrate is used to reduce the thickness from the surface opposite to the photodiode or transistor formation surface. Is also possible.
In addition, bumps protruding from the support substrate can be formed over the entire chip area. For example, an independent bump is formed for each pixel of the CMOS image sensor, connected to an interposer, and read out for each pixel. Also good.
In addition, various modifications can be made without departing from the scope of the present invention.

図１は本発明の第１実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を実装した電子装置の構成を示す模式断面図である。FIG. 1 is a schematic cross-sectional view showing the configuration of an electronic device mounted with a backside illumination type CMOS solid-state imaging device according to the first embodiment of the present invention. 図２は本発明の第１実施形態に係るＣＭＯＳ固体撮像素子を組み込んだイメージセンサの構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of an image sensor incorporating the CMOS solid-state imaging device according to the first embodiment of the present invention. 図３は本発明の第１実施形態に係るＣＭＯＳ固体撮像素子の画素の構成を示す等価回路図である。FIG. 3 is an equivalent circuit diagram showing a configuration of a pixel of the CMOS solid-state imaging device according to the first embodiment of the present invention. 図４（ａ）〜（ｃ）は本発明の第１実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。4A to 4C are cross-sectional views illustrating the manufacturing process of the back-illuminated CMOS solid-state imaging device according to the first embodiment of the present invention. 図５（ａ）及び（ｂ）は本発明の第１実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。FIGS. 5A and 5B are cross-sectional views showing the manufacturing process of the back-illuminated CMOS solid-state imaging device according to the first embodiment of the present invention. 図６（ａ）及び（ｂ）は本発明の第１実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。6A and 6B are cross-sectional views showing the manufacturing process of the backside illumination type CMOS solid-state imaging device according to the first embodiment of the present invention. 図７は本発明の第２実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子を実装した電子装置の構成を示す模式断面図である。FIG. 7 is a schematic cross-sectional view showing the configuration of an electronic device on which the backside illumination type CMOS solid-state imaging device according to the second embodiment of the present invention is mounted. 図８（ａ）〜（ｃ）は本発明の第２実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。FIGS. 8A to 8C are cross-sectional views illustrating manufacturing steps of the backside illumination type CMOS solid-state imaging device according to the second embodiment of the present invention. 図９（ａ）及び（ｂ）は本発明の第２実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。FIGS. 9A and 9B are cross-sectional views showing manufacturing steps of a backside illuminated CMOS solid-state imaging device according to the second embodiment of the present invention. 図１０（ａ）及び（ｂ）は本発明の第２実施形態に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。FIGS. 10A and 10B are cross-sectional views showing manufacturing steps of the backside illumination type CMOS solid-state imaging device according to the second embodiment of the present invention. 図１１は従来例に係る裏面照射型ＣＭＯＳ固体撮像素子を実装した電子装置の構成を示す模式断面図である。FIG. 11 is a schematic cross-sectional view showing a configuration of an electronic device in which a backside illumination type CMOS solid-state imaging device according to a conventional example is mounted. 図１２（ａ）〜（ｃ）は従来例に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。12 (a) to 12 (c) are cross-sectional views showing a manufacturing process of a back-illuminated CMOS solid-state imaging device according to a conventional example. 図１３（ａ）及び（ｂ）は従来例に係る裏面照射型ＣＭＯＳ固体撮像素子の製造工程を示す断面図である。13 (a) and 13 (b) are cross-sectional views showing a manufacturing process of a back-illuminated CMOS solid-state imaging device according to a conventional example.

符号の説明Explanation of symbols

１ａ，１ｂ…センサチップ、２…信号処理チップ、３…インタポーザ、１０…半導体基板、１１…（表面）絶縁膜、１２…半導体層、１３…アライメントマーク、１４…フォトダイオード（光電変換素子）、１５…トランジスタ、１６…半導体層貫通電極、１７…半導体層絶縁層貫通配線、１８…接続配線、１９…表面絶縁膜、２０…層間絶縁層、２１…埋め込み配線、３０…支持基板、３１…支持基板貫通配線（支持基板配線）、３２…バンプ（突起電極）、４０…配線、４１…絶縁層、４２…ワイヤボンディング、１１２…撮像画素部、１１４…Ｖ選択手段、１１６…Ｈ選択手段、１１８…タイミングジェネレータ（ＴＧ）、１２０…Ｓ／Ｈ・ＣＤＳ回路部、１２２…ＡＧＣ部、１２４…Ａ／Ｄ変換部、１２６…デジタルアンプ部、２００…フォトダイオード（ＰＤ）、２１０…フローティングディフュージョン部（ＦＤ部）、２２０…転送トランジスタ、２３０…リセットトランジスタ、２４０…増幅トランジスタ、２５０…アドレストランジスタ、２６０…垂直信号線、２７０…定電流源   DESCRIPTION OF SYMBOLS 1a, 1b ... Sensor chip, 2 ... Signal processing chip, 3 ... Interposer, 10 ... Semiconductor substrate, 11 ... (Surface) insulating film, 12 ... Semiconductor layer, 13 ... Alignment mark, 14 ... Photodiode (photoelectric conversion element), DESCRIPTION OF SYMBOLS 15 ... Transistor, 16 ... Semiconductor layer penetration electrode, 17 ... Semiconductor layer insulation layer penetration wiring, 18 ... Connection wiring, 19 ... Surface insulation film, 20 ... Interlayer insulation layer, 21 ... Embedded wiring, 30 ... Support substrate, 31 ... Support Through-substrate wiring (supporting substrate wiring), 32... Bump (projection electrode), 40 .. wiring, 41 .. Insulating layer, 42 .. Wire bonding, 112... Imaging pixel section, 114. ... Timing generator (TG), 120 ... S / H / CDS circuit section, 122 ... AGC section, 124 ... A / D conversion section, 126 ... Digital amplifier section, 20 ... photodiode (PD), 210 ... floating diffusion portion (FD portion), 220 ... transfer transistors, 230 ... reset transistor, 240 ... amplifier transistor, 250 ... address transistor, 260 ... vertical signal line, 270 ... constant current source

Claims (9)

一方の主面に光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層と、
前記半導体層の前記一方の主面に形成され、前記複数の画素に接続して形成された埋め込み配線と、
前記半導体層の前記一方の主面に貼り合わされた支持基板と、
前記埋め込み配線に接続するように前記支持基板を貫通して形成された貫通配線と
を有し、
前記半導体層の他方の主面側が前記光電変換素子の受光面となる裏面照射型である
固体撮像素子。 A semiconductor layer in which a plurality of pixels including a photoelectric conversion element and a field effect transistor are formed on one main surface;
Embedded wiring formed on the one main surface of the semiconductor layer and connected to the plurality of pixels;
A support substrate bonded to the one main surface of the semiconductor layer;
A through-wiring formed through the support substrate so as to connect to the embedded wiring;
A solid-state imaging device that is a backside illumination type in which the other main surface side of the semiconductor layer is a light receiving surface of the photoelectric conversion device. 前記支持基板の表面から突出する突起電極が前記貫通配線の表面に形成されている
請求項１に記載の固体撮像素子。 The solid-state imaging device according to claim 1, wherein a protruding electrode protruding from a surface of the support substrate is formed on a surface of the through wiring. 前記貫通配線が、前記支持基板から前記半導体層までを貫通して形成されている
請求項１に記載の固体撮像素子。 The solid-state imaging element according to claim 1, wherein the through wiring is formed to penetrate from the support substrate to the semiconductor layer. 光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に前記複数の画素に接続する埋め込み配線が形成され、前記半導体層の他方の面が前記光電変換素子の受光面となる裏面照射型固体撮像素子の製造方法であって、
半導体基板の一方の主面に前記光電変換素子と電界効果トランジスタを含む複数の画素を形成する工程と、
前記半導体基板の一方の主面に前記複数の画素に接続する埋め込み配線を形成する工程と、
前記半導体基板の前記一方の主面に支持基板を貼り合わせる工程と、
貼り合わせ面の反対側から前記支持基板を薄膜化する工程と、
前記埋め込み配線に接続するように前記支持基板を貫通する貫通配線を形成する工程と、
前記半導体基板の他方の主面側から前記光電変換素子が受光可能となるまで、前記半導体基板の他方の主面側から前記半導体基板を薄膜化して前記半導体層とする工程と
を有する固体撮像素子の製造方法。 Embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed, and the other surface of the semiconductor layer is received by the photoelectric conversion element. A method for manufacturing a backside illuminated solid-state imaging device to be a surface,
Forming a plurality of pixels including the photoelectric conversion element and a field effect transistor on one main surface of a semiconductor substrate;
Forming embedded wiring connected to the plurality of pixels on one main surface of the semiconductor substrate;
Bonding a support substrate to the one main surface of the semiconductor substrate;
A step of thinning the support substrate from the opposite side of the bonding surface;
Forming a through wiring penetrating through the support substrate so as to connect to the embedded wiring;
A step of thinning the semiconductor substrate from the other main surface side of the semiconductor substrate to form the semiconductor layer until the photoelectric conversion element can receive light from the other main surface side of the semiconductor substrate. Manufacturing method. 前記貫通配線を形成する工程の後に、前記支持基板の表面から突出する突起電極を前記貫通配線の表面に形成する工程をさらに有する
請求項４に記載の固体撮像素子の製造方法。 The method for manufacturing a solid-state imaging element according to claim 4, further comprising a step of forming a protruding electrode protruding from a surface of the support substrate on a surface of the through wiring after the step of forming the through wiring. 前記半導体基板が、主たる基板上に絶縁膜を介して半導体層が形成されてなるＳＯＩ（semiconductor on insulator）基板であり、
前記半導体基板の他方の主面側から前記半導体基板を薄膜化する工程においては、前記絶縁膜が露出するまで前記主たる基板を除去する
請求項４に記載の固体撮像素子の製造方法。 The semiconductor substrate is an SOI (semiconductor on insulator) substrate in which a semiconductor layer is formed on a main substrate via an insulating film,
The method for manufacturing a solid-state imaging element according to claim 4, wherein in the step of thinning the semiconductor substrate from the other main surface side of the semiconductor substrate, the main substrate is removed until the insulating film is exposed. 光電変換素子と電界効果トランジスタを含む複数の画素が形成された半導体層の一方の面に前記複数の画素に接続する埋め込み配線が形成され、前記半導体層の他方の面が前記光電変換素子の受光面となる裏面照射型固体撮像素子の製造方法であって、
半導体基板の一方の主面に前記光電変換素子と電界効果トランジスタを含む複数の画素を形成する工程と、
前記半導体基板の一方の主面に前記複数の画素に接続する埋め込み配線を形成する工程と、
支持基板の一方の主面の表面から少なくとも所定の深さにまで至る支持基板配線を形成する工程と、
前記半導体基板の一方の主面と前記支持基板の一方の主面を貼り合わせる工程と、
前記半導体基板の他方の主面側から前記光電変換素子が受光可能となるまで、前記半導体基板の他方の主面側から前記半導体基板を薄膜化して前記半導体層とする工程と、
前記支持基板配線と前記埋め込み配線を接続する接続配線を形成する工程と、
前記支持基板配線が露出するまで前記支持基板の他方の面側から前記支持基板を薄膜化して、前記支持基板配線を、前記支持基板を貫通する貫通配線とする工程と
を有する固体撮像素子の製造方法。 Embedded wiring connected to the plurality of pixels is formed on one surface of the semiconductor layer on which the plurality of pixels including the photoelectric conversion element and the field effect transistor are formed, and the other surface of the semiconductor layer is received by the photoelectric conversion element. A method for manufacturing a backside illuminated solid-state imaging device to be a surface,
Forming a plurality of pixels including the photoelectric conversion element and a field effect transistor on one main surface of a semiconductor substrate;
Forming embedded wiring connected to the plurality of pixels on one main surface of the semiconductor substrate;
Forming a support substrate wiring from the surface of one main surface of the support substrate to at least a predetermined depth;
Bonding one main surface of the semiconductor substrate and one main surface of the support substrate;
From the other main surface side of the semiconductor substrate until the photoelectric conversion element can receive light, thinning the semiconductor substrate from the other main surface side of the semiconductor substrate to form the semiconductor layer;
Forming a connection wiring for connecting the support substrate wiring and the embedded wiring;
Manufacturing the solid-state imaging device, comprising: thinning the support substrate from the other surface side of the support substrate until the support substrate wiring is exposed, and using the support substrate wiring as a through wiring penetrating the support substrate. Method. 前記支持基板配線を前記貫通配線とする工程の後に、前記支持基板の表面から突出する突起電極を前記貫通配線の表面に形成する工程をさらに有する
請求項７に記載の固体撮像素子の製造方法。 The method for manufacturing a solid-state imaging device according to claim 7, further comprising a step of forming a protruding electrode protruding from a surface of the support substrate on a surface of the through wiring after the step of using the support substrate wiring as the through wiring. 前記半導体基板が、主たる基板上に絶縁膜を介して半導体層が形成されてなるＳＯＩ基板であり、
前記半導体基板の他方の主面側から前記半導体基板を薄膜化する工程においては、前記絶縁膜が露出するまで前記主たる基板を除去する
請求項７に記載の固体撮像素子の製造方法。 The semiconductor substrate is an SOI substrate in which a semiconductor layer is formed on a main substrate via an insulating film,
The method for manufacturing a solid-state imaging device according to claim 7, wherein in the step of thinning the semiconductor substrate from the other main surface side of the semiconductor substrate, the main substrate is removed until the insulating film is exposed.
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