JP2012099843A - Solid state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image sensor, represented by a CMOS image sensor, which allows for microfabrication of pixels and a high aperture ratio by employing a backside light-receiving structure.SOLUTION: The solid state image sensor includes a silicon layer 31 having a photodiode 37, a wiring layer provided on the other surface of the silicon layer 31 opposite from the light-receiving surface, a photoelectric conversion region consisting of a P+ layer 45 provided on the surface layer on the other side in the silicon layer 31 and an N- type region 41 provided in the silicon layer 31, and a second conductivity type N+ region 44 having concentration higher than that of the photoelectric conversion region and provided between the photoelectric conversion region consisting of the P+ layer 45 and N- type region 41 in the silicon layer 31.

Description

  The present technology relates to a solid-state imaging device in which unit pixels including active elements that convert and output signal charges photoelectrically converted by a photoelectric conversion element are arranged in a matrix.

  Solid-state imaging devices are roughly classified into charge transfer type solid-state imaging devices typified by CCD image sensors and XY address type solid-state imaging devices typified by CMOS image sensors. Here, of these two types, an XY address type solid-state imaging device will be described with reference to FIG. 9 showing an example of a sectional structure of a CMOS image sensor.

  As is clear from FIG. 9, the CMOS image sensor includes a pixel unit 100 that photoelectrically converts incident light, a peripheral circuit unit 200 that drives a pixel to read a signal, performs signal processing on the signal, and outputs the signal. Are integrated on the same chip (substrate). In addition, a part of the wiring is shared by the transistors constituting the pixel portion 100 and the transistors constituting the peripheral circuit portion 200.

  The pixel unit 100 includes a photodiode 102 formed on the surface side of an N-type silicon substrate 101 having a thickness of about several hundred μm, and a color filter 105 and a wiring layer 103 and a passivation film 104 above the photodiode 102. The microlens 106 is arranged. The color filter 105 is provided for obtaining a color signal.

  In this pixel portion 100, since a transistor and a wiring exist between the photodiode 102 and the color filter 105, the ratio of the incident light to the photodiode 102 with respect to the incident light to the pixel portion 100, that is, the aperture ratio is increased. Therefore, incident light is condensed on the photodiode 102 through the wiring by the micro lens 106 (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 11-11960

  However, as described above, in the conventional technique that adopts a pixel structure that takes incident light into the photodiode 102 through the wiring layer 103, a part of the light collected by the microlens 106 is bounced by the wiring. The following causes various problems.

(1) The sensitivity decreases because the amount of light is reduced by the amount bounced by the wiring.
(2) A part of the light bounced by the wiring enters the photodiode of the adjacent pixel, and color mixing occurs.
(3) The characteristics are deteriorated due to wiring restrictions such as the inability to place a wiring on the photodiode 102 or the passage of a thick wiring, and it is difficult to miniaturize a pixel.
(4) Since the ratio of light that is obliquely incident and bounces increases in the peripheral pixels, darker shading occurs in the peripheral pixels.
(5) It is difficult to make a CMOS image sensor by an advanced CMOS process in which the number of wiring layers is further increased because the distance from the microlens 106 to the light receiving surface of the photodiode 102 increases.
(6) The CMOS process library advanced in (5) above can no longer be used, the circuit layout in the library can be redesigned, the wiring layer is limited, the area increases, and the cost increases. The pixel area per pixel also increases.

Furthermore, when long wavelength light such as red is photoelectrically converted in the P well 107 at a position deeper than the photodiode 102 in FIG. If a pixel that has been shielded from light in order to cause color mixing or black is detected, the black level may be detected incorrectly.

  In recent years, in CMOS image sensors, functions that were previously separate chips, such as camera signal processing circuits and DSPs (Digital Signal Processors), tend to be mounted on the same chip as the pixel unit. Since the process generation evolves from 0.4 μm → 0.25 μm → 0.18 μm → 0.13 μm, the CMOS image sensor itself cannot receive the benefits of miniaturization unless it can cope with these new processes. In addition, an abundant CMOS circuit library and IP cannot be used.

  However, as the process generation progresses, the wiring structure becomes multilayered. For example, in the 0.4 μm process, the wiring has three layers, but in the 0.13 μm process, eight layers of wiring are used. In addition, the thickness of the wiring also increases, and the distance from the microlens 106 to the light receiving surface of the photodiode 102 becomes 3 to 5 times. Therefore, in the conventional front-illuminated pixel structure that guides light to the light receiving surface of the photodiode 102 through the wiring layer, light cannot be efficiently collected on the light receiving surface of the photodiode 102. As a result, the above (1) The problem of (6) is remarkable.

  On the other hand, the charge transfer type solid-state imaging device includes a back side light receiving type frame transfer CCD image sensor that receives light from the back side. In this backside light receiving type frame transfer CCD image sensor, a silicon substrate is thinned and light is received on the backside (backside), and signal charges photoelectrically converted in the silicon are captured by a depletion layer extending from the front side, and a potential well on the front side. Are stored and output.

  An example of the cross-sectional structure of the photodiode is shown in FIG. In this example, the photodiode is formed by the P-type region 303 on the surface on the oxide film 302 side where wiring and the like are formed on the silicon substrate 301, and the depletion layer 305 is formed by the N-type well (epi layer) 304. It has a structure covered through. On the oxide film 302, an aluminum reflective film 306 is formed.

In the case of the back side light receiving type CCD image sensor having the above structure, there is a problem that the blue sensitivity with high absorptance is lowered. Further, signal charges generated by light incident on the back surface and photoelectrically converted at a shallow position enter the surrounding photodiodes at a diffused rate. In addition to these problems, the CCD image sensor does not require system-on-chip, so there is no need to increase the height of the wiring layer, and since it is a unique process, the light-shielding film can be dropped around the photodiode. Condensing with a chip lens is easy, the problems (1) to (6) described above do not occur, and there is no need to adopt a backside light receiving structure, so backside light receiving type CCD image sensors are rarely used. is the current situation.

  On the other hand, in the case of a CMOS image sensor, the process uses a standard CMOS process with a slight modification. By adopting a backside light receiving structure, the process is always up-to-date without being affected by the wiring process. There is an advantage that the CCD image sensor can use. However, the point that wiring runs vertically and horizontally is different from the CCD image sensor, and the problems (1) to (6) mentioned above are associated with the CMOS image sensor (XY address type represented by this). This is a remarkable problem specific to solid-state imaging devices.

  The present technology has been made in view of the above-described problems. The object of the present technology is to reduce the pixel size and increase the aperture by adopting a back surface light receiving structure in a solid-state imaging device represented by a CMOS image sensor. An object of the present invention is to provide a solid-state imaging device capable of increasing the efficiency.

  A solid-state imaging device according to the present technology includes a semiconductor layer having a photoelectric conversion element, a wiring layer provided on the other surface opposite to the light receiving surface in the semiconductor layer, and the other surface side in the semiconductor layer. A first conductivity type layer provided in a surface layer; a second conductivity type photoelectric conversion region provided in the semiconductor layer; and a second conductivity type having a higher concentration than the photoelectric conversion region, wherein the semiconductor And a second conductivity type layer provided between the first conductivity type layer and the photoelectric conversion region in the layer.

  The solid-state imaging device having such a configuration adopts a back-illuminated pixel structure in which a wiring layer is provided on the other surface opposite to the light receiving surface with respect to the semiconductor layer provided with the photoelectric conversion region. This eliminates the need for wiring in consideration of the light receiving surface. That is, wiring on the photoelectric conversion element region is possible. Accordingly, the degree of freedom of pixel wiring is increased, and the pixel can be miniaturized.

  According to the present technology, in the solid-state imaging device, by adopting a back surface light receiving type pixel structure, wiring that takes the light receiving surface into consideration is not necessary, so that the degree of freedom of pixel wiring is increased and the pixel is miniaturized. Will be able to.

It is a schematic structure figure showing an example of a CMOS image sensor concerning one embodiment of this art. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is sectional drawing which shows an example of the structure of a pixel part and a peripheral circuit part. It is a cross-section figure showing an example of the well structure of a silicon layer. It is a plane pattern diagram showing an active region (region of gate oxide film), a gate (polysilicon) electrode, and a contact portion between them. It is a plane pattern figure which shows the metal wiring above a gate electrode, and the contact part between them with an active region. It is process drawing (the 1) for demonstrating the process which produces the CMOS image sensor of a back surface light reception type pixel structure. It is process drawing (2) for demonstrating the process which produces the CMOS image sensor of a back surface light reception type pixel structure. It is sectional drawing which shows the conventional structure of a CMOS image sensor. It is sectional drawing which shows the cross-section of the photodiode of a back surface receiving type frame transfer CCD image sensor.

  Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In the present embodiment, a CMOS image sensor will be described as an example of an XY address type solid-state imaging device.

  FIG. 1 is a schematic configuration diagram illustrating an example of a CMOS image sensor according to an embodiment of the present technology. As is apparent from FIG. 1, this CMOS image sensor includes a pixel unit 11, a vertical (V) selection circuit 12, an S / H (sample / hold) & CDS (Correlated Double Sampling) circuit 13, a horizontal ( H) A selection circuit 14, a timing generator (TG) 15, an AGC (Automatic Gain Control) circuit 16, an A / D conversion circuit 17, a digital amplifier 18, etc. are mounted on the same substrate (chip) 19. It becomes the composition.

  The pixel unit 11 has a configuration in which a large number of unit pixels, which will be described later, are arranged in a matrix, and address lines and the like are arranged in rows and vertical signal lines are arranged in columns. The vertical selection circuit 12 sequentially selects pixels in units of rows and reads out pixel signals from each pixel in the selected row to the S / H & CDS circuit 13. The S / H & CDS circuit 13 performs a process of subtracting 0 level from the signal level for the read pixel signal, removing fixed pattern variation (noise) for each pixel, and holding it.

  The horizontal selection circuit 14 sequentially extracts the pixel signals held in the S / H & CDS circuit 13 and passes them to the AGC circuit 16. The AGC circuit 16 amplifies the signal with an appropriate gain and passes it to the A / D conversion circuit 17. The A / D conversion circuit 17 converts the analog signal into a digital signal and passes it to the digital amplifier 18. The digital amplifier 18 appropriately amplifies the digital signal and outputs it. The operations of the vertical selection circuit 12, the S / H & CDS circuit 13, the horizontal selection circuit 14, the AGC circuit 16, the A / D conversion circuit 17 and the digital amplifier 18 are performed based on various timing signals generated by the timing generator 15. Is called.

  An example of the circuit configuration of a unit pixel, which is a specific part of the CMOS image sensor, is shown in FIG. As can be seen from the figure, the unit pixel has, for example, a photodiode 21 as a photoelectric conversion element, and a transfer transistor 22, an amplification transistor 23, an address transistor 24, and a reset transistor 25 are associated with this one photodiode 21. The four transistors are configured as active elements.

  The photodiode 21 is grounded at its anode, and photoelectrically converts incident light into charges (here, electrons) in an amount corresponding to the amount of light. The transfer transistor 22 is connected between the cathode of the photodiode 21 and the floating diffusion FD, and a transfer signal is given to the gate through the transfer wiring 26, whereby the electrons photoelectrically converted by the photodiode 21 are transferred to the floating diffusion FD. Forward.

  The gate of the amplification transistor 23 is connected to the floating diffusion FD. The amplification transistor 23 is connected to the vertical signal line 27 via the address transistor 24, and constitutes a constant current source I and a source follower outside the pixel portion. When an address signal is applied to the gate of the address transistor 25 through the address wiring 28 and the address transistor 25 is turned on, the amplification transistor 23 amplifies the potential of the floating diffusion FD and applies a voltage corresponding to the potential to the vertical signal line 27. Output to. The vertical signal line 27 transmits the voltage output from each pixel to the S / H & CDS circuit 13.

  The reset transistor 25 is connected between the power supply Vdd and the floating diffusion FD, and resets the potential of the floating diffusion FD to the potential of the power supply Vdd when a reset signal is given to the gate through the reset wiring 29. In these operations, since the wirings 26, 28, and 29 to which the gates of the transfer transistor 22, the address transistor 24, and the reset transistor 25 are connected are wired in units of rows, the pixels for one row are simultaneously processed. Is called.

  Here, as the wiring for the unit pixel, there are three transfer wirings 26, address wirings 28 and reset wirings 29 in the horizontal direction, one vertical signal line 27 in the vertical direction, Vdd supply wiring, and floating diffusion FD. There is an internal wiring that connects the gate of the amplifying transistor 23 and a two-dimensional wiring that is not shown here, but is used as a light shielding film for a pixel boundary portion and a black level detection pixel.

  FIG. 3 is a cross-sectional view illustrating an example of the structure of the pixel portion and the peripheral circuit portion. In FIG. 3, the wafer is polished by CMP (Chemical Mechanical Polishing) to form a silicon (Si) layer (element layer) 31 having a thickness of about 10 to 20 μm. Desirable ranges of the thickness are 5 to 15 μm for visible light, 15 to 50 μm for infrared light, and 3 to 7 μm for ultraviolet region. A light shielding film 33 is formed on one surface side of the silicon layer 31 with the SiO 2 film 32 interposed therebetween.

  Unlike the wiring, the light shielding film 33 is laid out in consideration of only optical elements. An opening 33 </ b> A is formed in the light shielding film 33. On the light shielding film 33, a silicon nitride film (SiN) 34 is formed as a passivation film, and a color filter 35 and a micro lens 36 are formed above the opening 33A. That is, the light that enters from one surface side of the silicon layer 31 has a pixel structure that is guided to the light receiving surface of a photodiode 37 that will be described later formed in the silicon layer 31 via the microlens 36 and the color filter 35. ing. On the other surface side of the silicon layer 31, a wiring layer 38 on which transistors and metal wirings are formed is formed, and a substrate support member 39 is further attached below the wiring layer 38.

  Here, in the conventional CMOS image sensor, the wiring layer side is the front surface side, and the surface light receiving type pixel structure that takes in incident light from the wiring layer side is adopted. On the other hand, the CMOS image sensor according to this embodiment Then, since incident light is taken in from the surface (back surface) side opposite to the wiring layer 38, a back-surface light receiving type pixel structure is formed. As is apparent from this backside light receiving pixel structure, the light shielding layer 33 only exists as a metal layer between the microlens 36 and the photodiode 37, and the light shielding layer 33 has a high height from the photodiode 37. Is as low as the thickness of the SiO 2 film 32 (for example, about 0.5 μm), it is possible to eliminate the limitation of light collection due to the squeezing in the metal layer.

  FIG. 4 is a sectional view showing an example of the well structure of the silicon layer 31. In FIG. 4, the same parts as those in FIG.

  In this example, an N-type substrate 41 is used. As described above, the thickness of the silicon layer 31 is desirably 5 to 15 μm for visible light, and is 10 μm in this example. Thereby, visible light can be favorably photoelectrically converted. A shallow P + layer 42 is formed on the entire surface of the pixel portion on one surface of the silicon layer 31. The pixel isolation region is formed by a deep P well 43 and is connected to the P + layer 42 on one surface.

  The photodiode 37 is formed using the N− type substrate 41 by not forming the P well. This N− type region (substrate) 41 is a photoelectric conversion region, and is completely depleted because its area is small and the concentration is low. An N + region 44 for accumulating signal charges (electrons in this example) is formed thereon, and a P + layer 45 for forming a buried photodiode is further formed thereon.

  As is clear from FIG. 4, the photodiode 37 is formed so that the surface area on the light receiving surface side is larger than the surface area on the wiring layer 38 side. Thereby, incident light can be taken in efficiently. The signal charge photoelectrically converted by the photodiode 37 and accumulated in the N + region 44 is transferred to an FD (floating diffusion) 47 in the N + type region by the transfer transistor 46 (transfer transistor 22 in FIG. 2). The photodiode 37 side and the FD 47 are electrically separated by the P− layer 48.

  Transistors other than the transfer transistor 46 in the pixel (the amplification transistor 23, the address transistor 24, and the reset transistor 25 in FIG. 2) are normally formed in the deep P well 42. On the other hand, in the peripheral circuit region, a P-well 49 is formed at a depth that does not reach the P + layer 42 on the back surface, and an N-well 50 is further formed inside the P-well 49. A circuit is formed.

  Next, pixel layout examples will be described with reference to FIGS. 5 and 6, the same parts as those in FIG. 2 are denoted by the same reference numerals. FIG. 5 is a plan pattern diagram showing an active region (a region of a gate oxide film), a gate (polysilicon) electrode, and a contact portion between them. As is clear from the figure, there is one photodiode (PD) 21 and four transistors 22 to 25 per unit pixel.

  FIG. 6 is a plan pattern diagram showing the metal wiring above the gate electrode and the contact portion between them together with the active region. Here, the metal wiring (for example, aluminum wiring) has a three-layer structure. The first layer is a wiring in a pixel, and the second layer is a vertical wiring, that is, a vertical signal line 27 or a drain line. The third layer is used as a horizontal wiring, that is, a transfer wiring 26, an address wiring 28, and a reset wiring 29, respectively.

  As is apparent from the wiring pattern of FIG. 6, the vertical signal line 27, the transfer wiring 26, the address wiring 28, and the reset wiring 29 are wired on the photodiode region. These wirings are formed avoiding the photodiode region because the conventional pixel structure adopts a surface-receiving type pixel structure that takes in light from the wiring layer side. On the other hand, in the pixel structure according to the present embodiment, as apparent from FIG. 3, since the back-side light-receiving pixel structure that takes in light from the side opposite to the wiring layer (back side) is employed, The wiring can be routed above.

  As described above, in the XY address type solid-state image pickup device represented by the CMOS image sensor, the photodiode 37 adopts the back side light receiving type pixel structure that receives the visible light from the back side. Since there is no need for wiring that takes into consideration the light-receiving surface as in the pixel structure, the degree of freedom of wiring of the pixel is increased, the pixel can be miniaturized, and it is manufactured by an advanced CMOS process with many wiring layers. Can do.

  Further, since the photodiode 37 is formed at a depth that reaches the P + layer 45 on the back surface, the sensitivity of blue having a high absorptance is high, and photoelectric conversion is not performed deeper than the photodiode 37. , There is no need to worry about mixed colors and false detection of black levels. Further, as is clear from FIG. 3 in particular, since the wiring layer 38 does not exist on the light receiving surface side, the light shielding film 33, the color filter 35, and the microlens 36 can be made at a low position with respect to the light receiving surface. Problems such as sensitivity reduction, color mixing, and peripheral light reduction in the prior art can be solved.

  Next, a process for producing a CMOS image sensor having a back-surface light-receiving pixel structure having the above configuration will be described with reference to the process diagrams of FIGS.

  First, element isolation and a gate electrode (polysilicon electrode) are formed on the surface of the N− type substrate 51, and a deep P well 43 in the pixel portion, a shallow P + layer 42 in the photodiode portion, and a peripheral circuit are formed by ion implantation. A shallow P well 49 and N well 50 are formed, and further, a transistor, a pixel active region, and the like are formed in the same process as the conventional CMOS image sensor (process 1). At this time, the substrate 51 is trenched by about several tens of μm in order to make an alignment mark for the back surface.

  Next, first to third layer metal wirings (1Al, 2Al, 3Al), pads (PAD) 52, and an interlayer film 53 are formed on the surface of the substrate 51 (step 2). At this time, for example, tungsten (W) or aluminum (Al) is embedded in the back surface alignment mark portion that has been trenched in step 1 to form the alignment mark 54. Subsequently, a first substrate support material (for example, glass, silicon, organic film, etc.) 55A is poured into the upper surface of the wiring layer with a thickness of several hundreds μm (step 3). At this time, the pad 52 is masked with a resist 56.

  Next, the resist 56 above the pad 52 is removed, and surface treatment is performed so that metal flows into the resulting bumps (step 4). Subsequently, the conductor 57 is poured into the bumps opened on the pad 52 and the surface of the first substrate support member 55A (step 5). Thereafter, the conductor 57 on the surface of the substrate support 55 is removed leaving only the upper part of the pad 52 (step 6). This remaining portion becomes the pad 52 '.

  Next, a second substrate support 55B is poured to protect the pad 52 'during the back surface processing and the surface is flattened, and then polished, and the wafer is turned upside down until the thickness of the substrate 51 reaches about 10 μm. (Step 7). Subsequently, a SiO 2 film is formed with a thickness of about 10 nm by CVD (Chemical Vapor Deposition), and then a resist is placed in alignment with the alignment mark 54, and boron that fills the SiO 2 interface with holes on the entire pixel portion is dosed. (Step 8). In step 8, a SiO2 film 58 is formed on the back surface with a thickness of about 500 nm by CVD, a light shielding film 59 is formed with Al or W, and then a plasma SiN film is formed as a passivation film 60 by CVD.

  Next, the color filter 61 and the microlens 62 are formed by the same method as in the case of the conventional CMOS image sensor (step 9). At this time, the stepper alignment is performed by using the alignment mark 54 or by using the light shielding film 59. Subsequently, the second substrate support material 55B on the pad 52 'is removed by etching to expose the pad 52' (step 10). At this time, if necessary, the second substrate support material 55B is polished and adjusted to a desired thickness in order to align the microlens 62 and flatten the chip.

  According to the manufacturing method described above, the back-surface light receiving type pixel structure can be easily created, and in addition, the pad 52 ′ can be formed on the side opposite to the light receiving surface. The CMOS image sensor can be directly mounted on the substrate in the state of facing upward.

DESCRIPTION OF SYMBOLS 11 ... Pixel part, 12 ... Vertical selection circuit, 14 ... Horizontal selection circuit, 15 ... Timing generator, 21, 37 ... Photodiode, 22 ... Transfer transistor, 23 ... Amplification transistor, 24 ... Address transistor, 25 ... Reset transistor, 31 ... Silicon (Si) layer 33 ... Light-shielding film 35 ... Color filter 36 ... Microlens 38 ... Wiring layer

Claims (13)

A semiconductor layer having a photoelectric conversion element;
A wiring layer provided on the other surface of the semiconductor layer opposite to the light receiving surface;
A first conductivity type layer provided in a surface layer on the other surface side in the semiconductor layer;
A second conductivity type photoelectric conversion region provided in the semiconductor layer;
A second conductivity type having a higher concentration than the photoelectric conversion region, and a second conductivity type layer provided between the first conductivity type layer and the photoelectric conversion region in the semiconductor layer;
A solid-state imaging device. The solid-state imaging device according to claim 1, wherein a second first conductivity type layer is provided on a surface layer on the light receiving surface side in the semiconductor layer. The solid-state imaging device according to claim 2, wherein the photoelectric conversion region reaches the second first conductivity type layer from the other surface side. The solid-state imaging device according to claim 1, wherein a first conductivity type well is provided in the semiconductor layer so as to surround the photoelectric conversion region. A second first conductivity type layer is provided on the surface layer on the light receiving surface side in the semiconductor layer,
The solid-state imaging device according to claim 1, wherein the first conductivity type well is formed from the other surface to the second first conductivity type layer. 6. The solid-state imaging device according to claim 4, wherein the first conductivity type well has a surface area on the other surface side larger than a surface area on the light receiving surface side. The wiring layer is provided with a gate electrode that transfers signal charges from the photoelectric conversion element,
The solid-state imaging element according to claim 1, wherein a separation layer disposed adjacent to the first conductivity type layer is provided in the semiconductor layer below the gate electrode. The solid-state imaging device according to claim 1, wherein the photoelectric conversion region has a surface area on the light receiving surface side wider than that on the other surface side. The semiconductor layer includes a peripheral circuit region together with a pixel region in which the photoelectric conversion regions are arranged,
9. The solid-state imaging device according to claim 1, wherein a second first conductivity type layer is provided on a surface layer on the light receiving surface side of the pixel region and the peripheral circuit region in the semiconductor layer. The semiconductor layer includes a peripheral circuit region together with a pixel region in which the photoelectric conversion regions are arranged,
A second first conductivity type well is provided on a surface portion of the peripheral circuit region on the other surface side in the semiconductor layer;
The solid-state imaging device according to claim 1, wherein the second first conductivity type well does not reach a surface portion of the semiconductor layer on the light receiving surface side.   The solid-state imaging device according to claim 10, wherein a second conductivity type well is formed adjacent to the second first conductivity type well in the peripheral circuit region. The semiconductor layer includes a peripheral circuit region together with a pixel region in which the photoelectric conversion regions are arranged,
On the light receiving surface of the semiconductor layer, a light shielding film that covers a peripheral circuit region together with the pixel region and has an opening on the photoelectric conversion region,
Incident light is taken into the photoelectric conversion region from the opening.
The solid-state image sensor in any one of Claims 1-11. The solid-state imaging device according to claim 12, wherein an insulating film is disposed between the semiconductor layer and the light shielding film.

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