JP4123446B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

  The present invention relates to a method for manufacturing a solid-state imaging device used as various image sensors and camera modules.

In recent years, video cameras and electronic cameras have become widespread, and CCD and amplification type solid-state imaging devices are used for these cameras.
Among these, an amplification type solid-state imaging device (CMOS image sensor) includes an imaging pixel unit configured by two-dimensionally arranging a plurality of pixels on one semiconductor chip, and a peripheral circuit unit disposed outside the imaging pixel unit. Each pixel of the imaging pixel unit has an FD unit and various MOS transistors for transfer, amplification, etc., and photoelectrically converts light incident on each pixel by a photodiode to generate a signal charge, This signal charge is transferred to the FD portion by the transfer transistor, the potential fluctuation of the FD portion is detected by the amplification transistor, and this is converted into an electric signal, and the signal for each pixel is transmitted from the signal line to the peripheral circuit portion. Is output.
The peripheral circuit section includes a signal processing circuit that performs predetermined signal processing, such as CDS (correlated double sampling), gain control, A / D conversion, and the like on the pixel signal from the imaging pixel section, and each of the imaging pixel section. Drive control circuits that drive the pixels and control the output of the pixel signals, such as vertical and horizontal scanners and timing generators (TG), are provided.

FIG. 11 is a cross-sectional view showing the element structure of a conventional CMOS image sensor, showing the structure of one pixel 10 in the imaging pixel portion and one MOS transistor 20 provided in the peripheral circuit portion.
The pixel 10 in the imaging pixel unit is provided with a P-type well region 11 on an N-type silicon substrate 1, and a photodiode 12 and an FD unit 13 are provided therein. The upper insulating layer 2 of the N-type silicon substrate 1 has a transfer gate polysilicon transfer electrode 14 for transferring a signal charge from the photodiode 12 to the FD portion 13, and a metal wiring 15 such as aluminum on the upper layer. 16 is further provided, and a light shielding film 17 having a light receiving opening of the photodiode 12 is provided thereon.
Further, a passivation film 3 made of a silicon nitride film or the like is provided on the upper insulating layer 2, and an on-chip color filter 18 and an on-chip microlens 19 are provided on the upper layer.

  On the other hand, the MOS transistor 20 in the peripheral circuit portion is provided with a P-type well region 21 on an N-type silicon substrate 1, and a source region 22 and a drain region 23 are provided therein. A polysilicon gate electrode 24 of the MOS transistor 20 is provided on the upper insulating layer 2 of the N-type silicon substrate 1, and metal wirings 25, 26, 27 such as aluminum are provided on the upper layer, and further on the passivation film 3 on the upper layer. Also, a metal wiring 28 such as aluminum is provided.

In the solid-state imaging device having such a configuration, each pixel has incident light transmitted by the micro lens 19 in order to increase the aperture ratio of the photodiode 12 (ratio of incident light to the photodiode 12 with respect to incident light to the pixel). The light is condensed on the photodiode 12 through the wiring.
However, in this case, part of the light collected by the microlens 19 is bounced by the wirings 15 and 16. This causes the following problems.
1) The sensitivity is reduced by the amount bounced by the wiring.
2) A part of the light bounced by the wiring enters the photodiode of the adjacent pixel, and color mixing occurs.

3) Since the wiring layout is limited, the characteristics are degraded due to restrictions such as the inability to place the wiring on top of the photodiode or the inability to pass thick wiring.
4) Miniaturization is difficult for the same reason as 3) above.
5) Since the peripheral pixels have a large proportion of light that is obliquely incident and bounced, darker shading occurs in the periphery.
6) If a CMOS image sensor is manufactured by an advanced CMOS process in which the number of wiring layers is further increased, the distance from the microlens to the photodiode is increased, and the above-described difficulty is further increased.
7) Due to the above 6), the advanced CMOS process library cannot be used, and the layout of the circuit registered in the library can be changed again, or the wiring layer is limited and the area is increased. It will be up. In addition, the pixel area per pixel also increases.

In addition, when light having a long wavelength such as red is photoelectrically converted in the P-type well region 11 at a position deeper than the photodiode 12, the generated electrons diffuse in the P-type well region 11 and are moved to another position. If the pixel 12 enters the pixel 12 to cause color mixture or enters a pixel that is shielded to detect black, the black level is erroneously detected.
In addition, there is a process of using silicide in the active region. However, since silicide interferes with the incidence of light, it is necessary to add a process for removing only the silicide on the photodiode 12.
This increases the number of processes and makes the process complicated. The defect of the photodiode resulting from the process also occurs.

In addition, as described above, the peripheral pixel portion of the CMOS image sensor is equipped with functions such as a camera signal processing circuit and a DSP that have been configured with different chips so far.
Since these process generations evolve from 0.4 μm → 0.25 μm → 0.18 μm → 0.13 μm, the CMOS image sensor itself cannot receive the benefits of miniaturization unless it is compatible with these new processes. In addition, an abundant CMOS circuit library and IP cannot be used.
However, as the process generation progresses, the wiring structure becomes multilayered. For example, in the 0.4 μm process, the wiring has three layers, but in the 0.13 μm process, eight layers are used. In addition, the thickness of the wiring also increases, and the distance from the microlens to the light receiving surface of the photodiode becomes 3 to 5 times.
Therefore, in the conventional method of passing light through the wiring layer through the light receiving surface, the light cannot be efficiently collected on the light receiving surface of the pixel, and the problems 1) to 7) are remarkable.

Recently, a so-called back-illuminated solid-state imaging device in which a light receiving surface of a photodiode is provided on the back surface of a semiconductor chip has been proposed as a solid-state imaging device different from the above-described CMOS image sensor.
This is configured as a frame transfer type CCD image pickup device, in which a silicon substrate is thinned, a transfer electrode or the like is provided on the front surface side, and a light receiving surface of a photodiode is disposed on the back surface.
The light received on the light receiving surface is photoelectrically converted by a photodiode in the silicon substrate, and the signal charge is captured by a depletion layer extending from the substrate surface side, and accumulated in a potential well (P + type well region) on the surface side. And transfer and output.

FIG. 12 is a cross-sectional view showing an element structure of a photodiode portion in such a back-illuminated solid-state imaging element.
This solid-state imaging device comprises a photodiode by providing an N-type well region 31 by epitaxial growth on a thin P-type silicon substrate 30 and providing a P + type well region 33 via a depletion layer 32 thereon. is there.
An oxide film 34 and an aluminum light shielding film 35 are provided on the P + type well region 33.
In this case, the P-type silicon substrate 30 side is the back surface, that is, the light irradiation surface, and the oxide film 34 and the aluminum light-shielding film 35 side are the front surfaces. For example, wiring for transfer electrodes and the like are arranged.

However, the imaging device having such a structure has a problem that the blue sensitivity with high absorptance is lowered. In addition, since light is incident on the back surface and photoelectrically converted at a shallow position, the generated signal charges are diffused and enter a surrounding photodiode at a certain rate.
On the other hand, in the case of a CCD type image pickup device, since there is no system-on-chip, there is no need to increase the height of the wiring layer, and since it is a process unique to CCD, the light shielding film can be dropped around the photodiode. For the reason, it is easy to collect light with an on-chip lens, and thus the problems 1) to 7), which are problems in the case of the CMOS image sensor as described above, do not occur.
Under these circumstances, back-illuminated CCD image sensors are rarely used, and there are almost no on-chip color filters and microlenses in such back-illuminated CCD image sensors. It seems not to.

On the other hand, in the case of a CMOS image sensor, the process uses a standard CMOS process with a slight modification. By adopting the backside illumination type described above, it is not affected by the wiring process and is always the latest. There is an advantage that the process can be used in the case of a CCD type imaging device.
In addition, the fact that the metal wiring runs vertically and horizontally is a point that the CCD type image sensor does not have. Therefore, unlike the case of the CCD type image sensor, the above problems 1) to 7) are particularly problematic in the CMOS image sensor. From this point of view as well, it is advantageous to adopt the above-described back-illuminated type for the CMOS image sensor.

However, when a color filter and an on-chip microlens are formed on a normal CMOS image sensor wafer, the stepper is positioned using a metal wiring layer such as aluminum. In the case of manufacturing, after completing the wiring process to the wafer, the wafer is turned over and the surface opposite to the surface on which the wiring is provided is polished to form a silicon oxide film (SiO2), a light shielding film, a passivation film After the formation, steps such as formation of a back surface color filter and a back surface microlens are performed.
For this reason, in the production of the backside illumination type CMOS image sensor, there arises a problem that the alignment mark formed at the time of producing the aluminum wiring layer cannot be used as it is.

  Therefore, an object of the present invention is to easily and appropriately perform various alignments in manufacturing a so-called back-illuminated amplification type solid-state imaging device (CMOS image sensor), and to improve manufacturing efficiency and device accuracy. An object of the present invention is to provide a method for manufacturing a solid-state imaging device.

In order to achieve the above object, the present invention provides an imaging pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field effect transistor are arranged in a two-dimensional array on a semiconductor substrate, a drive circuit for driving the imaging pixel unit, and And a peripheral circuit unit including a signal processing circuit that processes a pixel signal output from the imaging pixel unit, and a wiring layer for driving a field effect transistor of the imaging pixel unit is formed on the first surface side of the semiconductor substrate And a light receiving surface of the photoelectric conversion element is disposed on the second surface side of the semiconductor substrate, and at least one of a color filter and a microlens is formed on the second surface side of the semiconductor substrate. When the imaging pixel unit and the peripheral circuit unit are formed on the semiconductor substrate from the first surface side, the field effect transistor is formed on the first surface of the semiconductor substrate. An active region in which a semiconductor metal compound is formed or a gate electrode for the field effect transistor is provided, and a first alignment mark is formed using a part of the active region, and then a first surface of the first surface of the semiconductor substrate is formed. Forming a wiring layer on the upper layer of the alignment mark, and then detecting the first alignment mark from the second surface side of the semiconductor substrate to thereby form a second alignment on the second surface side of the semiconductor substrate. A mark is formed, and then alignment is performed on the second surface of the semiconductor substrate using the second alignment mark to form at least one of the color filter and the microlens.

As described above, in the method for manufacturing a solid-state imaging device according to the present invention, an active region in which a semiconductor metal compound for a field effect transistor is formed on a wiring surface (first surface) opposite to an irradiation surface of a semiconductor substrate, or an electric field A first alignment mark is formed using the gate electrode for the effect transistor, and the first alignment mark is detected from the second surface side of the semiconductor substrate to thereby detect a second alignment mark on the second surface side of the semiconductor substrate. An alignment mark is formed, and color filters and microlenses are aligned using the second alignment mark.
Therefore, the first alignment mark using the metal compound or the electrode film, which is easier to detect than the mark using the conventional silicon oxide film or the like, is detected through the semiconductor substrate and is detected on the second surface side. 2 alignment marks can be formed, and color filters and microlenses can be aligned using the second alignment marks, and the alignment operation can be performed easily and appropriately. Accuracy can be improved.

Embodiments of a method for manufacturing a solid-state imaging device according to the present invention will be described below.
In this embodiment, an active region or a gate electrode (polysilicon) used in, for example, a MOS transistor manufacturing process in order to perform stepper alignment in a manufacturing process of a back-illuminated solid-state imaging device to cope with a new generation process. The alignment mark is formed on the wiring surface side using the film.

In addition, a silicide film using an active region can be used as the alignment mark, and the silicide film can be left on the photodiode (the surface opposite to the irradiation surface).
Thereafter, such an alignment mark is read from the back side with red light or near infrared light, and the stepper is aligned.
It is also possible to perform alignment by creating alignment marks on the silicon oxide film on the back surface (irradiation surface) side in accordance with the alignment marks on the wiring surface side.
As a result, a back-illuminated amplification type solid-state imaging device (CMOS image sensor) can be easily manufactured, and the above-described problems such as light collection can be solved.

First, an outline of the CMOS image sensor in this embodiment will be described.
FIG. 1 is a plan view schematically showing an outline of a CMOS image sensor according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram showing a configuration of a pixel of the CMOS image sensor shown in FIG.
The CMOS image sensor according to this example includes an imaging pixel unit 112 formed on a semiconductor chip 110, a V selection unit 114, an H selection unit 116, a timing generator (TG) 118, an S / H / CDS unit 120, an AGC unit 122, An A / D unit 124, a digital amplifier unit 126, and the like are included.

  The imaging pixel unit 112 has a large number of pixels arranged in a two-dimensional matrix, and each pixel is a photoelectric conversion element that generates and accumulates signal charges corresponding to the amount of received light as shown in FIG. A diode (PD) 200 is provided, and further, a transfer transistor 220 that transfers signal charges converted and accumulated by the photodiode 200 to a floating diffusion portion (FD portion) 210, and a reset transistor that resets the voltage of the FD portion 210 230, an amplification transistor 240 that outputs an output signal corresponding to the voltage of the FD section 210, and a selection (address) transistor 250 that outputs the output signal of the amplification transistor 240 to the vertical signal line 260 are provided. ing.

In the pixel having such a configuration, the signal charge photoelectrically converted by the photodiode 200 is transferred to the FD unit 210 by the transfer transistor 220. The FD unit 210 is connected to the gate of the amplification transistor 240. The amplification transistor 240 forms a source follower with a constant current source 270 provided outside the imaging pixel unit 112. Therefore, when the address transistor 250 is turned on, the FD unit A voltage corresponding to the voltage 210 is output to the vertical signal line 260.
The reset transistor 230 resets the voltage of the FD unit 210 to a constant voltage (drive voltage Vdd in the illustrated example) that does not depend on the signal charge.
In addition, various drive wirings for driving and controlling each MOS transistor are wired in the imaging pixel unit 112 in the horizontal direction, and each pixel in the imaging pixel unit 112 is horizontally lined (pixels) by the V selection unit 114. Each pixel is sequentially selected, and the MOS transistor of each pixel is controlled by various pulse signals from the timing generator 118, so that the signal of each pixel passes through the vertical signal line 260 for each S / H / CDS unit 120 for each pixel column. Is read out.

The S / H • CDS unit 120 is provided with an S / H • CDS circuit for each pixel column of the imaging pixel unit 112, and performs CDS on the pixel signal read from each pixel column of the imaging pixel unit 112. Signal processing such as (correlated double sampling) is performed. Further, the H selection unit 116 outputs the pixel signal from the S / H / CDS unit 120 to the AGC unit 122.
The AGC unit 122 performs predetermined gain control on the pixel signal from the S / H • CDS unit 120 selected by the H selection unit 116, and outputs the pixel signal to the A / D unit 124.
The A / D unit 124 converts the pixel signal from the AGC unit 122 from an analog signal to a digital signal and outputs the converted signal to the digital amplifier 126. The digital amplifier 126 performs necessary amplification and buffering for the digital signal output from the A / D unit 124 and outputs it from an external terminal (not shown).
The timing generator 118 also supplies various timing signals to each part other than each pixel of the imaging pixel part 112 described above.

3 and 4 are schematic plan views showing specific examples of the pixel layout of the CMOS image sensor according to the present embodiment.
First, FIG. 3 shows the arrangement of active regions (regions in which a gate oxide film is disposed) of photodiodes and transistors, gate electrodes (polysilicon film), and contacts to them.
As shown in the figure, an active region 300 of each pixel includes a rectangular region 310 including the photodiode (PD) 200 and the FD portion 210 described above, and a bent portion extending in an L shape from one corner of the rectangular region 310. It is composed of a band-shaped region 320.
A contact 311 is provided in the FD portion 210 of the rectangular region 310, and a transfer gate electrode 312 is provided between the photodiode (PD) 200 and the FD portion 210, and a contact is made at the end of the transfer gate electrode 312. 313 is provided.

Further, in the bent band region 320, a reset gate electrode 321, an amplification gate electrode 322, and an address gate electrode 323 are provided in order, and contacts 324, 325, and 326 are provided at end portions of the gate electrodes 321, 322, and 323, respectively. Is provided. The contact 311 of the FD portion 210 and the contact 325 of the amplification gate electrode 322 are connected by an intra-pixel metal wiring.
Further, a contact 327 connected to the reset Vdd is provided between the reset gate electrode 321 and the amplification gate electrode 322, and a contact 328 connected to the vertical signal line 260 is provided at an end of the bent band region 320. Is provided.

FIG. 4 shows an upper layer metal wiring and a contact between them together with an active region. In this example, the metal wiring has three layers, the first layer is used as the intra-pixel wiring 330, the second layer is used as the vertical (vertical) wiring 340, and the third layer is in the horizontal (horizontal) direction. The wiring 350 is used.
These metal wirings 330, 340, and 350 are conventionally arranged so as to avoid the photodiode region, but here, they are also arranged on the upper side of the photodiode (that is, the surface opposite to the irradiation surface). It is very different. Obviously, in the conventional wiring method in which the wiring avoids the photodiode, the pixel having the size as shown in the figure cannot be laid out.

FIG. 5 is a cross-sectional view showing an element structure in the backside illuminated CMOS image sensor according to the present embodiment, and shows the structure of one pixel 400 in the imaging pixel portion and one MOS transistor 500 provided in the peripheral circuit portion. Yes. In FIG. 5, the upper side in the drawing is the irradiation surface (back surface) side, and the lower side is the wiring surface (front surface) side.
In this CMOS image sensor, the above-described three layers of metal wirings 330, 340, and 350 are provided inside a silicon oxide film layer 610 provided on a substrate support material (glass resin or the like) 600. The pixel 400 and the MOS transistor 500 described above are provided on a silicon layer (N-type silicon substrate) 620 provided on the film layer 610.
FIG. 5 shows a schematic configuration. Here, an outline of the element structure will be described, and details will be described later with reference to FIG.

In the pixel 400, a photodiode 420 is provided in a state of penetrating the silicon layer 620 in an intermediate portion of the P-type well regions 410A and 410B formed in a state of penetrating the silicon layer 620.
One P-type well region 410A is provided with the above-described FD portion 210, and the transfer gate electrode 312 described above is disposed inside the silicon oxide film layer 610 located between the photodiode 420 and the FD portion 210. Is provided.
In the MOS transistor 500, a P-type well region 510 is provided in a region of the N-type silicon layer 620 on the silicon oxide film 610 side, and source / drain (S / D) 520A and 520B are provided in the P-type well region 510. In addition, a gate electrode (polysilicon film) 530 is provided on the silicon oxide film layer 610 side.

A P + type region 630 is provided on the N-type silicon layer 620, and a silicon oxide film (SiO2) 640 is provided thereon. Further, a light shielding film 650 made of aluminum or the like is provided above the silicon oxide film 640, and an opening 650A corresponding to the light receiving region of the photodiode 420 is formed in the light shielding film 650.
Although not shown in the drawing, the black level detection pixel has the same element structure as that of the pixel 400 shown in FIG. 5, but an opening 650A of the light shielding film 650 is formed in the light receiving region. The signal charge without light reception is output as a black level reference signal.

Further, a silicon nitride film (SiN) 660 as a passivation layer is provided above the light shielding film 650, and further, a color filter 670 and a microlens 680 are provided in an area corresponding to the imaging pixel portion above the light shielding film 650. Arranged in an on-chip structure.
The wafer constituting such a CMOS image sensor is polished by CMP (chemical mechanical polishing) so that the silicon layer 620 has a thickness of, for example, about 10 μm.
In terms of the frequency characteristics of light, desirable film thickness ranges are 5 μm to 15 μm for visible light, 15 μm to 50 μm for infrared light, and 3 μm to 7 μm for the ultraviolet region.
Further, unlike the wiring, the light shielding film 650 can be laid out in consideration of only optical elements. The metal layer from the microlens 680 to the photodiode 420 is only the light shielding film 650, and the height of the light shielding film 650 from the photodiode 420 is the thickness of the silicon oxide film 640, for example, 0. Since it is as low as about 5 μm, unlike the above-described conventional example, it is possible to eliminate the limitation of light collection due to kicking by the metal wiring.

FIG. 6 is a cross-sectional view showing the well structure in the N-type silicon layer 620 described above in some detail. 6, the element structure shown in FIG. 6 is on the wiring surface (front surface) side and the lower side is the irradiation surface (back surface) side, contrary to FIG. In addition, elements that are the same as those in FIG.
The MOS transistor 500 in the peripheral circuit portion shows the same contents as in FIG. 5, but a low concentration N-type is used for the N-type silicon layer (silicon substrate) 620 as shown.
On the other hand, for the pixel 400 in the imaging pixel portion, a MOS transistor 430 other than the transfer transistor (that is, an amplification transistor, a reset transistor, or an address transistor in this example) is shown in addition to the contents of FIG.

As described above, the pixel 400 includes the deep P-type well regions 410A and 410B penetrating the silicon layer 620 and the photodiode 420 penetrating the silicon layer 620 in the middle thereof.
The photodiode 420 includes a shallow P + type layer 420A (a part of the P + type region 630) on the irradiation surface side, an N− type layer 420B (a part of the silicon layer 620) therein, and a deep P− on the wiring surface side. The FD portion 210 and the transfer transistor 220 are formed in the P-well region 420C on the wiring surface side.
Further, the N− type layer 420B is a photoelectric conversion region, and is completely depleted because the area is small and the concentration is low.

An N + type region 440 for accumulating signal charges is formed at a part of the boundary between the N− type layer 420B and the P− type well region 420C. Further, a P + type region 450 for forming a buried photodiode is provided adjacent to the N + type region 440 on the wiring surface side.
The signal charge is transferred to the N + type region of the FD unit 210 by the operation of the transfer transistor 220. When the transfer transistor 220 is off, the N + type regions on the photodiode 420 side and the FD portion 210 side are electrically separated by an intermediate P− type well region 420C.
The MOS transistors 430 other than the transfer transistor 220 are normally formed in the deep P-type well region 410A. N + type source / drain regions 431 and 432 are formed in the P-type well region 410A, and the upper layers thereof are formed. A gate electrode 433 is formed.

Next, a method for manufacturing a CMOS image sensor having the above configuration will be described.
7 to 10 are cross-sectional views showing the manufacturing process of the CMOS image sensor in this example.
(1) Element isolation and well formation First, an element isolation region and various well regions are formed on a silicon substrate (silicon layer 630) before thinning. Here, as described above, a deep P-type well region is formed in the pixel portion, and a shallow P-type well region and an N-type well region are formed in the peripheral circuit portion.

(2) Various transistors, wiring, and PAD formation As shown in FIGS. 7A and 7B, various MOS transistors, aluminum wiring, electrode PAD, and the like are formed using the same processes as those of the conventional CMOS image sensor. In this example, however, a stepper alignment mark is formed using the gate or active region of the MOS transistor.
As a proposal preceding this application, a method for forming a mark by forming a trench in the wafer at this stage and embedding tungsten, aluminum, or the like in this stage is proposed in order to perform backside stepper alignment in a later process. It was. In this method, a mark can be formed at a deep position of the substrate and a position close to the back surface, but impurities such as metal atoms easily enter the substrate from the portion. In that case, there is a problem that a pixel is defective with a certain probability, and a white dot appears in an image captured by the solid-state imaging device.

Therefore, in this embodiment, the alignment mark 700 is created by diverting the gate electrode (polysilicon) or active region formed for the MOS transistor. In particular, in the active region, it is more preferable to form a silicide (a compound of metal and silicon) such as cobalt silicide.
In this case, the silicide film can be left on the photodiode (the surface opposite to the irradiation surface). In this way, the process of removing the silicide film can be omitted, and the process can be simplified. Further, defects (white dots appear on the photographed image) resulting from the removal process can be eliminated.
Further, it is possible to prevent light incident from the back surface from being transmitted through the photodiode and reflected by the wiring and being photoelectrically converted by another photodiode.

(3) Attaching Substrate Support Material As shown in FIG. 7C, a glass material is poured into the wiring surface to create a substrate support material (specifically, a first-layer substrate support material) 600A. At this time, a resist 710 is patterned on the position where the PAD 722 is formed.
(4) PAD, contact formation As shown in FIG. 8D, the contact is exposed by removing the resist 710, opening a hole 711 in the substrate support material 600A, and performing a surface treatment. . Then, as shown in FIG. 8E, a contact metal is introduced into the holes 711 and the surface of the substrate support member 600A to form the contact 720, and as shown in FIG. 8F, the substrate support member is formed. An electrode PAD721 is formed by patterning the metal film on the surface of 600A.
Thereafter, as shown in FIG. 9G, the second-layer substrate support member 600B is poured onto the first-layer substrate support member 600A for polishing on the wiring side and polished.

(5) Back surface polishing Thereafter, the wafer is turned over and the back surface is polished by CMP until the thickness of the silicon layer 630 becomes about 10 μm.
(6) Formation of backside silicon oxide film A thin silicon oxide film (SiO2) 640A (a part of the silicon oxide film 640) is formed to a thickness of, for example, about 10 nm by, for example, CVD (chemical vapor deposition).
Here, as shown in FIG. 9G, the alignment mark 730 is formed on the backside silicon oxide film 640 in alignment with the alignment mark 700 formed by the gate layer formed on the wiring layer side or the active region added with silicide. Form. This is formed by etching the silicon oxide film 640A so that the silicon layer 630 is slightly removed.
Note that the formation of the alignment mark 730 on the back side is not necessarily essential as will be described later.

(7) Back surface p + implantation Next, boron is added by ion implantation through the silicon oxide film 640 so that the interface of the silicon oxide film is filled with holes.
In the above-mentioned proposal preceding the present application, the stepper is aligned using the alignment mark formed by the trench formed in advance on the wafer surface as described above. In this example, any of the following methods is used. Alignment can be performed.
(A) The gate layer or active region alignment mark 700 formed in (2) above is used.
(B) The alignment mark 730 formed on the silicon oxide film in (6) above is used.
Therefore, when the method (A) is used, the formation of the alignment mark 730 in (B) can be omitted.
In order to detect the alignment mark 700 on the wiring surface (front surface) side by the method (A), the detection efficiency can be improved by using red light or near infrared light having a wavelength of 0.61 μm to 1.5 μm.
(8) Formation of backside silicon oxide film Next, the remaining silicon oxide film 640B is formed to a thickness of, for example, 500 nm by CVD.

(9) Back-side light-shielding film formation Next, the light-shielding film 650 is formed of aluminum or tungsten by a CMOS process similar to the conventional one.
The alignment at this time is performed by the method (A) or (B) described in (7) above. Here, an alignment mark (not shown) for a color filter and a microlens to be created in a later process is created.
(10) Passivation film formation In this process, a plasma SiN film is formed by CVD (FIG. 9H).
(11) Color filter and microlens (OCL) formation (FIG. 10I)

The above (9) to (11) are performed by a method similar to the conventional method.
However, the stepper alignment is performed using the mark formed in (9). Further, when the light shielding film is not used, the method (A) or (B) described in (7) is used.
(12) PAD surface exposure Next, as shown in FIG. 10J, the second-layer substrate support member 600B on the electrode PAD721 described above is removed by etching to expose the electrode PAD721. At this time, for example, the second-layer substrate support member 600B is polished and adjusted to a desired thickness in order to align the microlenses and flatten the element chip. Further, since the electrode PAD721 portion is on the opposite side of the light receiving surface, the mounting can be directly attached to the substrate.

As described above, in the manufacturing method of the CMOS image sensor according to the present example, the alignment mark is formed by the gate layer or the active region on the wiring layer side of the silicon substrate, and the alignment of the light shielding film on the back surface or the color filter or the on-chip lens is performed. The alignment mark is formed on the back surface with reference to the gate layer on the wiring layer side and the active region having silicide, and is used for the alignment of the light shielding film, color filter or on-chip lens on the back surface.
Therefore, since it is not necessary to make a backside alignment mark in a special process, the process is simplified, and impurities such as metal atoms can enter the substrate from that portion and prevent defects.

In particular, when the active region is formed of silicide such as cobalt salicide, it is easy to detect the mark from the back surface. Further, when confirming the alignment mark on the wiring side from the back surface, the confirmation of the mark is facilitated by using red light or near infrared light having a wavelength of 0.61 to 1.5 μm.
Also, by not removing the silicide in the active region on the photodiode, the process can be reduced and simplified, and defects associated with the removal process can be reduced. Further, the light incident from the back surface is transmitted through the photodiode and wired. , And photoelectric conversion by another photodiode can be prevented.
With such a method, a back-illuminated CMOS image sensor with few defects and good characteristics can be formed with a small number of steps.

Further, the back-illuminated CMOS image sensor produced in this embodiment has the following advantages as basic effects.
First, by allowing the photodiode to receive visible light from the back surface, there is no need for wiring in consideration of the light receiving surface as in the prior art. Accordingly, the degree of freedom of pixel wiring is increased, and the pixel can be miniaturized.
In addition, since the photodiode reaches the back surface, the sensitivity of blue with high absorption rate is high, and since there is no photoelectric conversion deeper than the photodiode, it causes color mixing and black level errors. There is no detection.
In addition, since the light shielding film, the color filter, and the on-chip lens can be formed at a low position from the light receiving surface, the problems of sensitivity reduction, color mixing, and peripheral light reduction can be solved.
In addition, a CMOS image sensor can be formed by an advanced CMOS process with many wiring layers.
Furthermore, since the electrode PAD is disposed on the opposite side to the light receiving surface, it can be directly mounted on the substrate with the light receiving surface facing upward.

As mentioned above, although the specific Example of this invention was described, this is an example of this invention, and this invention can be variously changed.
For example, specific numerical values such as film thickness and materials shown in the manufacturing process described above are not intended to limit the present invention. Further, the structure of the solid-state imaging device to be manufactured is not limited to the above example. For example, the configuration of the pixel is not only four MOS transistors but also three MOS transistors or five MOS transistors. There may be. Needless to say, the wiring structure for driving the pixels is not limited to the above example.

It is a top view which shows typically the outline | summary of the backside illumination type CMOS image sensor by the example of embodiment of this invention. FIG. 2 is an equivalent circuit diagram illustrating a configuration of a pixel of the backside illumination type CMOS image sensor illustrated in FIG. 1. It is a schematic plan view which shows the specific example of the pixel layout of the backside illumination type CMOS image sensor shown in FIG. It is a schematic plan view which shows the specific example of the pixel layout of the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the element structure in the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the element structure in the backside illumination type CMOS image sensor shown in FIG. 1 in some detail. It is sectional drawing which shows the manufacturing process of the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the manufacturing process of the backside illumination type CMOS image sensor shown in FIG. It is sectional drawing which shows the element structure in the conventional CMOS image sensor. It is sectional drawing which shows the element structure of the photodiode part in the back surface irradiation type solid-state image sensor shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 ... Semiconductor chip, 112 ... Imaging pixel part, 114 ... V selection means, 116 ... H selection means, 118 ... Timing generator, 120 ... S / H * CDS part, 122 ... AGC part, 124 ... A / D section, 126 ... Digital amplifier section, 200, 420 ... Photodiode, 210 ... FD section, 220 ... Transfer transistor, 230 ... Reset transistor, 240 ... Amplification transistor, 250 ... Selection (Address) transistor, 260... Vertical signal line, 400... Pixel, 330, 340, 350... Metal wiring, 410 A, 410 B, 510. , 600... Substrate support material (glass resin, etc.) 610... Silicon oxide film layer 620... Silicon layer (N type) Recon substrate), 630... P + type region, 640... Silicon oxide film, 650... Shielding film, 650 A. , 700, 730... Alignment mark.

Claims (7)

An imaging pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field effect transistor are arranged in a two-dimensional array on a semiconductor substrate, a driving circuit for driving the imaging pixel unit, and a pixel signal output from the imaging pixel unit A peripheral circuit portion including a signal processing circuit for signal processing, a wiring layer for driving a field effect transistor of the imaging pixel portion is formed on the first surface side of the semiconductor substrate, and a light receiving surface of the photoelectric conversion element is A method of manufacturing a solid-state imaging device, which is disposed on the second surface side of the semiconductor substrate and at least one of a color filter and a microlens is formed on the second surface side of the semiconductor substrate,
When forming the imaging pixel unit and the peripheral circuit unit from the first surface side on the semiconductor substrate, an active region in which the semiconductor metal compound for the field effect transistor is formed on the first surface of the semiconductor substrate, or Providing a gate electrode for a field effect transistor, and forming a first alignment mark using a part of the gate electrode;
Thereafter, a wiring layer is formed above the first alignment mark on the first surface of the semiconductor substrate,
Thereafter, the second alignment mark is formed on the second surface side of the semiconductor substrate by detecting the first alignment mark from the second surface side of the semiconductor substrate,
Thereafter, the second surface of the semiconductor substrate is aligned using the second alignment mark to form at least one of the color filter and the microlens.
A method for manufacturing a solid-state imaging device. 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the semiconductor metal compound is a silicide film made of a compound of cobalt and silicon. 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the gate electrode is a polysilicon film. 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the first alignment mark is detected by irradiating detection light having a predetermined wavelength from the second surface side of the semiconductor substrate. The method of manufacturing a solid-state imaging device according to claim 4, wherein the detection light is red light or near infrared light. Forming a first alignment mark by forming each element of the imaging pixel unit and the peripheral circuit unit in an upper layer part on the first surface side of the semiconductor substrate;
A second step of forming a wiring layer of the imaging pixel unit and the peripheral circuit unit including an insulating film and a wiring film on an upper surface of the semiconductor substrate;
A third step of providing a substrate support on the upper surface of the wiring layer;
A fourth step of forming a thin film semiconductor layer by removing a lower layer portion of the semiconductor substrate and leaving an upper film;
A fifth step of forming a transparent insulating film on the lower surface of the thin film semiconductor layer and forming the second alignment mark;
A sixth step of forming at least one of the color filter and the microlens on the lower surface of the transparent insulating film;
The method for manufacturing a solid-state imaging device according to claim 1, wherein: The second alignment mark is formed on the lower surface of the thin film semiconductor layer by forming a transparent insulating film on the lower surface of the thin film semiconductor layer in the fifth step and partially removing the transparent insulating film. The method for manufacturing a solid-state imaging device according to claim 6, wherein a second alignment mark is formed.

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