WO2010131462A1 - Solid-state image pickup element - Google Patents

Solid-state image pickup element Download PDF

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Publication number
WO2010131462A1
WO2010131462A1 PCT/JP2010/003214 JP2010003214W WO2010131462A1 WO 2010131462 A1 WO2010131462 A1 WO 2010131462A1 JP 2010003214 W JP2010003214 W JP 2010003214W WO 2010131462 A1 WO2010131462 A1 WO 2010131462A1
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WO
WIPO (PCT)
Prior art keywords
pad
wiring
semiconductor substrate
solid
shielding film
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PCT/JP2010/003214
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French (fr)
Japanese (ja)
Inventor
藤井恭子
中野高宏
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パナソニック株式会社
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Publication of WO2010131462A1 publication Critical patent/WO2010131462A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a solid-state imaging device, and more particularly to a back-illuminated solid-state imaging device that receives light from a side opposite to a side on which a wiring layer of a semiconductor substrate is formed.
  • FIG. 6 is a cross-sectional view of a conventional back-illuminated solid-state imaging device 500.
  • the pixel portion 120 is formed on the semiconductor substrate 101.
  • a photodiode 102A as a dark pixel and a plurality of photodiodes 102 as pixels are arranged in the pixel portion 120.
  • the dark pixel is a pixel for optically determining a black signal.
  • the photodiodes 102A and 102 are formed in the semiconductor substrate 101.
  • an element (not shown) that forms a peripheral circuit is formed on the semiconductor substrate 101.
  • an antireflection film 104 and a light shielding film 105 are formed on a surface on which imaging light is incident (hereinafter referred to as a light incident surface).
  • the light shielding film 105 is formed so as to cover the photodiode 102A in order to shield light incident on the photodiode 102A as a dark pixel.
  • the light shielding film 105 is formed so that light is incident on the photodiode 102 as a pixel.
  • a wiring layer 113 is formed on the surface opposite to the light incident surface.
  • a plurality of wirings 103 are formed in the wiring layer 113. Note that a pad 106 for connection to the outside is exposed on the wiring layer 113.
  • the back-illuminated solid-state imaging device 500 has an advantage that the aperture ratio is not lowered by the wiring layer 113.
  • the light shielding film 105 shields the photodiode 102A as a dark pixel from light.
  • the light shielding film 105 changes its parasitic capacitance when charged. Therefore, in order to prevent the parasitic capacitance from affecting photoelectron accumulation, photoelectron readout, noise, and the like in the photodiodes 102A and 102, it is preferable that the potential of the light shielding film 105 is fixed to a constant potential. .
  • FIG. 7A is a cross-sectional view of a conventional back-illuminated solid-state imaging device 600.
  • the solid-state image sensor 600 in FIG. 7A receives imaging light from the upper part of the solid-state image sensor 600.
  • an opening 141 is formed on the light incident surface side of the semiconductor substrate 101 in order to expose the wiring 103 formed in the wiring layer 113.
  • a portion of the wiring 103 exposed to the outside through the opening 141 is a pad 106.
  • an opening 142 is formed on the light incident surface side of the semiconductor substrate 101 in order to expose a part of the light shielding film 105 to the outside.
  • a voltage can be applied to the light shielding film 105 from the outside.
  • a portion of the light shielding film 105 exposed to the outside through the opening 142 is a pad 109.
  • FIG. 7B shows a diagram in which a back-illuminated solid-state imaging device 600 is mounted on a package. 7B mainly shows the semiconductor substrate 101 by simplifying the solid-state imaging device 600 of FIG. 7A.
  • a support substrate 107 is attached to the side of the semiconductor substrate 101 where the wiring layer is formed.
  • the semiconductor substrate 101 is mounted on the package 110.
  • Openings 141 and 142 are formed on the light incident surface side of the semiconductor substrate 101 opposite to the side on which the wiring layer is formed. By forming the openings 141 and 142, the pads 106 and 109 are exposed to the outside.
  • the pad 106 formed on the semiconductor substrate 101 and the terminal 111 of the package 110 are electrically connected by the wire 114. Further, the pad 109 and the terminal 112 of the package 110 are electrically connected by a wire 114.
  • the pad 109 which is a part of the light shielding film 105 and the terminal 112 of the package 110 are electrically connected.
  • the potential of the light shielding film 105 can be fixed to a constant potential from the outside of the semiconductor substrate 101.
  • a necessary driving voltage can be supplied to the pad 106 which is a part of the wiring 103.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a solid-state imaging device that can fix the potential of the light shielding film without increasing the number of terminals of the package. That is.
  • a solid-state imaging device has a semiconductor substrate on which a pixel portion in which a plurality of pixels are arranged and light for imaging incident on the semiconductor substrate. Formed on the surface opposite to the light incident surface, the wiring layer including the wiring including the driving signal lines of the pixel portion, and the light input surface of the semiconductor substrate. A light-shielding film that shields a dark pixel for determining the light intensity.
  • the semiconductor substrate penetrates the semiconductor substrate from the light incident surface side in order to expose a pad, which is a part of the wiring for extracting a fixed potential, formed on the wiring layer to the light incident surface side at least in the manufacturing process. An opening is formed, and the pad and the light shielding film are electrically connected by wiring.
  • a pad formed in the wiring layer, which is a part of the wiring, and a light shielding film that shields a dark pixel for determining a black signal among the plurality of pixels are electrically connected by the wiring.
  • the potential of the light shielding film can be fixed at a constant potential. Accordingly, a change in parasitic capacitance due to charging of the light shielding film can be suppressed, and the parasitic capacitance can be prevented from affecting photoelectron accumulation, photoelectron readout, noise, and the like in the pixel.
  • the pad and the light shielding film are respectively connected to two different terminals in the package. There is no need to connect to. That is, an increase in the number of terminals of the package can be suppressed.
  • the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
  • the wiring that electrically connects the pad and the light shielding film is mainly made of Cu, and a metal is further laminated on the upper part of the pad, and the outermost surface of the metal is aluminum or an alloy containing aluminum. May be.
  • the wiring that electrically connects the pad, which is part of the wiring for extracting the fixed potential, and the light shielding film is made of Cu, the wiring is also formed on a vertical surface such as the opening of the pad. Can do.
  • probe inspection and wire bonding are facilitated by making the outermost surface of the metal laminated on the pad aluminum or an alloy containing aluminum.
  • the opening corresponding to the pad formed in the semiconductor substrate is formed so that the width of the opening becomes narrower from the light incident surface side toward the pad, and the pad and the light shielding film are electrically connected.
  • the wiring connected to may be aluminum or an aluminum alloy.
  • a support substrate is attached to the semiconductor substrate on the side where the wiring layer is formed, and a bump is formed on the side of the support substrate opposite to the light incident surface, and one of the wirings formed on the wiring layer is formed.
  • the pad which is a part and the bump may be electrically connected by a through electrode penetrating the support substrate.
  • the pad that is a part of the wiring and the light shielding film are electrically connected by the wiring. For this reason, the pads that are part of the wiring are electrically connected to the bumps, whereby the bumps and the light shielding film are electrically connected to each other through the through electrodes.
  • the potential of the light shielding film can be fixed through the through electrode.
  • a groove is formed so as to penetrate from the light incident surface of the semiconductor substrate to the surface opposite to the light incident surface so as to surround the opening corresponding to the pad, and an insulating film is embedded in the groove. Also good.
  • a trench embedded with an insulating film is formed so as to surround the opening corresponding to the pad, thereby electrically separating the wiring in the opening corresponding to the pad and the pixel formed in the semiconductor substrate. It becomes possible to do. Therefore, an insulating film for separating the pixel formed on the semiconductor substrate and the wiring for electrically connecting the pad and the light-shielding film becomes unnecessary, and the film forming and processing steps can be reduced.
  • the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
  • FIG. 1 is a cross-sectional view of a solid-state imaging device according to this embodiment.
  • FIG. 2 is a cross-sectional view of a solid-state imaging device according to Modification 1 of the present embodiment.
  • FIG. 3 is a cross-sectional view of a solid-state imaging device according to the second modification of the present embodiment.
  • FIG. 4 is a cross-sectional view of a package according to the third modification of the present embodiment.
  • FIG. 5 is a cross-sectional view of a solid-state imaging device according to Modification 4 of the present embodiment.
  • FIG. 6 is a cross-sectional view of a conventional back-illuminated solid-state imaging device.
  • FIG. 7A is a diagram showing a conventional back-illuminated solid-state imaging device.
  • FIG. 7B is a diagram illustrating a conventional back-illuminated solid-state imaging device.
  • FIG. 1 is a cross-sectional view of a solid-state imaging device 100 according to the present embodiment.
  • the solid-state imaging device 100 is a back-illuminated MOS (Metal Oxide Semiconductor) sensor.
  • MOS Metal Oxide Semiconductor
  • the solid-state imaging device 100 includes a semiconductor substrate 1.
  • the semiconductor substrate 1 is an SOI (Silicon-on-Insulator) substrate.
  • SOI Silicon-on-Insulator
  • the solid-state imaging device 100 forms a photodiode 2 as a light receiving region in the semiconductor substrate 1 and forms a wiring 3, and then removes other than the Si active layers 4 to 6 ⁇ m of the semiconductor substrate 1. Obtained.
  • the solid-state image sensor 100 receives light from the side opposite to the side on which the wiring 3 is formed.
  • the pixel portion 20 is formed on the semiconductor substrate 1.
  • a photodiode 2A as a dark pixel and a plurality of photodiodes 2 as pixels are arranged. That is, a plurality of pixels are arranged in the pixel unit 20.
  • Dark pixels are pixels for optically determining a black signal.
  • the dark pixel is a part of a plurality of pixels arranged in the pixel unit 20.
  • the photodiodes 2A and 2 are formed in the semiconductor substrate 1.
  • imaging light receives light for imaging (hereinafter referred to as imaging light) from above the solid-state imaging device 100.
  • imaging light light for imaging
  • an antireflection film 4 and a light shielding film 5 are formed on a surface on which imaging light is incident (hereinafter referred to as a light incident surface).
  • the antireflection film 4 is SiN deposited on the light incident surface of the semiconductor substrate 1 using a plasma CVD technique.
  • the thickness of the antireflection film 4 is, for example, 200 nm.
  • the light shielding film 5 is formed so as to cover the photodiode 2A in order to shield light incident on the photodiode 2A as a dark pixel. That is, the light shielding film 5 shields the photodiode 2A as a dark pixel.
  • the light shielding film 5 is formed so that light is incident on the photodiode 2 as a pixel.
  • the light shielding film 5 is aluminum patterned on the antireflection film 4 so as to cover the boundary of the photodiode 2 as a pixel.
  • the thickness of the light shielding film 5 is, for example, 200 nm.
  • the width of the aluminum pattern which is the light shielding film 5 is very fine, 0.2 ⁇ m or less. Therefore, the aluminum as the light shielding film 5 needs to be a thin film.
  • a wiring layer 13 is formed on the surface opposite to the light incident surface.
  • a plurality of wirings 3 are formed in the wiring layer 13.
  • Each of the plurality of wirings 3 is formed of copper (Cu).
  • the driving signal line is a signal line for driving the photodiode 2 ⁇ / b> A as a dark pixel and the plurality of photodiodes 2 as pixels included in the pixel unit 20. That is, the driving signal line is a signal line for driving the pixel unit 20.
  • An interlayer insulating film 7 is formed on part of the wiring layer 13.
  • the light incident surface side of the semiconductor substrate 1 and the interlayer insulating film 7 is dry-etched.
  • the technique forms the opening.
  • a portion of the wiring 3 exposed to the outside through the opening at the time when the opening is formed is the pad 6.
  • the opening is formed so as to penetrate the semiconductor substrate 1 from the light incident surface side in order to expose the pad 6 which is formed in the wiring layer 13 and is a part of the wiring 3 for extracting a fixed potential. .
  • a protective film is formed on the exposed portions of the antireflection film 4, the interlayer insulating film 7, the pad 6, and the light shielding film 5 using the plasma CVD technique. 8 is deposited.
  • the protective film 8 is SiN.
  • an opening 41 is formed by a dry etching technique in order to expose the wiring 3 including the driving signal line of the pixel unit 20.
  • a portion of the wiring 3 exposed to the outside by the opening 41 is the pad 6.
  • the opening 41 penetrates the semiconductor substrate 1 from the light incident surface side in order to expose the pad 6 formed in the wiring layer 13 as a part of the wiring 3 for extracting a fixed potential to the light incident surface side. To be formed.
  • the pad 6 is exposed to the outside (light incident surface side) at least during the manufacturing process of the solid-state imaging device 100.
  • an opening 42 is formed on the light incident surface side of the semiconductor substrate 1 by a dry etching technique in order to expose a part of the light shielding film 5 to the outside.
  • the portion of the light shielding film 5 exposed to the outside by the opening 42 at the time when the opening 42 is formed is the pad 9.
  • the wiring 10 is formed by a general construction method.
  • the wiring 10 includes a seed layer and copper (Cu) plating.
  • the wiring 10 is mainly composed of copper (Cu).
  • the wiring 10 is formed so as to electrically connect the pad 6 which is a part of the wiring 3 and the pad 9 which is a part of the light shielding film 5. That is, the pad 6 and the pad 9 are electrically connected by the wiring 10.
  • the organic passivation film 31 is formed so that portions other than the pad 6 are covered with the organic passivation film 31.
  • the solid-state imaging device 100 shown in FIG. 1 is formed.
  • the wiring 10 is not formed unlike the solid-state imaging device 100, and therefore a part of the wiring 3 including the driving signal line of the pixel unit 20
  • the pad 6 and the pad 9 which is a part of the light shielding film 5 need to be connected to the two terminals of the package, respectively. For this reason, there are problems that the number of terminals of the package increases and the package size increases.
  • the light shielding film 5 and the pad 6 that is a part of the wiring 3 formed in the wiring layer are electrically connected on the light incident surface side of the semiconductor substrate 1. Thereby, the potential of the light shielding film can be fixed to a constant potential.
  • the pad 6 And pad 9 need not each be connected to two different terminals in the package. Therefore, an increase in the number of terminals of the package can be suppressed. That is, an increase in the number of terminals taken out from the package can be suppressed.
  • the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
  • FIG. 2 is a cross-sectional view of a solid-state imaging device 100A according to Modification 1 of the present embodiment.
  • solid-state imaging device 100A metal 11 is deposited (laminated) in a portion corresponding to the upper portion of pad 6 in wiring 10 as compared with solid-state imaging device 100 in FIG. The point is different. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
  • Metal 11 is an alloy of aluminum and copper (Cu).
  • the outermost surface of the metal 11 is aluminum or an alloy containing aluminum (hereinafter also referred to as an aluminum alloy).
  • the wiring 10 is formed. Thereafter, a metal 11 is deposited on a portion of the wiring 10 corresponding to the upper portion of the pad 6 by a sputtering technique. The metal 11 is patterned by photolithography and wet etching techniques.
  • the outermost surface of the metal 11 is aluminum or an alloy containing aluminum, probe inspection and wire bonding can be easily performed.
  • FIG. 3 is a cross-sectional view of a solid-state imaging device 100B according to Modification 2 of the present embodiment.
  • solid-state imaging device 100 ⁇ / b> B is different from solid-state imaging device 100 of FIG. 1 in that opening 41 ⁇ / b> B is formed instead of opening 41, and opening 42 ⁇ / b> B is used instead of opening 42. Is different from the point that is formed. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
  • the opening 41 ⁇ / b> B is an opening corresponding to the pad 6 that is a part of the wiring 3.
  • the opening 41 ⁇ / b> B is formed such that the width of the opening becomes narrower as it approaches the pad 6 from the light incident side (light incident surface side).
  • a portion of the semiconductor substrate 1 corresponding to the upper portion of the pad 6 is subjected to a wet etching technique using TMAH so that the width of the opening is reduced to the light incident surface. It opens so that it may become narrow as it approaches the pad 6 from the side. Thereby, the side wall of the opening 41B is inclined as shown in FIG.
  • the protective film 8 is deposited on the exposed portions of the antireflection film 4, the interlayer insulating film 7, the pad 6, and the light shielding film 5 by the same process as in the first embodiment.
  • the interlayer insulating film 7 and the protective film 8 formed on the top of the pad 6 are opened using dilute HF (Diluted Hydrofluoric Acid).
  • the protective film 8 formed on the pad 9 which is a part of the light shielding film 5 is opened using dilute HF. Thereby, the opening 42B is formed.
  • the opening 42 ⁇ / b> B is an opening corresponding to the pad 9 that is a part of the light shielding film 5.
  • the wiring 10B is formed by a sputtering technique.
  • the wiring 10B is made of aluminum or aluminum alloy.
  • the wiring 10 ⁇ / b> B is formed so as to electrically connect the pad 6 that is a part of the wiring 3 and the pad 9 that is a part of the light shielding film 5. That is, the pad 6 and the pad 9 are electrically connected by the wiring 10B.
  • ⁇ Reliable aluminum alloy must be deposited using sputtering technology.
  • Sputtering technology is difficult to control because the deposition rate on the vertical surface is low. Therefore, by using the wet etching technique to incline the side wall of the opening 41B corresponding to the pad 6, wiring is possible even by the sputtering technique.
  • the wiring 10B since it is not necessary to use copper plating for the wiring 10B, a highly reliable wiring can be obtained at low cost.
  • the wiring since the wiring is made of aluminum or aluminum alloy, probe inspection and wire bonding of the wiring become easy.
  • FIG. 4 is a cross-sectional view of a package 210 according to the third modification of the present embodiment.
  • the package 210 is a chip size package.
  • the package 210 includes the solid-state imaging device 100B of FIG. 3 as an example.
  • the package 210 may include the solid-state image sensor 100 or the solid-state image sensor 100A instead of the solid-state image sensor 100B.
  • the organic passivation film 31 corresponds to the upper part of the pixel portion 20.
  • the on-chip filter 12 and the microlens 23 are formed in the portion to be performed.
  • the adhesive 14 is a heat-sparing epoxy adhesive.
  • a support substrate 16 is attached to the side where the wiring layer 13 opposite to the light receiving side is formed. That is, the support substrate 16 is attached to the semiconductor substrate 1 on the side where the wiring layer 13 is formed.
  • the support substrate 16 is a Si substrate.
  • the thickness of the support substrate 16 is, for example, 150 ⁇ m.
  • a through electrode 18 that is an electrode penetrating the support substrate 16 is formed.
  • the through electrode 18 is formed by copper (Cu) plating.
  • bumps 17 are formed on the side opposite to the light incident surface of the semiconductor substrate 1.
  • the bumps 17 are made of solder.
  • the through electrode 18 is pulled out to the lower part of the support substrate 16.
  • the wiring 3 in contact with the through electrode 18 is electrically connected to the pad 6.
  • the through electrode 18 electrically connects the wiring 3 electrically connected to the pad 6 and the bump 17. That is, the through electrode 18 electrically connects the pad 6 and the bump 17.
  • the pad 6 is electrically connected to the pad 9 which is a part of the light shielding film 5 by the wiring 10B. Therefore, the pads 6 and the bumps 17 are electrically connected to each other, whereby the bumps 17 and the pads 9 that are part of the light shielding film 5 are electrically connected.
  • the potential of the light shielding film 5 can be fixed through the through electrode 18 by fixing the potential of the bump 17.
  • the package 210 can be made into a chip size. That is, the size of the package 210 can be reduced.
  • FIG. 5 is a cross-sectional view of a solid-state imaging device 100C according to Modification 4 of the present embodiment.
  • solid-state imaging element 100 ⁇ / b> C has a point in which protective film 8 and interlayer insulating film 7 are not formed and a point in which groove 19 is formed, as compared with solid-state imaging element 100 in FIG. 1. Is different. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
  • the groove 19 is formed so as to penetrate from the light incident surface of the semiconductor substrate 1 to the surface opposite to the light incident surface so as to surround the opening 41 corresponding to the pad 6 of the wiring layer 13.
  • An insulating film is embedded in the groove 19.
  • the groove 19 is formed as follows, for example. First, before the photodiodes 2 and 2A are formed, an opening is formed in the semiconductor substrate 1 from the side where the wiring layer 13 is formed by a dry etching technique. Thereafter, the trench 19 is formed by depositing an insulating film in the opening by a low pressure CVD technique.
  • the separation insulating film deposited inside the opening 41 corresponding to the pad 6 of the wiring layer 13 (on the semiconductor substrate 1 side) is not necessary, and the film forming and processing steps can be reduced.
  • the present invention relates to a back-illuminated solid-state imaging device, and is useful for reducing the package size without increasing the number of terminals of the package while fixing the potential of the light shielding film.

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Abstract

A solid-state image pickup element is provided with: a semiconductor substrate (1) on which a pixel section (20) wherein a plurality of pixels are arranged is formed; a wiring layer (13), which is formed on the semiconductor substrate (1) surface on the opposite side to the light incoming surface and has wiring (3) including the driving signal line of the pixel section (20) formed thereon; and a light shielding film (5), which is formed on the light incoming surface of the semiconductor substrate (1) and shields from light, the dark pixel which determines black signals among the pixels. A pad (6), which is formed on the wiring layer (13) and is a part of the wiring (3), and the light shielding film (5), which shields a photodiode (2A) as the dark pixel from light, are electrically connected to each other by means of wiring (10).

Description

固体撮像素子Solid-state image sensor
　本発明は、固体撮像素子に関し、特に、半導体基板の配線層が形成される側とは反対側から受光する、裏面照射型の固体撮像素子に関する。 The present invention relates to a solid-state imaging device, and more particularly to a back-illuminated solid-state imaging device that receives light from a side opposite to a side on which a wiring layer of a semiconductor substrate is formed.
　図６は、従来の裏面照射型の固体撮像素子５００の断面図である。 FIG. 6 is a cross-sectional view of a conventional back-illuminated solid-state imaging device 500.
　図６に示されるように、半導体基板１０１には、画素部１２０が形成される。画素部１２０には、暗画素としてのフォトダイオード１０２Ａと、画素としての複数のフォトダイオード１０２とが配列される。暗画素は、光学的に黒信号を決めるための画素である。フォトダイオード１０２Ａ，１０２は、半導体基板１０１内に形成される。また、半導体基板１０１には、周辺回路を構成する図示しない素子が形成される。 As shown in FIG. 6, the pixel portion 120 is formed on the semiconductor substrate 101. In the pixel portion 120, a photodiode 102A as a dark pixel and a plurality of photodiodes 102 as pixels are arranged. The dark pixel is a pixel for optically determining a black signal. The photodiodes 102A and 102 are formed in the semiconductor substrate 101. In addition, on the semiconductor substrate 101, an element (not shown) that forms a peripheral circuit is formed.
　図６の固体撮像素子５００は、撮像するための光（以下、撮像光という）を、当該固体撮像素子５００の上部から受光する。半導体基板１０１において、撮像光が入射される面（以下、光入射面という）には、反射防止膜１０４と、遮光膜１０５とが形成される。 6 receives light for imaging (hereinafter referred to as imaging light) from above the solid-state imaging device 500. In the semiconductor substrate 101, an antireflection film 104 and a light shielding film 105 are formed on a surface on which imaging light is incident (hereinafter referred to as a light incident surface).
　遮光膜１０５は、暗画素としてのフォトダイオード１０２Ａに入射される光を遮光するために、フォトダイオード１０２Ａを覆うように形成される。また、遮光膜１０５は、画素としてのフォトダイオード１０２に光が入射されるように形成される。 The light shielding film 105 is formed so as to cover the photodiode 102A in order to shield light incident on the photodiode 102A as a dark pixel. The light shielding film 105 is formed so that light is incident on the photodiode 102 as a pixel.
　半導体基板１０１において、光入射面と反対側の面には、配線層１１３が形成される。配線層１１３には、複数の配線１０３が形成される。なお、配線層１１３には、外部と接続されるためのパッド１０６が露出する。 In the semiconductor substrate 101, a wiring layer 113 is formed on the surface opposite to the light incident surface. A plurality of wirings 103 are formed in the wiring layer 113. Note that a pad 106 for connection to the outside is exposed on the wiring layer 113.
　このように、裏面照射型の固体撮像素子５００では、配線層１１３による開口率の低下がないという利点がある。 As described above, the back-illuminated solid-state imaging device 500 has an advantage that the aperture ratio is not lowered by the wiring layer 113.
　ここで、前述したように、遮光膜１０５により、暗画素としてのフォトダイオード１０２Ａが遮光される。遮光膜１０５は、帯電することにより寄生容量が変化する。そこで、当該寄生容量が、フォトダイオード１０２Ａ，１０２における光電子の蓄積、光電子の読み出しおよびノイズ等に影響を与えることを防止するために、遮光膜１０５の電位は、一定電位に固定されることが好ましい。 Here, as described above, the light shielding film 105 shields the photodiode 102A as a dark pixel from light. The light shielding film 105 changes its parasitic capacitance when charged. Therefore, in order to prevent the parasitic capacitance from affecting photoelectron accumulation, photoelectron readout, noise, and the like in the photodiodes 102A and 102, it is preferable that the potential of the light shielding film 105 is fixed to a constant potential. .
　以下、図７Ａ、図７Ｂを参照しながら、特許文献１に示されている裏面照射型の固体撮像素子の遮光膜へ外部から電圧を印加する方法について説明する。 Hereinafter, a method of applying a voltage from the outside to the light-shielding film of the back-illuminated solid-state imaging device shown in Patent Document 1 will be described with reference to FIGS. 7A and 7B.
　図７Ａは、従来の裏面照射型の固体撮像素子６００の断面図である。図７Ａの固体撮像素子６００は、当該固体撮像素子６００の上部から撮像光を受光する。 FIG. 7A is a cross-sectional view of a conventional back-illuminated solid-state imaging device 600. The solid-state image sensor 600 in FIG. 7A receives imaging light from the upper part of the solid-state image sensor 600.
　図７Ａに示される固体撮像素子６００は、図６の固体撮像素子５００と比較して、撮像光を受光する側の一部が開口されている点が異なる。それ以外の構成は、固体撮像素子５００と同様なので詳細な説明は繰り返さない。 7A is different from the solid-state imaging device 500 of FIG. 6 in that a part of the solid-state imaging device 600 that receives imaging light is opened. Since the other configuration is the same as that of solid-state imaging device 500, detailed description will not be repeated.
　固体撮像素子６００において、配線層１１３に形成される配線１０３を露出させるために、半導体基板１０１の光入射面側には、開口部１４１が形成される。配線１０３のうち、開口部１４１により外部に露出した部分は、パッド１０６である。 In the solid-state imaging device 600, an opening 141 is formed on the light incident surface side of the semiconductor substrate 101 in order to expose the wiring 103 formed in the wiring layer 113. A portion of the wiring 103 exposed to the outside through the opening 141 is a pad 106.
　また、遮光膜１０５の一部を外部に露出させるために、半導体基板１０１の光入射面側には、開口部１４２が形成される。開口部１４２が形成されることにより、遮光膜１０５に対し、外部から電圧を印加できるようになっている。遮光膜１０５のうち、開口部１４２により外部に露出した部分は、パッド１０９である。 Also, an opening 142 is formed on the light incident surface side of the semiconductor substrate 101 in order to expose a part of the light shielding film 105 to the outside. By forming the opening 142, a voltage can be applied to the light shielding film 105 from the outside. A portion of the light shielding film 105 exposed to the outside through the opening 142 is a pad 109.
　図７Ｂは、裏面照射型の固体撮像素子６００をパッケージに搭載した図を示す。なお、図７Ｂは、図７Ａの固体撮像素子６００を簡略化して、半導体基板１０１を主に示す。 FIG. 7B shows a diagram in which a back-illuminated solid-state imaging device 600 is mounted on a package. 7B mainly shows the semiconductor substrate 101 by simplifying the solid-state imaging device 600 of FIG. 7A.
　半導体基板１０１の配線層が形成されている側には、支持基板１０７が貼り付けられる。半導体基板１０１は、パッケージ１１０に搭載される。 A support substrate 107 is attached to the side of the semiconductor substrate 101 where the wiring layer is formed. The semiconductor substrate 101 is mounted on the package 110.
　半導体基板１０１の配線層が形成されている側とは反対側の光入射面側には、開口部１４１，１４２が形成される。開口部１４１，１４２が形成されることにより、パッド１０６，１０９が外部に露出される。 Openings 141 and 142 are formed on the light incident surface side of the semiconductor substrate 101 opposite to the side on which the wiring layer is formed. By forming the openings 141 and 142, the pads 106 and 109 are exposed to the outside.
　そして、半導体基板１０１に形成されたパッド１０６と、パッケージ１１０の端子１１１とがワイヤ１１４により電気的に接続される。また、パッド１０９と、パッケージ１１０の端子１１２とがワイヤ１１４により電気的に接続される。 Then, the pad 106 formed on the semiconductor substrate 101 and the terminal 111 of the package 110 are electrically connected by the wire 114. Further, the pad 109 and the terminal 112 of the package 110 are electrically connected by a wire 114.
　このように、遮光膜１０５の一部であるパッド１０９と、パッケージ１１０の端子１１２とが電気的に接続される。これにより、半導体基板１０１の外部から、遮光膜１０５の電位を一定電位に固定することができる。また、配線１０３の一部であるパッド１０６へ必要な駆動電圧を供給することができる。 Thus, the pad 109 which is a part of the light shielding film 105 and the terminal 112 of the package 110 are electrically connected. Thereby, the potential of the light shielding film 105 can be fixed to a constant potential from the outside of the semiconductor substrate 101. In addition, a necessary driving voltage can be supplied to the pad 106 which is a part of the wiring 103.
特開２００６－０１９６５３号公報JP 2006-019653 A
　しかしながら、図７Ｂのようにパッケージの端子と遮光膜とを直接ワイヤで接続することにより、遮光膜の電位を固定する方法では、パッケージの端子数が増え、パッケージサイズが大きくなるという課題が発生する。 However, in the method of fixing the potential of the light shielding film by directly connecting the package terminals and the light shielding film with wires as shown in FIG. 7B, there is a problem that the number of terminals of the package increases and the package size increases. .
　本発明は、上述の問題点を解決するためになされたものであって、その目的は、パッケージの端子数を増やさず、遮光膜の電位を固定することを可能とする固体撮像素子を提供することである。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a solid-state imaging device that can fix the potential of the light shielding film without increasing the number of terminals of the package. That is.
　上述の課題を解決するために、この発明のある局面に従う固体撮像素子は、複数の画素が配列された画素部が形成された半導体基板と、半導体基板において、撮像するための光が入射される面である光入射面の反対側の面に形成され、画素部の駆動用信号線を含む配線が形成された配線層と、半導体基板の光入射面に形成され、複数の画素のうち黒信号を決めるための暗画素を遮光する遮光膜とを備える。半導体基板には、少なくとも製造過程において、配線層に形成された、固定電位を引き出すための配線の一部であるパッドを光入射面側に露出させるために光入射面側から半導体基板を貫通する開口部が形成されており、パッドと遮光膜とが配線により電気的に接続される。 In order to solve the above-described problem, a solid-state imaging device according to an aspect of the present invention has a semiconductor substrate on which a pixel portion in which a plurality of pixels are arranged and light for imaging incident on the semiconductor substrate. Formed on the surface opposite to the light incident surface, the wiring layer including the wiring including the driving signal lines of the pixel portion, and the light input surface of the semiconductor substrate. A light-shielding film that shields a dark pixel for determining the light intensity. The semiconductor substrate penetrates the semiconductor substrate from the light incident surface side in order to expose a pad, which is a part of the wiring for extracting a fixed potential, formed on the wiring layer to the light incident surface side at least in the manufacturing process. An opening is formed, and the pad and the light shielding film are electrically connected by wiring.
　すなわち、配線層に形成された、配線の一部であるパッドと、複数の画素のうち黒信号を決めるための暗画素を遮光する遮光膜とが配線により電気的に接続される。 That is, a pad formed in the wiring layer, which is a part of the wiring, and a light shielding film that shields a dark pixel for determining a black signal among the plurality of pixels are electrically connected by the wiring.
　そのため、遮光膜の電位を一定電位に固定することができる。したがって、遮光膜の帯電による寄生容量の変化を抑制でき、当該寄生容量が、画素における、光電子の蓄積、光電子の読み出しおよびノイズ等に影響を与えることを防止することができる。 Therefore, the potential of the light shielding film can be fixed at a constant potential. Accordingly, a change in parasitic capacitance due to charging of the light shielding film can be suppressed, and the parasitic capacitance can be prevented from affecting photoelectron accumulation, photoelectron readout, noise, and the like in the pixel.
　また、半導体基板において配線の一部であるパッドと遮光膜とを電気的に接続させるため、固体撮像素子を、パッケージに接続させる場合において、パッドおよび遮光膜を、それぞれ、パッケージにおける異なる２つの端子に接続させる必要はない。つまり、パッケージの端子数の増加を抑えることができる。 In addition, in order to electrically connect the light shielding film and the pad which is a part of the wiring in the semiconductor substrate, when the solid-state imaging device is connected to the package, the pad and the light shielding film are respectively connected to two different terminals in the package. There is no need to connect to. That is, an increase in the number of terminals of the package can be suppressed.
　つまり、パッケージの端子数を増やさず、遮光膜の電位を固定することができる。 That is, the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
　また、パッドと遮光膜とを電気的に接続する配線は、主にＣｕで構成されており、パッドの上部には、さらに金属が積層され、金属の最表面はアルミまたはアルミを含む合金であってもよい。 The wiring that electrically connects the pad and the light shielding film is mainly made of Cu, and a metal is further laminated on the upper part of the pad, and the outermost surface of the metal is aluminum or an alloy containing aluminum. May be.
　すなわち、固定電位を引き出すための配線の一部であるパッドと遮光膜とを電気的に接続する配線をＣｕで構成するため、パッドの開口部のような垂直な面にも配線を形成することができる。 That is, since the wiring that electrically connects the pad, which is part of the wiring for extracting the fixed potential, and the light shielding film is made of Cu, the wiring is also formed on a vertical surface such as the opening of the pad. Can do.
　また、パッドに積層された金属の最表面をアルミまたはアルミを含む合金にすることにより、プローブ検査やワイヤーボンドが容易になる。 Also, probe inspection and wire bonding are facilitated by making the outermost surface of the metal laminated on the pad aluminum or an alloy containing aluminum.
　また、半導体基板に形成された、パッドに対応する開口部は、当該開口部の幅が、光入射面側からパッドに近づくに従い狭くなるように形成されており、パッドと遮光膜とを電気的に接続する配線はアルミまたはアルミ合金であってもよい。 Further, the opening corresponding to the pad formed in the semiconductor substrate is formed so that the width of the opening becomes narrower from the light incident surface side toward the pad, and the pad and the light shielding film are electrically connected. The wiring connected to may be aluminum or an aluminum alloy.
　開口部の幅を光入射面側からパッドに近づくに従い狭くすることで、スパッタ技術を用いても、配線としてのアルミまたはアルミ合金を容易に当該開口部に堆積することができる。また、配線に、銅めっきを使う必要がなくなるので、安価に信頼性の良い配線を得ることができる。また、配線がアルミまたはアルミ合金であるため、配線のプローブ検査やワイヤーボンドが容易になる。 By narrowing the width of the opening as it approaches the pad from the light incident surface side, aluminum or an aluminum alloy as wiring can be easily deposited in the opening even if sputtering technology is used. In addition, since it is not necessary to use copper plating for the wiring, a reliable wiring can be obtained at low cost. In addition, since the wiring is made of aluminum or aluminum alloy, probe inspection and wire bonding of the wiring become easy.
　また、半導体基板に対し、配線層が形成された側には支持基板が貼り付けられ、支持基板において、光入射面の反対側には、バンプが形成され、配線層に形成された配線の一部であるパッドと、バンプとが支持基板を貫通する貫通電極により電気的に接続されてもよい。 In addition, a support substrate is attached to the semiconductor substrate on the side where the wiring layer is formed, and a bump is formed on the side of the support substrate opposite to the light incident surface, and one of the wirings formed on the wiring layer is formed. The pad which is a part and the bump may be electrically connected by a through electrode penetrating the support substrate.
　配線の一部であるパッドと、遮光膜とは配線により電気的に接続される。そのため、配線の一部であるパッドと、バンプとが電気的に接続されることにより、バンプと、遮光膜とは貫通電極により電気的に接続される。 The pad that is a part of the wiring and the light shielding film are electrically connected by the wiring. For this reason, the pads that are part of the wiring are electrically connected to the bumps, whereby the bumps and the light shielding film are electrically connected to each other through the through electrodes.
　したがって、バンプの電位を固定することにより、貫通電極を通じて、遮光膜の電位を固定することができる。 Therefore, by fixing the potential of the bump, the potential of the light shielding film can be fixed through the through electrode.
　また、パッドに対応する開口部を取り囲むように、半導体基板における光入射面から該光入射面の反対側の面まで貫通するように溝が形成され、溝には、絶縁膜が埋め込まれていてもよい。 A groove is formed so as to penetrate from the light incident surface of the semiconductor substrate to the surface opposite to the light incident surface so as to surround the opening corresponding to the pad, and an insulating film is embedded in the groove. Also good.
　これにより、パッドに対応する開口部を取り囲むように、絶縁膜が埋め込まれた溝が形成されることにより、パッドに対応する開口部分の配線と半導体基板に形成される画素とを電気的に分離することが可能になる。そのため、半導体基板に形成される画素と、パッドと遮光膜とを電気的に接続する配線とを分離するための絶縁膜が不要となり、成膜、加工の工程が削減できる。 As a result, a trench embedded with an insulating film is formed so as to surround the opening corresponding to the pad, thereby electrically separating the wiring in the opening corresponding to the pad and the pixel formed in the semiconductor substrate. It becomes possible to do. Therefore, an insulating film for separating the pixel formed on the semiconductor substrate and the wiring for electrically connecting the pad and the light-shielding film becomes unnecessary, and the film forming and processing steps can be reduced.
　本発明により、パッケージの端子数を増やさず、遮光膜の電位を固定することができる。 According to the present invention, the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
図１は、本実施形態に係る固体撮像素子の断面図である。FIG. 1 is a cross-sectional view of a solid-state imaging device according to this embodiment. 図２は、本実施形態の変形例１に係る固体撮像素子の断面図である。FIG. 2 is a cross-sectional view of a solid-state imaging device according to Modification 1 of the present embodiment. 図３は、本実施形態の変形例２に係る固体撮像素子の断面図である。FIG. 3 is a cross-sectional view of a solid-state imaging device according to the second modification of the present embodiment. 図４は、本実施形態の変形例３に係るパッケージの断面図である。FIG. 4 is a cross-sectional view of a package according to the third modification of the present embodiment. 図５は、本実施形態の変形例４に係る固体撮像素子の断面図である。FIG. 5 is a cross-sectional view of a solid-state imaging device according to Modification 4 of the present embodiment. 図６は、従来の裏面照射型の固体撮像素子の断面図である。FIG. 6 is a cross-sectional view of a conventional back-illuminated solid-state imaging device. 図７Ａは、従来の裏面照射型の固体撮像素子を示す図である。FIG. 7A is a diagram showing a conventional back-illuminated solid-state imaging device. 図７Ｂは、従来の裏面照射型の固体撮像素子を示す図である。FIG. 7B is a diagram illustrating a conventional back-illuminated solid-state imaging device.
　以下、図面を参照しつつ、本発明の実施の形態について説明する。以下の説明では、同一の部品には同一の符号を付してある。それらの名称および機能も同じである。したがって、それらについての詳細な説明は繰り返さない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.
　＜第１の実施の形態＞
　以下、本発明の第１の実施形態に係る固体撮像素子について、図面を参照しながら説明する。 <First Embodiment>
Hereinafter, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to the drawings.
　図１は、本実施形態に係る固体撮像素子１００の断面図である。固体撮像素子１００は、裏面照射型のＭＯＳ（Metal Oxide Semiconductor）センサーである。 FIG. 1 is a cross-sectional view of a solid-state imaging device 100 according to the present embodiment. The solid-state imaging device 100 is a back-illuminated MOS (Metal Oxide Semiconductor) sensor.
　図１を参照して、固体撮像素子１００は、半導体基板１を含む。半導体基板１は、ＳＯＩ（Silicon on Insulator）基板である。固体撮像素子１００は、詳細は後述するが、半導体基板１内に受光領域であるフォトダイオード２を形成し、配線３を形成したのちに、半導体基板１のＳｉ活性層４～６μｍ以外を除去して得られる。固体撮像素子１００は、配線３が形成された側とは反対側から受光することを特徴とする。 Referring to FIG. 1, the solid-state imaging device 100 includes a semiconductor substrate 1. The semiconductor substrate 1 is an SOI (Silicon-on-Insulator) substrate. As will be described in detail later, the solid-state imaging device 100 forms a photodiode 2 as a light receiving region in the semiconductor substrate 1 and forms a wiring 3, and then removes other than the Si active layers 4 to 6 μm of the semiconductor substrate 1. Obtained. The solid-state image sensor 100 receives light from the side opposite to the side on which the wiring 3 is formed.
　半導体基板１には、画素部２０が形成される。画素部２０には、暗画素としてのフォトダイオード２Ａと、画素としての複数のフォトダイオード２とが配列される。すなわち、画素部２０には、複数の画素が配列される。 The pixel portion 20 is formed on the semiconductor substrate 1. In the pixel unit 20, a photodiode 2A as a dark pixel and a plurality of photodiodes 2 as pixels are arranged. That is, a plurality of pixels are arranged in the pixel unit 20.
　暗画素は、光学的に黒信号を決めるための画素である。暗画素は、画素部２０に配列される複数の画素の一部の画素である。フォトダイオード２Ａ，２は、半導体基板１内に形成される。 Dark pixels are pixels for optically determining a black signal. The dark pixel is a part of a plurality of pixels arranged in the pixel unit 20. The photodiodes 2A and 2 are formed in the semiconductor substrate 1.
　図１の固体撮像素子１００は、撮像するための光（以下、撮像光という）を、当該固体撮像素子１００の上部から受光する。半導体基板１において、撮像光が入射される面（以下、光入射面という）には、反射防止膜４と、遮光膜５とが形成される。 1 receives light for imaging (hereinafter referred to as imaging light) from above the solid-state imaging device 100. In the semiconductor substrate 1, an antireflection film 4 and a light shielding film 5 are formed on a surface on which imaging light is incident (hereinafter referred to as a light incident surface).
　反射防止膜４は、プラズマＣＶＤ技術を用いて、半導体基板１の光入射面上に堆積されるＳｉＮである。反射防止膜４の厚みは、例えば、２００ｎｍである。 The antireflection film 4 is SiN deposited on the light incident surface of the semiconductor substrate 1 using a plasma CVD technique. The thickness of the antireflection film 4 is, for example, 200 nm.
　遮光膜５は、暗画素としてのフォトダイオード２Ａに入射される光を遮光するために、フォトダイオード２Ａを覆うように形成される。すなわち、遮光膜５は、暗画素としてのフォトダイオード２Ａを遮光する。また、遮光膜５は、画素としてのフォトダイオード２に光が入射されるように形成される。 The light shielding film 5 is formed so as to cover the photodiode 2A in order to shield light incident on the photodiode 2A as a dark pixel. That is, the light shielding film 5 shields the photodiode 2A as a dark pixel. The light shielding film 5 is formed so that light is incident on the photodiode 2 as a pixel.
　遮光膜５は、画素としてのフォトダイオード２の境界を覆うように、反射防止膜４上にパターニングされるアルミである。遮光膜５の厚みは、例えば、２００ｎｍである。遮光膜５であるアルミのパターンの幅は、０．２μｍ以下と非常に微細である。そのため、遮光膜５としてのアルミは薄膜である必要がある。 The light shielding film 5 is aluminum patterned on the antireflection film 4 so as to cover the boundary of the photodiode 2 as a pixel. The thickness of the light shielding film 5 is, for example, 200 nm. The width of the aluminum pattern which is the light shielding film 5 is very fine, 0.2 μm or less. Therefore, the aluminum as the light shielding film 5 needs to be a thin film.
　半導体基板１において、光入射面と反対側の面には、配線層１３が形成される。配線層１３には、複数の配線３が形成される。複数の配線３の各々は、銅（Ｃｕ）で形成される。 In the semiconductor substrate 1, a wiring layer 13 is formed on the surface opposite to the light incident surface. A plurality of wirings 3 are formed in the wiring layer 13. Each of the plurality of wirings 3 is formed of copper (Cu).
　複数の配線３の一部は、駆動用信号線を含む。駆動用信号線は、画素部２０に含まれる、暗画素としてのフォトダイオード２Ａと、画素としての複数のフォトダイオード２とを駆動させるための信号線である。すなわち、駆動用信号線は、画素部２０を駆動させるための信号線である。また、配線層１３の一部には、層間絶縁膜７が形成される。 Some of the plurality of wirings 3 include drive signal lines. The driving signal line is a signal line for driving the photodiode 2 </ b> A as a dark pixel and the plurality of photodiodes 2 as pixels included in the pixel unit 20. That is, the driving signal line is a signal line for driving the pixel unit 20. An interlayer insulating film 7 is formed on part of the wiring layer 13.
　固体撮像素子１００において、配線層１３に形成される、画素部２０の駆動用信号線を含む配線３を露出させるために、半導体基板１および層間絶縁膜７の光入射面側には、ドライエッチ技術により、開口部が形成される。当該開口部が形成された時点において、配線３のうち、当該開口部により外部に露出した部分は、パッド６である。当該開口部は、配線層１３に形成された、固定電位を引き出すための配線３の一部であるパッド６を露出させるために、光入射面側から半導体基板１を貫通するように形成される。 In the solid-state imaging device 100, in order to expose the wiring 3 including the driving signal line of the pixel unit 20 formed in the wiring layer 13, the light incident surface side of the semiconductor substrate 1 and the interlayer insulating film 7 is dry-etched. The technique forms the opening. A portion of the wiring 3 exposed to the outside through the opening at the time when the opening is formed is the pad 6. The opening is formed so as to penetrate the semiconductor substrate 1 from the light incident surface side in order to expose the pad 6 which is formed in the wiring layer 13 and is a part of the wiring 3 for extracting a fixed potential. .
　パッド６を露出させる開口部が設けられた後、プラズマＣＶＤ技術を用いて、反射防止膜４、層間絶縁膜７、パッド６および遮光膜５の各々の上部が露出している部分に、保護膜８が堆積される。保護膜８はＳｉＮである。 After the opening for exposing the pad 6 is provided, a protective film is formed on the exposed portions of the antireflection film 4, the interlayer insulating film 7, the pad 6, and the light shielding film 5 using the plasma CVD technique. 8 is deposited. The protective film 8 is SiN.
　保護膜８が堆積された後、画素部２０の駆動用信号線を含む配線３を露出させるために、ドライエッチ技術により、開口部４１が形成される。開口部４１が形成された時点において、配線３のうち、当該開口部４１により外部に露出した部分は、パッド６である。当該開口部４１は、配線層１３に形成された、固定電位を引き出すための配線３の一部であるパッド６を光入射面側に露出させるために、光入射面側から半導体基板１を貫通するように形成される。パッド６は、少なくとも固体撮像素子１００の製造過程において外部（光入射面側）に露出される。 After the protective film 8 is deposited, an opening 41 is formed by a dry etching technique in order to expose the wiring 3 including the driving signal line of the pixel unit 20. At the time when the opening 41 is formed, a portion of the wiring 3 exposed to the outside by the opening 41 is the pad 6. The opening 41 penetrates the semiconductor substrate 1 from the light incident surface side in order to expose the pad 6 formed in the wiring layer 13 as a part of the wiring 3 for extracting a fixed potential to the light incident surface side. To be formed. The pad 6 is exposed to the outside (light incident surface side) at least during the manufacturing process of the solid-state imaging device 100.
　また、保護膜８が堆積された後、遮光膜５の一部を外部に露出させるために、半導体基板１の光入射面側には、ドライエッチ技術により、開口部４２が形成される。開口部４２が形成された時点において、遮光膜５のうち、開口部４２により外部に露出した部分は、パッド９である。 Further, after the protective film 8 is deposited, an opening 42 is formed on the light incident surface side of the semiconductor substrate 1 by a dry etching technique in order to expose a part of the light shielding film 5 to the outside. The portion of the light shielding film 5 exposed to the outside by the opening 42 at the time when the opening 42 is formed is the pad 9.
　開口部４１および開口部４２が形成された後、一般的な工法により、配線１０が形成される。配線１０は、シード層および銅（Ｃｕ）めっきで構成される。なお、配線１０は、主に銅（Ｃｕ）で構成される。 After the opening 41 and the opening 42 are formed, the wiring 10 is formed by a general construction method. The wiring 10 includes a seed layer and copper (Cu) plating. The wiring 10 is mainly composed of copper (Cu).
　配線１０は、配線３の一部であるパッド６と、遮光膜５の一部であるパッド９とを電気的に接続させるように形成される。すなわち、パッド６と、パッド９とは、配線１０により電気的に接続される。 The wiring 10 is formed so as to electrically connect the pad 6 which is a part of the wiring 3 and the pad 9 which is a part of the light shielding film 5. That is, the pad 6 and the pad 9 are electrically connected by the wiring 10.
　配線１０が形成された後、パッド６以外の部分が有機パッシベーション膜３１で覆われるように、有機パッシベーション膜３１が形成される。 After the wiring 10 is formed, the organic passivation film 31 is formed so that portions other than the pad 6 are covered with the organic passivation film 31.
　以上により、図１に示す固体撮像素子１００が形成される。 Thus, the solid-state imaging device 100 shown in FIG. 1 is formed.
　従来の裏面照射型の固体撮像素子（例えば、固体撮像素子６００）では、固体撮像素子１００のように配線１０が形成されていないため、画素部２０の駆動用信号線を含む配線３の一部であるパッド６および遮光膜５の一部であるパッド９を、それぞれパッケージの２つの端子に接続する必要があった。そのため、パッケージの端子数が増え、パッケージサイズが大きくなるという問題があった。 In a conventional back-illuminated solid-state imaging device (for example, solid-state imaging device 600), the wiring 10 is not formed unlike the solid-state imaging device 100, and therefore a part of the wiring 3 including the driving signal line of the pixel unit 20 The pad 6 and the pad 9 which is a part of the light shielding film 5 need to be connected to the two terminals of the package, respectively. For this reason, there are problems that the number of terminals of the package increases and the package size increases.
　しかしながら、本実施形態における固体撮像素子１００では、半導体基板１における光入射面側で、遮光膜５と配線層に形成される配線３の一部であるパッド６とを電気的に接続する。これにより、遮光膜の電位を一定電位に固定することができる。 However, in the solid-state imaging device 100 according to the present embodiment, the light shielding film 5 and the pad 6 that is a part of the wiring 3 formed in the wiring layer are electrically connected on the light incident surface side of the semiconductor substrate 1. Thereby, the potential of the light shielding film can be fixed to a constant potential.
　また、半導体基板１において配線３の一部であるパッド６と遮光膜５の一部であるパッド９とを電気的に接続させるため、固体撮像素子１００を、パッケージに接続させる場合において、パッド６およびパッド９を、それぞれ、パッケージにおける異なる２つの端子に接続させる必要はない。そのため、パッケージの端子数の増加を抑えることができる。すなわち、パッケージから取り出す端子数の増加を抑えることができる。 Further, in order to electrically connect the pad 6 which is a part of the wiring 3 and the pad 9 which is a part of the light shielding film 5 in the semiconductor substrate 1, when the solid-state imaging device 100 is connected to the package, the pad 6 And pad 9 need not each be connected to two different terminals in the package. Therefore, an increase in the number of terminals of the package can be suppressed. That is, an increase in the number of terminals taken out from the package can be suppressed.
　つまり、パッケージの端子数を増やさず、遮光膜の電位を固定することができる。 That is, the potential of the light shielding film can be fixed without increasing the number of terminals of the package.
　＜第１の実施の形態の変形例１＞
　図２は、本実施形態の変形例１に係る固体撮像素子１００Ａの断面図である。 <Variation 1 of the first embodiment>
FIG. 2 is a cross-sectional view of a solid-state imaging device 100A according to Modification 1 of the present embodiment.
　図２を参照して、固体撮像素子１００Ａは、図１の固体撮像素子１００と比較して、配線１０のうち、パッド６の上部に対応する部分に、金属１１が堆積（積層）されている点が異なる。それ以外の構成は、固体撮像素子１００と同様なので詳細な説明は繰り返さない。 Referring to FIG. 2, in solid-state imaging device 100A, metal 11 is deposited (laminated) in a portion corresponding to the upper portion of pad 6 in wiring 10 as compared with solid-state imaging device 100 in FIG. The point is different. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
　金属１１は、アルミと銅（Ｃｕ）との合金である。金属１１の最表面は、アルミまたはアルミを含む合金（以下、アルミ合金ともいう）である。 Metal 11 is an alloy of aluminum and copper (Cu). The outermost surface of the metal 11 is aluminum or an alloy containing aluminum (hereinafter also referred to as an aluminum alloy).
　以下に、金属１１を形成するための工程を説明する。 Hereinafter, a process for forming the metal 11 will be described.
　まず、第１の実施の形態と同様に、配線１０が形成される。その後、スパッタ技術により、配線１０のうち、パッド６の上部に対応する部分に、金属１１が堆積される。金属１１は、フォトリソグラフィーとウェットエッチ技術によってパターニングされている。 First, as in the first embodiment, the wiring 10 is formed. Thereafter, a metal 11 is deposited on a portion of the wiring 10 corresponding to the upper portion of the pad 6 by a sputtering technique. The metal 11 is patterned by photolithography and wet etching techniques.
　本実施形態の変形例１においては、金属１１の最表面が、アルミまたはアルミを含む合金であることにより、プローブ検査やワイヤーボンドが容易に実施できる。 In the first modification of the present embodiment, since the outermost surface of the metal 11 is aluminum or an alloy containing aluminum, probe inspection and wire bonding can be easily performed.
　＜第１の実施の形態の変形例２＞
　図３は、本実施形態の変形例２に係る固体撮像素子１００Ｂの断面図である。 <Modification 2 of the first embodiment>
FIG. 3 is a cross-sectional view of a solid-state imaging device 100B according to Modification 2 of the present embodiment.
　図３を参照して、固体撮像素子１００Ｂは、図１の固体撮像素子１００と比較して、開口部４１の代わりに開口部４１Ｂが形成される点と、開口部４２の代わりに開口部４２Ｂが形成される点とが異なる。それ以外の構成は、固体撮像素子１００と同様なので詳細な説明は繰り返さない。 Referring to FIG. 3, solid-state imaging device 100 </ b> B is different from solid-state imaging device 100 of FIG. 1 in that opening 41 </ b> B is formed instead of opening 41, and opening 42 </ b> B is used instead of opening 42. Is different from the point that is formed. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
　開口部４１Ｂは、配線３の一部であるパッド６に対応する開口部である。  The opening 41 </ b> B is an opening corresponding to the pad 6 that is a part of the wiring 3.
　開口部４１Ｂは、当該開口部の幅が、光が入射する側（光入射面側）からパッド６に近づくに従い狭くなるように形成される。 The opening 41 </ b> B is formed such that the width of the opening becomes narrower as it approaches the pad 6 from the light incident side (light incident surface side).
　以下に、開口部４１Ｂを形成するための工程を説明する。 Hereinafter, a process for forming the opening 41B will be described.
　まず、半導体基板１に開口部が設けられていない状態において、半導体基板１のうち、パッド６の上部に対応する部分を、ＴＭＡＨを用いたウェットエッチ技術により、開口部の幅が、光入射面側からパッド６に近づくに従い狭くなるように開口させる。これにより、開口部４１Ｂの側壁は図３のように傾斜する。 First, in a state in which no opening is provided in the semiconductor substrate 1, a portion of the semiconductor substrate 1 corresponding to the upper portion of the pad 6 is subjected to a wet etching technique using TMAH so that the width of the opening is reduced to the light incident surface. It opens so that it may become narrow as it approaches the pad 6 from the side. Thereby, the side wall of the opening 41B is inclined as shown in FIG.
　その後、第１の実施の形態と同様な工程により、反射防止膜４、層間絶縁膜７、パッド６および遮光膜５の各々の上部が露出している部分に、保護膜８が堆積される。 Thereafter, the protective film 8 is deposited on the exposed portions of the antireflection film 4, the interlayer insulating film 7, the pad 6, and the light shielding film 5 by the same process as in the first embodiment.
　保護膜８が堆積された後、パッド６の上部に形成される層間絶縁膜７および保護膜８を、希ＨＦ（Diluted Hydrofluoric Acid）を用いて開口させる。 After the protective film 8 is deposited, the interlayer insulating film 7 and the protective film 8 formed on the top of the pad 6 are opened using dilute HF (Diluted Hydrofluoric Acid).
　また、保護膜８が堆積された後、遮光膜５の一部であるパッド９の上部に形成される保護膜８を、希ＨＦを用いて、開口させる。これにより、開口部４２Ｂが形成される。開口部４２Ｂは、遮光膜５の一部であるパッド９に対応する開口部である。 Further, after the protective film 8 is deposited, the protective film 8 formed on the pad 9 which is a part of the light shielding film 5 is opened using dilute HF. Thereby, the opening 42B is formed. The opening 42 </ b> B is an opening corresponding to the pad 9 that is a part of the light shielding film 5.
　開口部４１Ｂおよび開口部４２Ｂが形成された後、スパッタ技術により、配線１０Ｂが形成される。配線１０Ｂはアルミまたはアルミ合金である。 After the opening 41B and the opening 42B are formed, the wiring 10B is formed by a sputtering technique. The wiring 10B is made of aluminum or aluminum alloy.
　配線１０Ｂは、配線３の一部であるパッド６と、遮光膜５の一部であるパッド９とを電気的に接続させるように形成される。すなわち、パッド６と、パッド９とは、配線１０Ｂにより電気的に接続される。 The wiring 10 </ b> B is formed so as to electrically connect the pad 6 that is a part of the wiring 3 and the pad 9 that is a part of the light shielding film 5. That is, the pad 6 and the pad 9 are electrically connected by the wiring 10B.
　信頼性に強いアルミ合金はスパッタ技術を用いて成膜する必要がある。スパッタ技術では、垂直な面への堆積速度が低く制御が難しい。そのため、ウェットエッチ技術を用いてパッド６に対応する開口部４１Ｂの側壁を傾斜させることで、スパッタ技術でも配線が可能になる。 ¡Reliable aluminum alloy must be deposited using sputtering technology. Sputtering technology is difficult to control because the deposition rate on the vertical surface is low. Therefore, by using the wet etching technique to incline the side wall of the opening 41B corresponding to the pad 6, wiring is possible even by the sputtering technique.
　また、アルミ合金１層で、パッド６とパッド９とを接続する配線と、プローブ検査やワイヤーボンドが可能な電極を形成することが可能になる。 Also, it is possible to form wiring that connects the pad 6 and the pad 9 and an electrode that can be probe-inspected and wire-bonded with one layer of aluminum alloy.
　以上により、配線１０Ｂに、銅めっきを使う必要がなくなるので、安価に信頼性の良い配線を得ることができる。また、配線がアルミまたはアルミ合金であるため、配線のプローブ検査やワイヤーボンドが容易になる。 As described above, since it is not necessary to use copper plating for the wiring 10B, a highly reliable wiring can be obtained at low cost. In addition, since the wiring is made of aluminum or aluminum alloy, probe inspection and wire bonding of the wiring become easy.
　＜第１の実施の形態の変形例３＞
　図４は、本実施形態の変形例３に係るパッケージ２１０の断面図である。パッケージ２１０は、チップサイズのパッケージである。 <Modification 3 of the first embodiment>
FIG. 4 is a cross-sectional view of a package 210 according to the third modification of the present embodiment. The package 210 is a chip size package.
　図４のパッケージ２１０は、一例として、図３の固体撮像素子１００Ｂを含む。なお、パッケージ２１０は、固体撮像素子１００Ｂの代わりに、固体撮像素子１００または固体撮像素子１００Ａを含んでもよい。 4 includes the solid-state imaging device 100B of FIG. 3 as an example. The package 210 may include the solid-state image sensor 100 or the solid-state image sensor 100A instead of the solid-state image sensor 100B.
　配線３の一部であるパッド６と、遮光膜５の一部であるパッド９とを電気的に接続させる配線１０Ｂが形成された後、有機パッシベーション膜３１のうち、画素部２０の上部に対応する部分には、オンチップフィルター１２およびマイクロレンズ２３が形成される。 After the wiring 10B for electrically connecting the pad 6 which is a part of the wiring 3 and the pad 9 which is a part of the light-shielding film 5 is formed, the organic passivation film 31 corresponds to the upper part of the pixel portion 20. The on-chip filter 12 and the microlens 23 are formed in the portion to be performed.
　また、有機パッシベーション膜３１には、接着剤１４を介してガラス１５が貼り付けられる。接着剤１４は、熱過疎性のエポキシ系の接着剤である。 Further, the glass 15 is attached to the organic passivation film 31 through the adhesive 14. The adhesive 14 is a heat-sparing epoxy adhesive.
　また、受光側とは反対側の配線層１３が形成された側には支持基板１６が貼り付けられる。すなわち、半導体基板１に対し、配線層１３が形成された側には支持基板１６が貼り付けられる。支持基板１６はＳｉ基板である。支持基板１６の厚さは、例えば、１５０μｍである。 Further, a support substrate 16 is attached to the side where the wiring layer 13 opposite to the light receiving side is formed. That is, the support substrate 16 is attached to the semiconductor substrate 1 on the side where the wiring layer 13 is formed. The support substrate 16 is a Si substrate. The thickness of the support substrate 16 is, for example, 150 μm.
　支持基板１６には、当該支持基板１６を貫通する電極である貫通電極１８が形成される。貫通電極１８は銅（Ｃｕ）めっきで形成される。支持基板１６において、半導体基板１の光入射面と反対側には、バンプ１７が形成される。バンプ１７はハンダにより構成される。貫通電極１８は、支持基板１６の下部まで引き出される。 In the support substrate 16, a through electrode 18 that is an electrode penetrating the support substrate 16 is formed. The through electrode 18 is formed by copper (Cu) plating. On the support substrate 16, bumps 17 are formed on the side opposite to the light incident surface of the semiconductor substrate 1. The bumps 17 are made of solder. The through electrode 18 is pulled out to the lower part of the support substrate 16.
　図４において、貫通電極１８に接する配線３は、パッド６と電気的に接続される。貫通電極１８は、パッド６と電気的に接続される配線３と、バンプ１７とを電気的に接続する。すなわち、貫通電極１８は、パッド６とバンプ１７とを電気的に接続する。 In FIG. 4, the wiring 3 in contact with the through electrode 18 is electrically connected to the pad 6. The through electrode 18 electrically connects the wiring 3 electrically connected to the pad 6 and the bump 17. That is, the through electrode 18 electrically connects the pad 6 and the bump 17.
　なお、パッド６は、配線１０Ｂにより、遮光膜５の一部であるパッド９と電気的に接続される。そのため、パッド６とバンプ１７とが電気的に接続されることにより、バンプ１７と、遮光膜５の一部であるパッド９と電気的に接続される。 Note that the pad 6 is electrically connected to the pad 9 which is a part of the light shielding film 5 by the wiring 10B. Therefore, the pads 6 and the bumps 17 are electrically connected to each other, whereby the bumps 17 and the pads 9 that are part of the light shielding film 5 are electrically connected.
　したがって、バンプ１７の電位を固定することにより、貫通電極１８を通じて、遮光膜５の電位を固定することができる。 Therefore, the potential of the light shielding film 5 can be fixed through the through electrode 18 by fixing the potential of the bump 17.
　また、支持基板１６の下部まで引き出された貫通電極１８にバンプ１７を形成することで、パッケージ２１０をチップサイズにすることが可能になる。すなわち、パッケージ２１０のサイズを小さくすることができる。 Further, by forming the bumps 17 on the through electrodes 18 drawn to the lower part of the support substrate 16, the package 210 can be made into a chip size. That is, the size of the package 210 can be reduced.
　＜第１の実施の形態の変形例４＞
　図５は、本実施形態の変形例４に係る固体撮像素子１００Ｃの断面図である。 <Modification 4 of the first embodiment>
FIG. 5 is a cross-sectional view of a solid-state imaging device 100C according to Modification 4 of the present embodiment.
　図５を参照して、固体撮像素子１００Ｃは、図１の固体撮像素子１００と比較して、保護膜８および層間絶縁膜７が形成されてない点と、溝１９が形成されている点とが異なる。それ以外の構成は、固体撮像素子１００と同様なので詳細な説明は繰り返さない。 Referring to FIG. 5, solid-state imaging element 100 </ b> C has a point in which protective film 8 and interlayer insulating film 7 are not formed and a point in which groove 19 is formed, as compared with solid-state imaging element 100 in FIG. 1. Is different. Since the other configuration is the same as that of the solid-state imaging device 100, detailed description will not be repeated.
　以下に、溝１９について説明する。溝１９は、配線層１３のパッド６に対応する開口部４１を取り囲むように、半導体基板１における光入射面から当該光入射面の反対側の面まで貫通するように形成される。溝１９には、絶縁膜が埋め込まれている。 Hereinafter, the groove 19 will be described. The groove 19 is formed so as to penetrate from the light incident surface of the semiconductor substrate 1 to the surface opposite to the light incident surface so as to surround the opening 41 corresponding to the pad 6 of the wiring layer 13. An insulating film is embedded in the groove 19.
　溝１９は、例えば、以下のようにして形成される。まず、フォトダイオード２，２Ａが形成される前に、半導体基板１において、配線層１３が形成される側からドライエッチ技術によって開口部が形成される。その後、減圧ＣＶＤ技術により、当該開口部に、絶縁膜を堆積することにより溝１９が形成される。 The groove 19 is formed as follows, for example. First, before the photodiodes 2 and 2A are formed, an opening is formed in the semiconductor substrate 1 from the side where the wiring layer 13 is formed by a dry etching technique. Thereafter, the trench 19 is formed by depositing an insulating film in the opening by a low pressure CVD technique.
　以上のように、配線層１３のパッド６に対応する開口部４１を取り囲むように、絶縁膜が埋め込まれた溝１９が形成されことにより、パッド６に対応する開口部４１の配線１０と半導体基板１に形成される画素および暗画素（フォトダイオード２，２Ａ）とを電気的に分離することが可能になる。 As described above, the trench 19 in which the insulating film is embedded is formed so as to surround the opening 41 corresponding to the pad 6 of the wiring layer 13, and thereby the wiring 10 of the opening 41 corresponding to the pad 6 and the semiconductor substrate. 1 and the dark pixels ( photodiodes 2, 2A) can be electrically separated.
　そのため、配線層１３のパッド６に対応する開口部４１の内側（半導体基板１側）に堆積されていた分離のための絶縁膜が不要となり、成膜、加工の工程が削減できる。 Therefore, the separation insulating film deposited inside the opening 41 corresponding to the pad 6 of the wiring layer 13 (on the semiconductor substrate 1 side) is not necessary, and the film forming and processing steps can be reduced.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　本発明は、裏面照射型の固体撮像素子に関するものであり、遮光膜の電位を固定しながら、パッケージの端子数を増やさず、パッケージサイズを小型化するのに有用である。 The present invention relates to a back-illuminated solid-state imaging device, and is useful for reducing the package size without increasing the number of terminals of the package while fixing the potential of the light shielding film.
１，１０１　半導体基板
２，２Ａ，１０２，１０２Ａ　フォトダイオード
３，１０３　配線
４，１０４　反射防止膜
５，１０５　遮光膜
６，９，１０６，１０９　パッド
７　層間絶縁膜
８　保護膜
１０, １０Ｂ　配線
１１　金属
１２　オンチップフィルター
１３，１１３　配線層
１４　接着剤
１５　ガラス
１６，１０７　支持基板
１７　バンプ
１８　貫通電極
１９　溝
２０　画素部
２３　マイクロレンズ
１００，１００Ａ，１００Ｂ，１００Ｃ　固体撮像素子
１１０，２１０　パッケージ
１１１，１１２　端子
１１４　ワイヤ  DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2, 2A, 102, 102A Photodiode 3,103 Wiring 4,104 Antireflection film 5,105 Light shielding film 6,9,106,109 Pad 7 Interlayer insulating film 8 Protective film 10, 10B Wiring 11 Metal 12 On- chip filters 13 and 113 Wiring layer 14 Adhesive 15 Glass 16 and 107 Support substrate 17 Bump 18 Through electrode 19 Groove 20 Pixel part 23 Microlens 100, 100A, 100B, 100C Solid- state imaging device 110, 210 Package 111, 112 Terminal 114 wire

Claims (5)

  1. 　複数の画素が配列された画素部が形成された半導体基板と、
    　前記半導体基板において、撮像するための光が入射される面である光入射面の反対側の面に形成され、前記画素部の駆動用信号線を含む配線が形成された配線層と、
    　前記半導体基板の前記光入射面に形成され、前記複数の画素のうち黒信号を決めるための暗画素を遮光する遮光膜とを備え、
    　前記半導体基板には、少なくとも製造過程において、前記配線層に形成された、固定電位を引き出すための配線の一部であるパッドを前記光入射面側に露出させるために前記光入射面側から前記半導体基板を貫通する開口部が形成されており、
    　前記パッドと前記遮光膜とが配線により電気的に接続される、
    　固体撮像素子。     A semiconductor substrate on which a pixel portion in which a plurality of pixels are arranged is formed;
    In the semiconductor substrate, a wiring layer formed on a surface opposite to a light incident surface that is a surface on which light for imaging is incident, and a wiring layer including a signal line for driving the pixel unit is formed;
    A light shielding film that is formed on the light incident surface of the semiconductor substrate and shields a dark pixel for determining a black signal among the plurality of pixels;
    In the semiconductor substrate, at least in the manufacturing process, the pad, which is a part of the wiring for drawing out a fixed potential, formed on the wiring layer is exposed from the light incident surface side in order to expose the pad to the light incident surface side. An opening penetrating the semiconductor substrate is formed,
    The pad and the light shielding film are electrically connected by wiring;
    Solid-state image sensor.
  2. 　前記パッドと前記遮光膜とを電気的に接続する前記配線は、主にＣｕで構成されており、
    　前記パッドの上部には、さらに金属が積層され、
    　前記金属の最表面はアルミまたはアルミを含む合金である、
    　請求項１に記載の固体撮像素子。     The wiring for electrically connecting the pad and the light shielding film is mainly composed of Cu,
    A metal is further laminated on the top of the pad,
    The outermost surface of the metal is aluminum or an alloy containing aluminum,
    The solid-state imaging device according to claim 1.
  3. 　前記半導体基板に形成された、前記パッドに対応する開口部は、当該開口部の幅が、前記光入射面側から前記パッドに近づくに従い狭くなるように形成されており、
    　前記パッドと前記遮光膜とを電気的に接続する前記配線はアルミまたはアルミ合金である、
    　請求項１に記載の固体撮像素子。     The opening corresponding to the pad formed in the semiconductor substrate is formed so that the width of the opening becomes narrower as it approaches the pad from the light incident surface side,
    The wiring for electrically connecting the pad and the light shielding film is aluminum or aluminum alloy.
    The solid-state imaging device according to claim 1.
  4. 　前記半導体基板に対し、前記配線層が形成された側には支持基板が貼り付けられ、
    　前記支持基板において、前記光入射面の反対側には、バンプが形成され、
    　前記配線層に形成された配線の一部である前記パッドと、前記バンプとが前記支持基板を貫通する貫通電極により電気的に接続される、
    　請求項１に記載の固体撮像素子。     A support substrate is attached to the semiconductor substrate on the side where the wiring layer is formed,
    In the support substrate, a bump is formed on the opposite side of the light incident surface,
    The pads, which are part of the wiring formed in the wiring layer, and the bumps are electrically connected by a through electrode penetrating the support substrate;
    The solid-state imaging device according to claim 1.
  5. 　前記パッドに対応する開口部を取り囲むように、前記半導体基板における前記光入射面から該光入射面の反対側の面まで貫通するように溝が形成され、
    　前記溝には、絶縁膜が埋め込まれている、
    　請求項１に記載の固体撮像素子。      A groove is formed so as to penetrate from the light incident surface of the semiconductor substrate to a surface opposite to the light incident surface so as to surround the opening corresponding to the pad,
    An insulating film is embedded in the groove,
    The solid-state imaging device according to claim 1.
PCT/JP2010/003214 2009-05-13 2010-05-12 Solid-state image pickup element WO2010131462A1 (en)

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