JP2021530856A - 発光装置及びその製造方法 - Google Patents
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
Abstract
Description
図11は、本開示の例示的な実施形態による発光装置を示す概略断面図である。
Claims (30)
- 基板と、
前記基板から突出する複数の突出部のパターンと、
前記基板上に設けられた第1半導体層と、
前記第1半導体層上に設けられた活性層と、
前記活性層上に設けられた第2半導体層と、
を含み、
前記突出部の各々は、前記基板と一体かつ分離不能に形成され、かつ、前記基板の上面から突出する第1層と、前記第1層上に設けられ、前記第1層とは異なる材料で形成された第2層と、を含み、
隣り合う2つの突出部の中心間の間隔をピッチと呼ぶとき、前記突出部の直径と前記突出部のパターンの前記ピッチとの比は、約0.8〜約1.0である、発光装置。 - 前記突出部の各々の直径は、約2.5マイクロメートル〜約3.5マイクロメートルであり、
前記ピッチは、約2.5マイクロメートル以上約3.5マイクロメートル以下である、請求項1に記載の発光装置。 - 前記突出部の各々の直径は、約2.6マイクロメートル〜約2.8マイクロメートルであり、
前記ピッチは、約2.9マイクロメートル〜約3.1マイクロメートルである、請求項2に記載の発光装置。 - 前記突出部の各々の直径は、約2.8マイクロメートルである、請求項3に記載の発光装置。
- 前記第1層の高さと前記第2層の高さとの比が、約0.2〜約1.5である、請求項1に記載の発光装置。
- 前記第1層の高さと前記第2層の高さとの比が、約0.75〜約1.5である、請求項5に記載の発光装置。
- 前記第2層の高さは、前記第1層の高さよりも大きい、請求項6に記載の発光装置。
- 前記突出部の直径は、前記ピッチ以下である、請求項1に記載の発光装置。
- 前記第1層の側面の傾斜角度と前記第2層の側面の傾斜角度とが異なる、請求項1に記載の発光装置。
- 前記第1半導体層は、前記突出部の側面に対応する領域の一部に空隙を有する、請求項1に記載の発光装置。
- 基板と、
前記基板と一体かつ分離不能に形成され、前記基板の上面から突出する第1層と、前記第1層上に設けられ、前記第1層とは異なる材料で形成される第2層と、を含む複数の突出部のパターンと、
前記基板上に設けられ、発光する発光スタックと、
を含み、
前記発光スタックは、前記突出部の前記第1層の少なくとも1つの側面上に設けられた空隙を有し、
前記第1層の高さと前記第2層の高さとの比は2.5より大きく、9.5より小さい、発光装置。 - 前記発光スタックが、基板上に設けられた第1半導体層と、前記第1半導体層上に設けられた活性層と、前記活性層上に設けられた第2半導体層と、を含み、
前記空隙は、前記第1半導体層内に設けられている、請求項11に記載の発光装置。 - 前記基板からの前記空隙の最上部の高さと、前記基板表面からの前記第1層の最上部の高さとは、実質的に同じである、請求項12に記載の発光装置。
- 前記空隙は、前記第1層の上面が平面視で円形状である場合、前記円に内接する正六角形の頂点に対応して設けられる、請求項13に記載の発光装置。
- 前記基板の上面に垂直で円の中心を通る平面に沿って切断した場合、空隙は、直角三角形であり、
前記直角三角形の斜辺は、第1層の側面である、請求項14に記載の発光装置。 - 前記第1層の高さと前記第2層の高さとの比が、2.5より大きく、9.5より小さい、請求項11に記載の発光装置。
- 前記第1層の高さは、約0.25以上約0.55以下であり、前記第1層と前記第2層の高さの合計は、約2.1マイクロメートルである、請求項16に記載の発光装置。
- 請求項11〜17のいずれかに記載の発光装置の製造方法であって、
複数の突出部のパターンを基板上に形成する工程であって、前記突出部の各々が、基板の上面から突出する第1層と、前記第1層上に設けられ、前記第1層とは異なる材料で形成される第2層とを含む工程と、を含む工程と、
前記基板上に、第1半導体層、活性層、及び第2半導体層を順次形成する工程と、
含み、
前記第1半導体層を形成する工程は、前記基板上に前記第1半導体層の材料を三次元(3D)成長させる工程と、前記基板上に前記第1半導体層の材料を二次元(2D)成長させる工程と、を含む、発光装置の製造方法。 - 基板と、
前記基板と一体かつ分離不能に形成され、かつ、前記基板の表面から突出する第1層と、前記第1層上に設けられ、前記第1層とは異なる材料で形成される第2層と、を含む複数の突出部のパターンと、
前記基板上に設けられ、発光する発光スタックと、
を含み、
前記第1層は、上面と、前記基板の表面と前記第1層の上面とを接続する側面と、を含み、
前記第1層の上面は、粗面を有する、発光装置。 - 前記第1層の前記上面の粗さにおいて、前記粗さの標準偏差Rqは、約0.300nm〜約0.550nmであり、
前記粗さの算術平均Raは、約0.250nm〜約0.400nmである、請求項19に記載の発光装置。 - 発光スタックは、基板上に設けられ、前記突出部を覆う第1半導体層と、前記第1半導体層上に設けられた活性層と、前記活性層上に設けられた第2半導体層と、を有し、
前記活性層から出射された光は、前記第1半導体層を通過して前記基板の方向に進行する、請求項19に記載の発光装置。 - 前記第1層の屈折率が、前記第2層の屈折率よりも大きい、請求項21に記載の発光装置。
- 前記第1層の屈折率が約1.6〜約2.45であり、
前記第2層の屈折率が約1.3〜約2.0である、請求項22に記載の発光装置。 - 前記第1層及び前記第2層の屈折率は、前記第1半導体層の屈折率よりも小さい、請求項22に記載の発光装置。
- 前記第1半導体層の屈折率が、約2.0〜約2.5である、請求項24に記載の発光装置。
- 前記基板は、前記突出部が設けられていない領域に粗面を有する、請求項19に記載の発光装置。
- 前記側面は、前記第1半導体層から前記側面に向かって進行する光の90%以上を反射する反射面である、請求項19に記載の発光装置。
- 請求項19〜27のいずれかに記載の発光装置の製造方法であって、
基板を準備する工程と、
前記基板の上面に粗面を形成する工程と、
前記基板の屈折率とは異なる屈折率を有する材料の絶縁層を形成する工程と、
前記絶縁層上にフォトレジストを形成し、フォトリソグラフィを用いてフォトレジストをパターニングする工程と、
前記フォトレジストをリフローする工程と、
前記フォトレジストをマスクとして用いて前記絶縁層及び前記基板をエッチングする工程と、
前記基板上に発光スタックを形成する工程と、
を含む、発光装置の製造方法。 - 前記粗面は、ウェットエッチング、ドライエッチング、及び研削の少なくともいずれか1つによって形成される、請求項28に記載の発光装置の製造方法。
- 前記絶縁層及び前記基板をエッチングする工程は、異方的に行われる、請求項28に記載の発光装置の製造方法。
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KR10-2018-0079626 | 2018-07-09 | ||
KR1020180079626A KR102554230B1 (ko) | 2018-07-09 | 2018-07-09 | 발광 소자 |
KR1020180119585A KR20200039956A (ko) | 2018-10-08 | 2018-10-08 | 발광 소자 및 이의 제조 방법 |
KR10-2018-0119585 | 2018-10-08 | ||
KR10-2018-0122759 | 2018-10-15 | ||
KR1020180122759A KR20200042316A (ko) | 2018-10-15 | 2018-10-15 | 발광 소자 및 이의 제조 방법 |
PCT/KR2019/008410 WO2020013563A1 (ko) | 2018-07-09 | 2019-07-09 | 발광 소자 및 이의 제조 방법 |
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CN112701198A (zh) * | 2020-12-25 | 2021-04-23 | 福建晶安光电有限公司 | 一种图形化衬底、发光二极管及制备方法 |
WO2022134009A1 (zh) * | 2020-12-25 | 2022-06-30 | 福建晶安光电有限公司 | 一种图形化衬底、发光二极管及制备方法 |
CN116544332A (zh) * | 2023-07-06 | 2023-08-04 | 江西兆驰半导体有限公司 | 一种图形化蓝宝石衬底及其制备方法 |
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US20230378394A1 (en) | 2023-11-23 |
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CN113555477A (zh) | 2021-10-26 |
JP7436371B2 (ja) | 2024-02-21 |
US11658264B2 (en) | 2023-05-23 |
CN111801806B (zh) | 2024-04-09 |
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EP3748701A4 (en) | 2022-03-02 |
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