JP2021509499A5 - - Google Patents

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JP2021509499A5
JP2021509499A5 JP2020533853A JP2020533853A JP2021509499A5 JP 2021509499 A5 JP2021509499 A5 JP 2021509499A5 JP 2020533853 A JP2020533853 A JP 2020533853A JP 2020533853 A JP2020533853 A JP 2020533853A JP 2021509499 A5 JP2021509499 A5 JP 2021509499A5
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Japan
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memory device
memory
ecc
channel mode
data
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JP2020533853A
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Japanese (ja)
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JP7146920B2 (ja
JP2021509499A (ja
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JP2020533853A 2018-01-03 2018-12-18 メモリ・コントローラを動作させる方法、デュアル・チャネル・モードからシングル・チャネル・モードに切り替える方法、およびメモリ・コントローラ Active JP7146920B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/860,871 US10546628B2 (en) 2018-01-03 2018-01-03 Using dual channel memory as single channel memory with spares
US15/860,871 2018-01-03
PCT/IB2018/060237 WO2019135134A1 (en) 2018-01-03 2018-12-18 Using dual channel memory as single channel memory with spares

Publications (3)

Publication Number Publication Date
JP2021509499A JP2021509499A (ja) 2021-03-25
JP2021509499A5 true JP2021509499A5 (enExample) 2021-07-26
JP7146920B2 JP7146920B2 (ja) 2022-10-04

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JP2020533853A Active JP7146920B2 (ja) 2018-01-03 2018-12-18 メモリ・コントローラを動作させる方法、デュアル・チャネル・モードからシングル・チャネル・モードに切り替える方法、およびメモリ・コントローラ

Country Status (5)

Country Link
US (2) US10546628B2 (enExample)
EP (1) EP3729272A4 (enExample)
JP (1) JP7146920B2 (enExample)
CN (1) CN111566621B (enExample)
WO (1) WO2019135134A1 (enExample)

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