JP2021501516A5 - - Google Patents
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- JP2021501516A5 JP2021501516A5 JP2020523248A JP2020523248A JP2021501516A5 JP 2021501516 A5 JP2021501516 A5 JP 2021501516A5 JP 2020523248 A JP2020523248 A JP 2020523248A JP 2020523248 A JP2020523248 A JP 2020523248A JP 2021501516 A5 JP2021501516 A5 JP 2021501516A5
- Authority
- JP
- Japan
- Prior art keywords
- flexible grid
- signal
- noise ratio
- channel
- clock recovery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/795,676 US10243671B1 (en) | 2017-10-27 | 2017-10-27 | Clock recovery circuits, systems and implementation for increased optical channel density |
| US15/795,676 | 2017-10-27 | ||
| PCT/US2018/056851 WO2019083878A1 (en) | 2017-10-27 | 2018-10-22 | CIRCUITS, SYSTEMS AND IMPLEMENTATION OF CLOCK FREQUENCY RECOVERY FOR INCREASED OPTICAL CHANNEL DENSITY |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021501516A JP2021501516A (ja) | 2021-01-14 |
| JP2021501516A5 true JP2021501516A5 (https=) | 2021-10-07 |
| JP7244508B2 JP7244508B2 (ja) | 2023-03-22 |
Family
ID=64316986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020523248A Active JP7244508B2 (ja) | 2017-10-27 | 2018-10-22 | 光チャネル密度増加のためのクロック回復回路、システムおよび実装 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US10243671B1 (https=) |
| EP (1) | EP3701645B1 (https=) |
| JP (1) | JP7244508B2 (https=) |
| WO (1) | WO2019083878A1 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10805064B1 (en) | 2019-04-23 | 2020-10-13 | Ciena Corporation | Built-in jitter loading and state of polarization generation to characterize optical transceivers |
| US10715169B1 (en) | 2019-05-21 | 2020-07-14 | Ciena Corporation | Coarse-fine gain-tracking loop and method of operating |
| US11228403B2 (en) * | 2019-12-09 | 2022-01-18 | Skyworks Solutions, Inc. | Jitter self-test using timestamps |
| CN111092714B (zh) * | 2019-12-10 | 2022-05-06 | 中国科学院微电子研究所 | 一种高速信号时钟恢复方法及装置 |
| US11119854B2 (en) * | 2020-02-14 | 2021-09-14 | Elite Semiconductor Memory Technology Inc. | Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device |
| US10985900B1 (en) | 2020-03-03 | 2021-04-20 | Ciena Corporation | Estimating clock phase error based on channel conditions |
| US11381306B2 (en) * | 2020-04-29 | 2022-07-05 | Cisco Technology, Inc. | Bisection searching algorithm to derive optimum baud rate with maximum spectral efficiency exploiting Q-margin-to-SNR-margin conversion |
| US11558061B2 (en) | 2021-04-22 | 2023-01-17 | Ciena Corporation | ADC self-calibration with on-chip circuit and method |
| US11463093B1 (en) | 2021-05-12 | 2022-10-04 | Ciena Corporation | Reducing non-linearities of a phase rotator |
| US11750287B2 (en) | 2021-05-25 | 2023-09-05 | Ciena Corporation | Optical DSP operating at half-baud rate with full data rate converters |
| US11770203B2 (en) * | 2021-09-09 | 2023-09-26 | Ciena Corporation | Matching transmitters with receivers for making network-level assignments |
| CN119156786A (zh) * | 2022-03-23 | 2024-12-17 | 密歇根州立大学董事会 | 光通信的接收器同步 |
| CN119675775A (zh) * | 2024-12-17 | 2025-03-21 | 西安空间无线电技术研究所 | 一种小型化高稳定星载里德堡原子宽频通信接收机系统 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4454798B2 (ja) * | 2000-06-09 | 2010-04-21 | Ｎｅｃエレクトロニクス株式会社 | クロック再生装置 |
| US20060024062A1 (en) | 2004-07-28 | 2006-02-02 | Nortel Networks Limited | Pre-compensation for modulator distortion in optical systems |
| US7512203B2 (en) * | 2005-03-30 | 2009-03-31 | Silicon Laboratories Inc. | Data cleaning with an asynchronous reference clock |
| US7492849B2 (en) * | 2005-05-10 | 2009-02-17 | Ftd Solutions Pte., Ltd. | Single-VCO CDR for TMDS data at gigabit rate |
| US7492195B1 (en) * | 2005-06-22 | 2009-02-17 | Cypress Semiconductor Corp. | Agile, low phase noise clock synthesizer and jitter attenuator |
| US7742507B1 (en) | 2006-03-28 | 2010-06-22 | Nortel Networks Limited | Method and system for phase and byte alignment on a multiplexed high speed bus |
| US20080240230A1 (en) * | 2007-03-29 | 2008-10-02 | Horizon Semiconductors Ltd. | Media processor with an integrated TV receiver |
| US8849882B2 (en) | 2007-10-19 | 2014-09-30 | The Royal Institution for the Association of Learning | Generation of an analog Gaussian noise signal having predetermined characteristics |
| US8855215B2 (en) | 2011-05-09 | 2014-10-07 | The Royal Institution For The Advancement Of Learning/Mcgill University | Phase/frequency synthesis using periodic sigma-delta modulated bit-stream techniques |
| US8497716B2 (en) * | 2011-08-05 | 2013-07-30 | Qualcomm Incorporated | Phase locked loop with phase correction in the feedback loop |
| US8384452B1 (en) * | 2011-09-13 | 2013-02-26 | Cortina Systems, Inc. | Integrated jitter compliant low bandwidth phase locked loops |
| US8786337B2 (en) * | 2012-05-14 | 2014-07-22 | Ensphere Solutions, Inc. | Low jitter clock generator for multiple lanes high speed data transmitter |
| US9037104B2 (en) * | 2013-02-04 | 2015-05-19 | Qualcomm, Incorporated | Receiver that reconfigures between zero intermediate frequency and direct sampling based on channel conditions |
| CN105103508A (zh) * | 2013-03-30 | 2015-11-25 | 中兴通讯股份有限公司 | 从正交相移键控调制光信号恢复数据 |
| US9225430B2 (en) | 2013-05-20 | 2015-12-29 | Ciena Corporation | Digital noise loading for optical receivers |
| US9537493B2 (en) * | 2014-05-21 | 2017-01-03 | Robert Bosch Gmbh | Phase lock loop circuit having a wide bandwidth |
| US9634826B1 (en) * | 2015-11-30 | 2017-04-25 | Intel Corporation | Apparatus and method for automatic bandwidth calibration for phase locked loop |
| US9787466B2 (en) | 2016-03-09 | 2017-10-10 | Ciena Corporation | High order hybrid phase locked loop with digital scheme for jitter suppression |
| KR20190127783A (ko) * | 2017-03-21 | 2019-11-13 | 비프로스트 커뮤니케이션즈 에이피에스 | 고성능 광수신기를 포함한 광학 통신 시스템, 장치 및 방법 |
| US10063367B1 (en) * | 2017-04-28 | 2018-08-28 | Ciena Corporation | Optical clock recovery using feedback phase rotator with non-linear compensation |
-
2017
- 2017-10-27 US US15/795,676 patent/US10243671B1/en active Active
-
2018
- 2018-10-22 EP EP18803818.6A patent/EP3701645B1/en active Active
- 2018-10-22 WO PCT/US2018/056851 patent/WO2019083878A1/en not_active Ceased
- 2018-10-22 JP JP2020523248A patent/JP7244508B2/ja active Active
-
2019
- 2019-02-07 US US16/270,203 patent/US10855380B2/en active Active
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