JP2020534695A5 - - Google Patents

Download PDF

Info

Publication number
JP2020534695A5
JP2020534695A5 JP2020516384A JP2020516384A JP2020534695A5 JP 2020534695 A5 JP2020534695 A5 JP 2020534695A5 JP 2020516384 A JP2020516384 A JP 2020516384A JP 2020516384 A JP2020516384 A JP 2020516384A JP 2020534695 A5 JP2020534695 A5 JP 2020534695A5
Authority
JP
Japan
Prior art keywords
metal
copper
barrier layer
molybdenum
microelectronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020516384A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020534695A (ja
JP7185375B2 (ja
Filing date
Publication date
Priority claimed from US15/954,254 external-priority patent/US10424552B2/en
Application filed filed Critical
Publication of JP2020534695A publication Critical patent/JP2020534695A/ja
Publication of JP2020534695A5 publication Critical patent/JP2020534695A5/ja
Application granted granted Critical
Publication of JP7185375B2 publication Critical patent/JP7185375B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020516384A 2017-09-20 2018-09-20 合金拡散障壁層 Active JP7185375B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762561070P 2017-09-20 2017-09-20
US62/561,070 2017-09-20
US15/954,254 2018-04-16
US15/954,254 US10424552B2 (en) 2017-09-20 2018-04-16 Alloy diffusion barrier layer
PCT/US2018/051874 WO2019060496A1 (en) 2017-09-20 2018-09-20 ALLOY DIFFUSION BARRIER LAYER

Publications (3)

Publication Number Publication Date
JP2020534695A JP2020534695A (ja) 2020-11-26
JP2020534695A5 true JP2020534695A5 (enExample) 2021-11-04
JP7185375B2 JP7185375B2 (ja) 2022-12-07

Family

ID=65720677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020516384A Active JP7185375B2 (ja) 2017-09-20 2018-09-20 合金拡散障壁層

Country Status (4)

Country Link
US (2) US10424552B2 (enExample)
JP (1) JP7185375B2 (enExample)
CN (1) CN111052362B (enExample)
WO (1) WO2019060496A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7353794B2 (ja) * 2019-05-13 2023-10-02 ローム株式会社 半導体装置、その製造方法、及びモジュール
US11380613B2 (en) * 2020-05-29 2022-07-05 Qualcomm Incorporated Repurposed seed layer for high frequency noise control and electrostatic discharge connection
US11753736B2 (en) 2020-11-16 2023-09-12 Raytheon Company Indium electroplating on physical vapor deposition tantalum
US11862593B2 (en) * 2021-05-07 2024-01-02 Microsoft Technology Licensing, Llc Electroplated indium bump stacks for cryogenic electronics
US20230091379A1 (en) * 2021-09-22 2023-03-23 Intel Corporation First level interconnect under bump metallizations for fine pitch heterogeneous applications
JP7357824B1 (ja) * 2022-12-16 2023-10-06 株式会社荏原製作所 めっき装置およびめっき方法
JP7579476B1 (ja) 2024-02-21 2024-11-07 有限会社 ナプラ 端子

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1139413B1 (en) * 2000-03-24 2005-03-16 Texas Instruments Incorporated Wire bonding process
US20050085062A1 (en) * 2003-10-15 2005-04-21 Semitool, Inc. Processes and tools for forming lead-free alloy solder precursors
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
JP2007250849A (ja) * 2006-03-16 2007-09-27 Casio Comput Co Ltd 半導体装置の製造方法
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
JP4829340B2 (ja) * 2009-12-25 2011-12-07 株式会社東芝 半導体装置の製造方法
US9598772B2 (en) 2010-04-16 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating bump structure without UBM undercut
US8922004B2 (en) 2010-06-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump structures having sidewall protection layers
US8232193B2 (en) 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US8283781B2 (en) 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US8664760B2 (en) 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US8698308B2 (en) 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9831201B2 (en) 2015-03-11 2017-11-28 Guy F. Burgess Methods for forming pillar bumps on semiconductor wafers
US9728521B2 (en) * 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
JP6572673B2 (ja) * 2015-08-13 2019-09-11 富士通株式会社 電子装置及び電子装置の製造方法
US9748173B1 (en) * 2016-07-06 2017-08-29 International Business Machines Corporation Hybrid interconnects and method of forming the same
US10431464B2 (en) * 2016-10-17 2019-10-01 International Business Machines Corporation Liner planarization-free process flow for fabricating metallic interconnect structures

Similar Documents

Publication Publication Date Title
US20210167034A1 (en) Chip arrangements
JP4195886B2 (ja) 無鉛はんだを用い反応バリア層を有するフリップ・チップ用相互接続構造を形成するための方法
CN101944496B (zh) 柱状结构及其形成方法、倒装芯片接合结构
US7547623B2 (en) Methods of forming lead free solder bumps
JP7185375B2 (ja) 合金拡散障壁層
CN1254862C (zh) 无铅焊料凸块及其制造方法
JP6287759B2 (ja) 半導体装置とその製造方法
US11587858B2 (en) Zinc-cobalt barrier for interface in solder bond applications
WO2012053178A1 (ja) 半導体接合構造体および半導体接合構造体の製造方法
US12023762B2 (en) Layer structure with an intermetallic phase layer and a chip package that includes the layer structure
CN115881673A (zh) 层结构、芯片封装体以及它们的形成方法和焊料材料
TWI302722B (en) Ubm pad, solder contact and methods for creating a solder joint
JP2006100739A (ja) 接合体、半導体装置、接合方法及び半導体装置の製造方法
TW201127541A (en) Manufacturing method for lead-free solder material mixed with metal micro-particles
CN101044609A (zh) 形成无铅焊料凸块和相关结构的方法
CN112310027B (zh) 将导体焊接到铝层
TWI272152B (en) Doped alloys for electrical interconnects, methods of production and uses thereof
JP6186802B2 (ja) 電子デバイス用の接合構造及び電子デバイス
JP4765099B2 (ja) 半導体装置およびその製造方法
TWI236746B (en) Circuit carrier and bonding pad thereof
Karim et al. Lead-free solder bump technologies for flip-chip packaging applications
TW502424B (en) Method of forming lead-free bump interconnections
JP2002299381A (ja) はんだめっきボールおよびそれを用いた半導体接続構造の製造方法
Yeoh et al. Highly customizable RDL combined with UBM for various solder applications in wafer level packaging
Dai et al. Newly developed in-situ formation of SnAg and SnAgCu solder on copper pillar bump