JP2020167181A - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
JP2020167181A
JP2020167181A JP2019063313A JP2019063313A JP2020167181A JP 2020167181 A JP2020167181 A JP 2020167181A JP 2019063313 A JP2019063313 A JP 2019063313A JP 2019063313 A JP2019063313 A JP 2019063313A JP 2020167181 A JP2020167181 A JP 2020167181A
Authority
JP
Japan
Prior art keywords
layer
heat diffusion
electronic device
diffusion layer
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019063313A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020167181A5 (enExample
Inventor
大佳 國枝
Hiroyoshi Kunieda
大佳 國枝
林　宏樹
Hiroki Hayashi
宏樹 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2019063313A priority Critical patent/JP2020167181A/ja
Priority to CN202080023587.1A priority patent/CN113632218A/zh
Priority to PCT/JP2020/010547 priority patent/WO2020195834A1/ja
Publication of JP2020167181A publication Critical patent/JP2020167181A/ja
Publication of JP2020167181A5 publication Critical patent/JP2020167181A5/ja
Priority to US17/484,337 priority patent/US20220013428A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
JP2019063313A 2019-03-28 2019-03-28 電子装置 Pending JP2020167181A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019063313A JP2020167181A (ja) 2019-03-28 2019-03-28 電子装置
CN202080023587.1A CN113632218A (zh) 2019-03-28 2020-03-11 电子装置
PCT/JP2020/010547 WO2020195834A1 (ja) 2019-03-28 2020-03-11 電子装置
US17/484,337 US20220013428A1 (en) 2019-03-28 2021-09-24 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019063313A JP2020167181A (ja) 2019-03-28 2019-03-28 電子装置

Publications (2)

Publication Number Publication Date
JP2020167181A true JP2020167181A (ja) 2020-10-08
JP2020167181A5 JP2020167181A5 (enExample) 2021-03-25

Family

ID=72611428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019063313A Pending JP2020167181A (ja) 2019-03-28 2019-03-28 電子装置

Country Status (4)

Country Link
US (1) US20220013428A1 (enExample)
JP (1) JP2020167181A (enExample)
CN (1) CN113632218A (enExample)
WO (1) WO2020195834A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024153459A (ja) * 2023-04-17 2024-10-29 株式会社デンソー 半導体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7056620B2 (ja) * 2019-03-28 2022-04-19 株式会社デンソー 電子装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
KR102134133B1 (ko) * 2013-09-23 2020-07-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR20150049622A (ko) * 2013-10-30 2015-05-08 삼성전자주식회사 패키지 온 패키지 장치
CN103560090B (zh) * 2013-10-31 2016-06-15 中国科学院微电子研究所 一种用于PoP封装的散热结构的制作方法
CN104064551B (zh) * 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备
KR102327548B1 (ko) * 2017-10-17 2021-11-16 삼성전자주식회사 반도체 패키지

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024153459A (ja) * 2023-04-17 2024-10-29 株式会社デンソー 半導体装置

Also Published As

Publication number Publication date
US20220013428A1 (en) 2022-01-13
CN113632218A (zh) 2021-11-09
WO2020195834A1 (ja) 2020-10-01

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