WO2020195834A1 - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
WO2020195834A1
WO2020195834A1 PCT/JP2020/010547 JP2020010547W WO2020195834A1 WO 2020195834 A1 WO2020195834 A1 WO 2020195834A1 JP 2020010547 W JP2020010547 W JP 2020010547W WO 2020195834 A1 WO2020195834 A1 WO 2020195834A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
heat diffusion
diffusion layer
electronic device
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2020/010547
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
大佳 國枝
林　宏樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to CN202080023587.1A priority Critical patent/CN113632218A/zh
Publication of WO2020195834A1 publication Critical patent/WO2020195834A1/ja
Priority to US17/484,337 priority patent/US20220013428A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control

Definitions

  • This disclosure relates to electronic devices.
  • PoP Package on Package
  • the present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide an electronic device having improved reliability by improving heat dissipation.
  • the electronic device includes an upper package including an upper chip, a lower package including a lower chip, a printed circuit board including the upper package and the lower package stacked on the upper side, and the lower package. , A heat diffusion layer arranged in the vicinity of the lower chip.
  • heat is efficiently propagated from the lower chip to the heat diffusion layer, so that heat is efficiently released from the lower chip.
  • the heat dissipation of the entire electronic device can be improved, so that it is possible to provide an electronic device with improved reliability.
  • FIG. 1 is a vertical cross-sectional view showing a schematic configuration of an electronic device according to the first embodiment.
  • FIG. 2 is a plan view of the electronic device viewed from above, and is a conceptual diagram showing a schematic configuration of the heat dissipation area.
  • FIG. 3 is a vertical sectional view showing a schematic configuration of the electronic device according to the second embodiment.
  • FIG. 4 is a vertical cross-sectional view showing a schematic configuration of an electronic device according to a second embodiment, and is an enlarged view of a region S in FIG.
  • the electronic device according to the embodiment of the present disclosure will be described with reference to the drawings.
  • the same elements as those described above will be designated by the same reference numerals, and the description thereof will be omitted.
  • the metal case 14 side of the electronic device 1 is upward, and the printed circuit board 16 side is downward.
  • the electronic device 1 As shown in FIGS. 1 and 2, the electronic device 1 according to the first embodiment is a so-called PoP in which two IC packages are laminated.
  • the electronic device 1 includes a printed circuit board 16 (Printed Circuit Board, hereinafter referred to as PCB), a lower package 12, an upper package 10, and a metal case 14 that covers them.
  • the electronic device 1 has a substantially rectangular shape as a flat plate.
  • the upper package 10 and the lower package 12 provided in the electronic device 1 also have a substantially rectangular shape as a flat plate.
  • the lower package 12 and the upper package 10 are stacked and arranged on the upper part of the PCB 16.
  • a plurality of solder balls 20 are arranged between the upper package 10 and the lower package 12.
  • the upper package 10 and the lower package 12 are connected by a plurality of solder balls 20.
  • a plurality of solder balls 22 are arranged between the lower package 12 and the PCB 16.
  • the lower package 12 and the PCB 16 are connected by a plurality of solder balls 22.
  • a thermal interface material 18 (Thermal Interface Material, hereinafter referred to as TIM) is provided between the upper surface of the upper package 10 and the inner ceiling surface of the metal case 14.
  • TIM18 is composed of a substance having high thermal conductivity, and is composed of, for example, silicon and graphite. The TIM 18 is in contact with the upper surface of the upper package 10 and the inner ceiling surface of the metal case 14, and the heat from the upper package 10 is propagated to the metal kale 14.
  • the upper package 10 includes an upper chip 10a, an upper layer 10b, and a lower layer 10c.
  • the upper chip 10a is arranged on the lower layer 10c.
  • the upper surface and side surfaces of the upper chip 10a are covered with the upper layer 10b.
  • the upper chip 10a may be configured such that the upper surface and a part of the side surface are covered with the upper layer 10b.
  • the upper chip 10a is an integrated circuit in which a plurality of transistors, wiring, and the like are mounted on a semiconductor substrate (not shown), the lower layer 10c is, for example, a printed circuit board, and the upper layer 10b is, for example, a mold resin.
  • the upper tip 10a has a substantially rectangular shape as a flat plate.
  • the lower package 12 includes a lower chip 12a, an upper layer 12b, an intermediate layer 12c, a lower layer 12d, and a heat diffusion layer 26.
  • the lower chip 12a is arranged on the lower layer 12d, and a part of the upper surface and the side surface is contacted and covered by the heat diffusion layer 26.
  • the heat diffusion layer 26 is arranged at least in the vicinity of the lower chip 12a.
  • the lateral dimension of the heat diffusion layer 26 is larger than the lateral dimension of the lower chip 12a, and the area of the upper surface of the heat diffusion layer 26 is larger than the area of the upper surface of the lower chip 12a.
  • the lower chip 12a and the heat diffusion layer 26 have a substantially rectangular shape as a flat plate.
  • the intermediate layer 12c is in contact with the side surface of the lower chip 12a and the lower half of the heat diffusion layer 26 and covers a part of these side surfaces and the lower surface of the heat diffusion layer 26. Further, the upper layer 12b is located on the intermediate layer 12c and covers a part of the upper surface and the side surface of the heat diffusion layer 26.
  • the intermediate layer 12c includes a stack via 24 located laterally to the lower insert 12a and the heat diffusion layer 26 and in contact with the upper layer 12b and the lower layer 12d.
  • the stack via 24 is, for example, a solder ball made of solder.
  • a solder ball made of solder.
  • one containing lead and tin as main components may be used, one having copper added thereto, or a lead-free solder containing no lead may be used.
  • a through hole may be provided in the intermediate layer 12c, and a metal such as copper may be embedded in the through hole to form an embedded metal.
  • the heat diffusion layer 26 is made of a substance having a high thermal conductivity, and is configured to have a higher thermal conductivity than the surrounding material, for example, a mold resin.
  • the heat diffusion layer 26 is made of, for example, a metal such as copper or graphite.
  • the heat diffusion layer 26 propagates the heat generated from the lower chip 12a by coming into contact with the lower chip 12a, and further dissipates heat from the surface of the heat diffusion layer 26. Most of the heat dissipated from the heat diffusion layer 26 propagates while diffusing upward with a spread having a predetermined angle. This diffused heat propagates to the metal case 14.
  • the heat dissipation area A is shown so as to be located on the lower surface of the metal case 14.
  • the heat dissipation area A of the electronic device 1 is at least larger than the flat area of the lower chip 12a.
  • the heat dissipation area A is larger than the area of the heat diffusion layer 26.
  • the angle at which heat diffuses from the heat diffusion layer 26 to the metal case 14 differs depending on the material and the like existing between the heat diffusion layer 26 and the metal case 14.
  • the planar shape of the heat radiating area A has a substantially rectangular shape, reflecting the shape of the heat diffusion layer 26 that transfers heat to the metal case 14.
  • the lower chip 12a is an integrated circuit in which a plurality of transistors and wirings are formed on a semiconductor substrate (not shown), the upper layer 12b and the lower layer 12d are, for example, a printed circuit board, and the intermediate layer 12c is, for example, a mold resin.
  • the thermal conductivity of the heat diffusion layer 26 is configured to be at least higher than that of the intermediate layer 12c, that is, higher than that of the mold resin.
  • the heat diffusion layer 26 is arranged in the vicinity of the lower chip 12a, contacts and covers the upper surface of the lower chip 12a, and the thermal conductivity of the heat diffusion layer 26 is larger than that of the mold resin constituting the intermediate layer 12c.
  • the heat generated from the lower chip 12a propagates to the heat diffusion layer 26, is thermally diffused from the heat diffusion layer 26, reaches the metal case 14, and is dissipated to the outside.
  • the heat diffusion layer The thermal conductivity of 26 is configured to be greater than that of the molded resin. Therefore, heat is efficiently propagated from the lower chip 12a to the heat diffusion layer 26. As a result, heat is efficiently released from the lower tip 12a.
  • the upper surface of the heat diffusion layer 26 has a larger area than the upper surface of the lower chip 12a, and the heat diffusion layer 26 is arranged between the upper package 10 and the metal case 14. According to this configuration, the heat generated in the lower chip 12a propagates to the heat diffusion layer 26. That is, the heat generated by the lower chip 12a is transferred to the heat diffusion layer 26 which covers the upper part of the lower chip 12a and has a larger upper surface area than the lower chip 12a, and the heat propagated to the heat diffusion layer 26 is the heat. It is dissipated from the upper surface of the heat diffusion layer 26.
  • the heat from the heat diffusion layer 26 spreads over the heat dissipation area A and propagates to the metal case 14.
  • the heat generated by the lower chip 12a is efficiently propagated to the metal case 14 via the heat diffusion layer 26, so that the heat dissipation of the entire electronic device 1 can be improved. This makes it possible to provide an electronic device with improved reliability.
  • the electronic device 1 has substantially the same configuration as that of the first embodiment, but differs in the following points.
  • the lower package 12 includes a lower chip 12a, an upper layer 12e, an intermediate layer 12f, and a lower layer 12g from the top.
  • the lower chip 12a is arranged on the lower layer 12d.
  • the heat diffusion layer 30 and the heat diffusion portion 32 are arranged in the vicinity of the lower chip 12a.
  • the heat diffusion layer 30 is provided in the upper layer 12e directly above the intermediate layer 12f in which the lower chip 12a is arranged.
  • a substance having high thermal conductivity is used, and is composed of, for example, a metal such as copper.
  • the upper layer 12e is a PCB, and as shown in FIG. 4, includes a plurality of wiring layers 13 and a heat diffusion layer 30 inside.
  • the wiring layer 13 is a wiring layer constituting the circuit of the upper layer 12e which is a PCB.
  • the wiring layer 13 and the heat diffusion layer 30 are made of the same material.
  • the film thickness of the heat diffusion layer 30 is larger than that of the wiring layer 13.
  • the heat diffusion layer 30 is provided at the lowest layer among the wiring layers provided at the upper layer 12e. That is, the heat diffusion layer 30 is made of the same material as the wiring layer 13, and is configured as the lowest layer of the plurality of wiring layers provided in the upper layer 12e. Further, in this case, the heat diffusion layer 30 is configured to be thicker than the wiring layer 13.
  • the heat transfer efficiency is improved by increasing the thickness of the heat diffusion layer 30. Since the size of the plane of the heat diffusion layer 30 is larger than the area of the upper surface of the lower chip 12a, the heat propagated from the lower chip 12a can be efficiently propagated to the heat diffusion layer 30.
  • a plurality of heat diffusion portions 32 provided so as to penetrate the intermediate layer 12f vertically, that is, in the thickness direction are provided.
  • the heat diffusion unit 32 is, for example, a solder ball made of solder.
  • the heat diffusing unit 32 one containing lead and tin as main components may be used, one to which copper is added, or a lead-free solder containing no lead may be used.
  • the heat diffusion portion 32 may be configured as a through electrode formed by providing a through hole in the intermediate layer 12f and embedding a metal such as copper in the through hole.
  • the heat diffusion layer 30 and the heat diffusion unit 32 are configured to have a higher thermal conductivity than the materials surrounding the heat diffusion layer 30 and the heat diffusion unit 32, for example, a mold resin.
  • the following effects are obtained.
  • the same effect as that of the electronic device 1 according to the first embodiment can be obtained.
  • the heat diffusion layer 30 is configured as the wiring layer 13 provided in the upper layer 12b, the heat diffusion layer 30 can be formed by using the wiring formation step. Therefore, the heat diffusion layer 30 can be easily formed.
  • the heat diffusion layer 30 is provided as the lowest layer in the upper layer 12e directly above the lower chip 12a, the heat diffusion layer 30 can be arranged in the vicinity of the lower chip 12a. Further, the thickness of the heat diffusion layer 30 is made thicker than that of the wiring layer 13. Therefore, the heat transfer efficiency from the lower chip 12a to the heat diffusion layer 30 is improved, and the heat generated by the lower chip 12a can be efficiently propagated to the heat diffusion layer 30.
  • the heat diffusion portion 32 is arranged in the vicinity of the lower chip 12a in the lateral direction.
  • the heat generated in the lateral direction of the lower chip 12a propagates to the heat diffusion unit 32, and can be transmitted from the heat diffusion unit 32 to the upper layer 12e connected to the heat diffusion unit 32 and propagated to the heat diffusion layer 30. Therefore, due to the presence of the heat diffusion unit 32, the heat generated by the lower chip 12a is efficiently propagated to the metal case 14, so that the heat dissipation of the entire electronic device 1 can be further improved.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
PCT/JP2020/010547 2019-03-28 2020-03-11 電子装置 Ceased WO2020195834A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080023587.1A CN113632218A (zh) 2019-03-28 2020-03-11 电子装置
US17/484,337 US20220013428A1 (en) 2019-03-28 2021-09-24 Electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-063313 2019-03-28
JP2019063313A JP2020167181A (ja) 2019-03-28 2019-03-28 電子装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/484,337 Continuation US20220013428A1 (en) 2019-03-28 2021-09-24 Electronic device

Publications (1)

Publication Number Publication Date
WO2020195834A1 true WO2020195834A1 (ja) 2020-10-01

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Application Number Title Priority Date Filing Date
PCT/JP2020/010547 Ceased WO2020195834A1 (ja) 2019-03-28 2020-03-11 電子装置

Country Status (4)

Country Link
US (1) US20220013428A1 (enExample)
JP (1) JP2020167181A (enExample)
CN (1) CN113632218A (enExample)
WO (1) WO2020195834A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7056620B2 (ja) * 2019-03-28 2022-04-19 株式会社デンソー 電子装置
JP2024153459A (ja) * 2023-04-17 2024-10-29 株式会社デンソー 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
KR102134133B1 (ko) * 2013-09-23 2020-07-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR20150049622A (ko) * 2013-10-30 2015-05-08 삼성전자주식회사 패키지 온 패키지 장치
CN103560090B (zh) * 2013-10-31 2016-06-15 中国科学院微电子研究所 一种用于PoP封装的散热结构的制作方法
CN104064551B (zh) * 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备
KR102327548B1 (ko) * 2017-10-17 2021-11-16 삼성전자주식회사 반도체 패키지

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure

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Publication number Publication date
US20220013428A1 (en) 2022-01-13
CN113632218A (zh) 2021-11-09
JP2020167181A (ja) 2020-10-08

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