JP2020064975A - Method for inspecting laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor - Google Patents

Method for inspecting laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor Download PDF

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JP2020064975A
JP2020064975A JP2018195842A JP2018195842A JP2020064975A JP 2020064975 A JP2020064975 A JP 2020064975A JP 2018195842 A JP2018195842 A JP 2018195842A JP 2018195842 A JP2018195842 A JP 2018195842A JP 2020064975 A JP2020064975 A JP 2020064975A
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ceramic capacitor
voltage
monolithic ceramic
monolithic
laminated ceramic
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JP7110902B2 (en
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知之 大谷
Tomoyuki Otani
知之 大谷
良直 西岡
Yoshinao Nishioka
良直 西岡
藤井　裕雄
Hiroo Fujii
裕雄 藤井
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Abstract

To provide a method for inspecting a laminated ceramic capacitor, which can detect a new crack generated during the inspection of structural defects with high reliability.SOLUTION: A method includes a measurement step of measuring a value of a current flowing through a laminated ceramic capacitor 1 while applying a voltage to the laminated ceramic capacitor 1. The measurement step includes a determination step of determining the laminated ceramic capacitor 1 in which an abnormal current has been detected as abnormal. In the measurement step, a voltage is applied to the laminated ceramic capacitor 1 such that a current flowing through the laminated ceramic capacitor 1 falls below a predetermined current value when there is no structural defect.SELECTED DRAWING: Figure 5

Description

本発明は、積層セラミックコンデンサの検査方法及び積層セラミックコンデンサの製造方法に関する。   The present invention relates to a method for inspecting a laminated ceramic capacitor and a method for manufacturing a laminated ceramic capacitor.

従来、種々の電子装置に、積層セラミックコンデンサが用いられている。積層セラミックコンデンサは、通常、セラミック素体と、セラミック素体内に配されており、セラミック部を介して対向している第１及び第２の内部電極を有する。積層セラミックコンデンサでは、セラミック素体にデラミネーションなどの構造欠陥が存在すると、電圧印加時に絶縁不良が発生する場合がある。このため、製造された積層セラミックコンデンサに対して、出荷前に、構造欠陥の有無を検査することが行われている。特許文献１では、検査方法の一例として、第１及び第２の内部電極間に高電圧を印加することにより、絶縁不良の原因となり得る構造欠陥の有無を検査する方法が提案されている。第１及び第２の内部電極間に高電圧を印加すると、構造欠陥を有する積層セラミックコンデンサは、絶縁破壊される。このため、積層セラミックコンデンサの電気抵抗が低下し、積層セラミックコンデンサを流れる電流が増大する。よって、第１及び第２の内部電極間に高電圧を印加した後に、第１及び第２の内部電極間に流れる電流をモニタリングすることにより積層セラミックコンデンサの構造欠陥を検査し得る。   Conventionally, multilayer ceramic capacitors have been used in various electronic devices. The monolithic ceramic capacitor usually has a ceramic body and first and second internal electrodes that are arranged inside the ceramic body and face each other with a ceramic portion interposed therebetween. In a monolithic ceramic capacitor, if there is a structural defect such as delamination in the ceramic body, insulation failure may occur when a voltage is applied. Therefore, the manufactured monolithic ceramic capacitors are inspected for structural defects before shipment. Patent Document 1 proposes, as an example of an inspection method, a method of inspecting for the presence or absence of structural defects that may cause insulation failure by applying a high voltage between the first and second internal electrodes. When a high voltage is applied between the first and second internal electrodes, the monolithic ceramic capacitor having a structural defect is dielectrically broken down. Therefore, the electric resistance of the monolithic ceramic capacitor is lowered, and the current flowing through the monolithic ceramic capacitor is increased. Therefore, the structural defect of the monolithic ceramic capacitor can be inspected by applying a high voltage between the first and second internal electrodes and then monitoring the current flowing between the first and second internal electrodes.

特開２００１−３５７５８号公報JP, 2001-35758, A

しかしながら、構造欠陥を検査する際に積層セラミックコンデンサに高電圧を印加すると、電歪と呼ばれるセラミックの歪みが顕著となる。このため、積層セラミックコンデンサに新たにクラックが生じることがある。この新たに生じたクラックは、構造欠陥の検査中に生じるものであり、クラックが生じても検査中に絶縁破壊されない場合がある。しかしながら、クラックが存在すると、積層セラミックコンデンサの使用時において、クラックが進展し、絶縁不良が生じるおそれがある。従って、検査工程において生じたクラックも検出する必要がある。   However, when a high voltage is applied to the multilayer ceramic capacitor when inspecting for structural defects, distortion of the ceramic called electrostriction becomes significant. Therefore, a crack may newly occur in the monolithic ceramic capacitor. The newly generated cracks are generated during the inspection of structural defects, and even if the cracks are generated, dielectric breakdown may not occur during the inspection. However, if cracks exist, there is a possibility that cracks may develop and insulation failure may occur when the multilayer ceramic capacitor is used. Therefore, it is necessary to detect cracks generated in the inspection process.

しかしながら、特許文献１に記載の検査方法では、構造欠陥を検査するために高電圧を印加したときに生じたクラックを検出することはできない。   However, the inspection method described in Patent Document 1 cannot detect cracks generated when a high voltage is applied to inspect structural defects.

本発明の主な目的は、構造欠陥の検査中に生じた新たなクラックも高い確実性で検出し得る積層セラミックコンデンサの検査方法を提供することにある。   A main object of the present invention is to provide a method for inspecting a monolithic ceramic capacitor that can detect a new crack generated during an inspection for structural defects with high reliability.

本発明に係る積層セラミックコンデンサの検査方法では、積層セラミックコンデンサに電圧を印加しながら、積層セラミックコンデンサに流れる電流値を測定する測定工程を行う。測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程を行う。測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように積層セラミックコンデンサに電圧を印加する。   In the method for inspecting a monolithic ceramic capacitor according to the present invention, a measurement step of measuring a current value flowing through the monolithic ceramic capacitor while applying a voltage to the monolithic ceramic capacitor is performed. A determination process is performed to determine that the monolithic ceramic capacitor in which an abnormal current is detected in the measurement process is abnormal. In the measuring step, a voltage is applied to the monolithic ceramic capacitor such that the current flowing through the monolithic ceramic capacitor falls below a predetermined current value when no structural defect exists.

本発明に係る積層セラミックコンデンサの検査方法のある特定の局面では、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧まで漸増させる。   In a specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, in the measuring step, the monolithic ceramic capacitor is so arranged that the current flowing through the monolithic ceramic capacitor falls below a predetermined current value when there is no structural defect. The applied voltage is gradually increased to a voltage higher than the rated voltage of the monolithic ceramic capacitor.

本発明に係る積層セラミックコンデンサの検査方法の別の特定の局面では、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧から定格電圧以下まで漸減させる。   In another specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, in the measuring step, the monolithic ceramic capacitor is controlled so that the current flowing through the monolithic ceramic capacitor falls below a predetermined current value when no structural defect exists. The voltage applied to is gradually reduced from a voltage higher than the rated voltage of the multilayer ceramic capacitor to a rated voltage or less.

本発明に係る積層セラミックコンデンサの検査方法の他の特定の局面では、測定工程において、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧まで上昇させた後に、当該電圧で保持し、その後、積層セラミックコンデンサの定格電圧以下の電圧まで低下させる。   In another specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, in the measurement step, after increasing the voltage applied to the monolithic ceramic capacitor to a voltage higher than the rated voltage of the monolithic ceramic capacitor, Hold and then reduce to a voltage below the rated voltage of the monolithic ceramic capacitor.

本発明に係る積層セラミックコンデンサの検査方法のさらに他の特定の局面では、測定工程において、積層セラミックコンデンサに正電圧及び負電圧の一方を印加した後に正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行う。   In still another specific aspect of the method for inspecting a laminated ceramic capacitor according to the present invention, in the measuring step, a cycle of applying one of the positive voltage and the negative voltage to the laminated ceramic capacitor and then applying the other of the positive voltage and the negative voltage is performed. Do at least once.

本発明に係る積層セラミックコンデンサの製造方法では、積層セラミックコンデンサを作製する。積層セラミックコンデンサに電圧を印加しながら、積層セラミックコンデンサに流れる電流値を測定する測定工程を行う。測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程を行う。測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように積層セラミックコンデンサに電圧を印加する。   In the method for manufacturing a monolithic ceramic capacitor according to the present invention, a monolithic ceramic capacitor is manufactured. A measurement process of measuring a current value flowing through the multilayer ceramic capacitor while applying a voltage to the multilayer ceramic capacitor is performed. A determination process is performed to determine that the monolithic ceramic capacitor in which an abnormal current is detected in the measurement process is abnormal. In the measuring step, a voltage is applied to the monolithic ceramic capacitor such that the current flowing through the monolithic ceramic capacitor falls below a predetermined current value when no structural defect exists.

本発明によれば、構造欠陥の検査中に、新たに生じたクラックも高い確実性で検出し得る積層セラミックコンデンサの検査方法を提供することができる。   According to the present invention, it is possible to provide a method for inspecting a monolithic ceramic capacitor that can detect a newly-generated crack with high reliability during inspection of a structural defect.

本発明の一実施形態における積層セラミックコンデンサの略図的斜視図である。1 is a schematic perspective view of a monolithic ceramic capacitor according to an embodiment of the present invention. 図１の線ＩＩ−ＩＩにおける略図的断面図である。FIG. 2 is a schematic sectional view taken along line II-II in FIG. 1. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）と、積層セラミックコンデンサが良品であった場合に測定される電流（実線）とを表すグラフである。6 is a graph showing a voltage applied to the laminated ceramic capacitor (dashed line) in the measurement process in one embodiment of the present invention and a current (solid line) measured when the laminated ceramic capacitor is a good product. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）と、積層セラミックコンデンサに短絡不良が発生した場合に測定される電流（実線）とを表すグラフである。6 is a graph showing a voltage (dotted line) applied to the laminated ceramic capacitor in the measurement step in one embodiment of the present invention and a current (solid line) measured when a short circuit failure occurs in the laminated ceramic capacitor. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）と、積層セラミックコンデンサにクラックが発生した場合に測定される電流（実線）とを表すグラフである。6 is a graph showing a voltage applied to the multilayer ceramic capacitor (dashed line) and a current measured when a crack occurs in the multilayer ceramic capacitor (solid line) in the measurement process in the embodiment of the present invention. 第１の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in a 1st modification. 第２の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in the 2nd modification. 第４の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in the 4th modification. 第５の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in a 5th modification. 第７の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in the 7th modification. 第８の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in the 8th modification. 第９の変形例における測定工程において積層セラミックコンデンサに印加する電圧（一点鎖線）を表すグラフである。It is a graph showing the voltage (dashed-dotted line) applied to a multilayer ceramic capacitor in the measurement process in the 9th modification.

以下、本発明を実施した好ましい形態の一例について説明する。但し、下記の実施形態は、単なる例示である。本発明は、下記の実施形態に何ら限定されない。   Hereinafter, an example of a preferable mode for carrying out the present invention will be described. However, the following embodiments are merely examples. The present invention is not limited to the embodiments described below.

また、実施形態等において参照する各図面において、実質的に同一の機能を有する部材は同一の符号で参照することとする。また、実施形態等において参照する図面は、模式的に記載されたものである。図面に描画された物体の寸法の比率などは、現実の物体の寸法の比率などとは異なる場合がある。図面相互間においても、物体の寸法比率等が異なる場合がある。具体的な物体の寸法比率等は、以下の説明を参酌して判断されるべきである。   In each drawing referred to in the embodiments and the like, members having substantially the same function are referred to by the same reference numeral. Further, the drawings referred to in the embodiments and the like are schematically described. The dimensional ratio of the object drawn in the drawing may be different from the dimensional ratio of the actual object. The dimensional ratio of objects may be different between the drawings. Specific dimensional ratios of objects should be determined in consideration of the following description.

図１は、本実施形態における積層セラミックコンデンサの略図的斜視図である。図２は、図１の線ＩＩ−ＩＩにおける略図的断面図である。まず、図１及び図２を参照しながら、検査対象となる積層セラミックコンデンサの一例について説明する。本発明において、積層セラミックコンデンサは、以下に説明する積層セラミックコンデンサ１に特に限定されない。本発明において、積層セラミックコンデンサは、セラミック素体を有するものである限りにおいて特に限定されない。   FIG. 1 is a schematic perspective view of a monolithic ceramic capacitor according to this embodiment. 2 is a schematic sectional view taken along line II-II in FIG. First, an example of a monolithic ceramic capacitor to be inspected will be described with reference to FIGS. 1 and 2. In the present invention, the laminated ceramic capacitor is not particularly limited to the laminated ceramic capacitor 1 described below. In the present invention, the laminated ceramic capacitor is not particularly limited as long as it has a ceramic body.

（積層セラミックコンデンサ１の構成）
図１及び図２に示されるように、積層セラミックコンデンサ１は、セラミック素体１０を備えている。セラミック素体１０は、略直方体状である。セラミック素体１０は、第１及び第２の主面１０ａ，１０ｂと、第１及び第２の側面１０ｃ，１０ｄと、第１及び第２の端面１０ｅ，１０ｆ（図２を参照）とを有する。第１及び第２の主面１０ａ，１０ｂは、それぞれ、長さ方向Ｌ及び幅方向Ｗに沿って延びている。第１の主面１０ａと第２の主面１０ｂとは、互いに平行である。第１及び第２の側面１０ｃ，１０ｄは、それぞれ、長さ方向Ｌ及び厚み方向Ｔに沿って延びている。第１の側面１０ｃと第２の側面１０ｄとは、互いに平行である。第１及び第２の端面１０ｅ，１０ｆは、それぞれ、幅方向Ｗ及び厚み方向Ｔに沿って延びている。第１の端面１０ｅと第２の端面１０ｆとは互いに平行である。 (Structure of monolithic ceramic capacitor 1)
As shown in FIGS. 1 and 2, the monolithic ceramic capacitor 1 includes a ceramic body 10. The ceramic body 10 has a substantially rectangular parallelepiped shape. The ceramic body 10 has first and second main surfaces 10a and 10b, first and second side surfaces 10c and 10d, and first and second end surfaces 10e and 10f (see FIG. 2). . The first and second main surfaces 10a and 10b extend along the length direction L and the width direction W, respectively. The first main surface 10a and the second main surface 10b are parallel to each other. The first and second side faces 10c and 10d extend along the length direction L and the thickness direction T, respectively. The first side surface 10c and the second side surface 10d are parallel to each other. The first and second end faces 10e and 10f extend along the width direction W and the thickness direction T, respectively. The first end face 10e and the second end face 10f are parallel to each other.

セラミック素体１０は、例えば、誘電体セラミックを主成分とする材料により構成することができる。誘電体セラミックの具体例としては、例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３、ＣａＺｒＯ３などが挙げられる。セラミック素体１０には、例えば、Ｍｎ化合物、Ｍｇ化合物、Ｓｉ化合物、Ｃｏ化合物、Ｎｉ化合物、希土類化合物などの副成分を適宜添加してもよい。 The ceramic body 10 can be made of, for example, a material containing a dielectric ceramic as a main component. Specific examples of the dielectric ceramics include BaTiO 3 , CaTiO 3 , SrTiO 3 , CaZrO 3 and the like. Subelements such as Mn compounds, Mg compounds, Si compounds, Co compounds, Ni compounds, and rare earth compounds may be appropriately added to the ceramic body 10.

なお、「略直方体」には、角部や稜線部が面取りされた直方体や、角部や稜線部が丸められた直方体が含まれるものとする。   The “substantially rectangular parallelepiped” includes a rectangular parallelepiped whose corners and ridges are chamfered and a rectangular parallelepiped whose corners and ridges are rounded.

図２に示されるように、セラミック素体１０の内部には、複数の内部電極１１，１２が設けられている。複数の内部電極１１，１２は、厚み方向Ｔに沿って積層されている。各内部電極１１，１２は、長さ方向Ｌ及び幅方向Ｗに平行に設けられている。セラミック素体１０の内部において、内部電極１１と内部電極１２とは、厚み方向Ｔに沿って交互に設けられている。厚み方向Ｔにおいて隣り合う内部電極１１，１２間には、セラミック部１５が配されている。すなわち、厚み方向Ｔにおいて隣り合う内部電極１１，１２は、セラミック部１５を介して対向している。   As shown in FIG. 2, a plurality of internal electrodes 11 and 12 are provided inside the ceramic body 10. The plurality of internal electrodes 11, 12 are stacked along the thickness direction T. The internal electrodes 11 and 12 are provided in parallel to the length direction L and the width direction W. Inside the ceramic body 10, the internal electrodes 11 and the internal electrodes 12 are alternately provided along the thickness direction T. The ceramic portion 15 is arranged between the internal electrodes 11 and 12 that are adjacent to each other in the thickness direction T. That is, the internal electrodes 11 and 12 that are adjacent to each other in the thickness direction T face each other with the ceramic portion 15 interposed therebetween.

内部電極１１は、第１の端面１０ｅに引き出されている。第１の端面１０ｅの上には、外部電極１３が設けられている。外部電極１３は、内部電極１１と電気的に接続されている。   The internal electrode 11 is drawn out to the first end face 10e. The external electrode 13 is provided on the first end surface 10e. The external electrode 13 is electrically connected to the internal electrode 11.

内部電極１２は、第２の端面１０ｆに引き出されている。第２の端面１０ｆの上には、外部電極１４が設けられている。外部電極１４は、内部電極１２と電気的に接続されている。   The internal electrode 12 is drawn out to the second end face 10f. The external electrode 14 is provided on the second end face 10f. The outer electrode 14 is electrically connected to the inner electrode 12.

内部電極１１，１２及び外部電極１３，１４は、例えば、Ｎｉ，Ｃｕ，Ａｇ，Ｐｄ，Ａｕ，Ａｇ−Ｐｄ合金などの適宜の導電材料により構成することができる。   The internal electrodes 11 and 12 and the external electrodes 13 and 14 can be made of an appropriate conductive material such as Ni, Cu, Ag, Pd, Au, and Ag-Pd alloy.

（積層セラミックコンデンサ１の製造方法）
積層セラミックコンデンサ１の製造に際しては、まず、積層セラミックコンデンサ１を作製する。その後、下記の検査方法による検査を行う。その検査結果を踏まえ、良品と不良品とに選別する。このようにすることにより、絶縁不良品や検査中に新たに生じたクラックを有する積層セラミックコンデンサの割合が低い、複数の積層セラミックコンデンサを製造することができる。 (Method of manufacturing laminated ceramic capacitor 1)
In manufacturing the monolithic ceramic capacitor 1, first, the monolithic ceramic capacitor 1 is manufactured. After that, the inspection is performed by the following inspection method. Based on the inspection result, it is sorted into a good product and a defective product. By doing so, it is possible to manufacture a plurality of monolithic ceramic capacitors in which the proportion of defective insulation products or monolithic ceramic capacitors having cracks newly generated during inspection is low.

（積層セラミックコンデンサ１の検査方法）
本実施形態における積層セラミックコンデンサ１の検査方法では、検査前に生じていた構造欠陥を有する積層セラミックコンデンサの判別だけでなく、検査中に新たに生じたクラックも高い確実性で検出することができる。 (Inspection method for monolithic ceramic capacitor 1)
In the method for inspecting the monolithic ceramic capacitor 1 according to the present embodiment, not only the monolithic ceramic capacitor having a structural defect that occurred before the inspection can be discriminated but also a crack newly generated during the inspection can be detected with high reliability. .

具体的には、積層セラミックコンデンサ１に電圧を印加しながら、積層セラミックコンデンサ１に流れる電流値を測定する（測定工程）。測定工程において、異常電流が検出された積層セラミックコンデンサ１を異常（不良品）と判断する（判定工程）。測定工程において、積層セラミックコンデンサ１に構造欠陥が存在しない場合に積層セラミックコンデンサ１を流れる電流が予め定められた電流値（制限電流値）を下回るように積層セラミックコンデンサ１に電圧を印加する。予め定められた電流値は、例えば、１０ｍＡ、３０ｍＡ、５０ｍＡなどの値である。予め定められた電流値は、検査に用いられる電源や回路上に設けられた過電流を防止する機構により設定された電流の制限値であることが好ましい。   Specifically, the value of the current flowing through the laminated ceramic capacitor 1 is measured while applying a voltage to the laminated ceramic capacitor 1 (measurement step). In the measurement process, the monolithic ceramic capacitor 1 in which the abnormal current is detected is determined to be abnormal (defective product) (determination process). In the measuring step, a voltage is applied to the monolithic ceramic capacitor 1 such that the current flowing through the monolithic ceramic capacitor 1 falls below a predetermined current value (limit current value) when there is no structural defect in the monolithic ceramic capacitor 1. The predetermined current value is, for example, a value of 10 mA, 30 mA, 50 mA or the like. The predetermined current value is preferably a current limit value set by a power supply used for inspection or a mechanism provided on a circuit for preventing overcurrent.

例えば、積層セラミックコンデンサに印加する電圧を一気に上昇させた場合は、積層セラミックコンデンサに大電流が流れる。このため、積層セラミックコンデンサ１に流れる電流が制限電流値に達する場合がある。一方、本実施形態では、積層セラミックコンデンサ１に印加する電圧を、積層セラミックコンデンサ１の定格電圧よりも低い電圧（例えば、０Ｖ）から、積層セラミックコンデンサ１の定格電圧よりも高い電圧（Ｖ１）まで漸増させる。また、積層セラミックコンデンサ１に印加する電圧を、積層セラミックコンデンサ１の定格電圧よりも高い電圧（Ｖ１）から積層セラミックコンデンサ１の定格電圧よりも低い電圧（例えば、０Ｖ）まで漸減させる。より具体的には、本実施形態では、積層セラミックコンデンサ１に印加する電圧を、積層セラミックコンデンサ１の定格電圧よりも低い電圧（例えば、０Ｖ）から、積層セラミックコンデンサ１の定格電圧よりも高い電圧（Ｖ１）まで漸増させる。その後、積層セラミックコンデンサ１に印加する電圧をＶ１で所定の時間保持し、その後、積層セラミックコンデンサ１に印加する電圧を、積層セラミックコンデンサ１の定格電圧よりも高い電圧（Ｖ１）から積層セラミックコンデンサ１の定格電圧よりも低い電圧（例えば、０Ｖ）まで漸減させる。このため、積層セラミックコンデンサ１に構造欠陥が存在しない場合に積層セラミックコンデンサ１を流れる電流が予め定められた電流値（制限電流値）を下回る。   For example, when the voltage applied to the monolithic ceramic capacitor is increased at once, a large current flows through the monolithic ceramic capacitor. Therefore, the current flowing through the monolithic ceramic capacitor 1 may reach the limiting current value. On the other hand, in the present embodiment, the voltage applied to the monolithic ceramic capacitor 1 ranges from a voltage lower than the rated voltage of the monolithic ceramic capacitor 1 (for example, 0V) to a voltage higher than the rated voltage of the monolithic ceramic capacitor 1 (V1). Gradually increase. Further, the voltage applied to the monolithic ceramic capacitor 1 is gradually reduced from a voltage higher than the rated voltage of the monolithic ceramic capacitor 1 (V1) to a voltage lower than the rated voltage of the monolithic ceramic capacitor 1 (for example, 0V). More specifically, in the present embodiment, the voltage applied to the laminated ceramic capacitor 1 is changed from a voltage lower than the rated voltage of the laminated ceramic capacitor 1 (for example, 0 V) to a voltage higher than the rated voltage of the laminated ceramic capacitor 1. Gradually increase to (V1). Thereafter, the voltage applied to the monolithic ceramic capacitor 1 is maintained at V1 for a predetermined time, and then the voltage applied to the monolithic ceramic capacitor 1 is changed from a voltage (V1) higher than the rated voltage of the monolithic ceramic capacitor 1 to the monolithic ceramic capacitor 1. Is gradually reduced to a voltage lower than the rated voltage (for example, 0V). Therefore, when there is no structural defect in the monolithic ceramic capacitor 1, the current flowing through the monolithic ceramic capacitor 1 falls below a predetermined current value (limit current value).

上記のような電圧の印加を行った場合、積層セラミックコンデンサ１に構造欠陥がなければ、積層セラミックコンデンサ１を流れる電流は、図３の実線で示すグラフのようになる。すなわち、まず、積層セラミックコンデンサ１に対して電圧の印加が開始されると、積層セラミックコンデンサ１への充電が開始する。このため、積層セラミックコンデンサ１を流れる電流値が増大する。図３においては、電圧を直線的に漸増させている。その後、積層セラミックコンデンサ１のＤＣバイアス特性に従って電流が漸減する。印加電圧が一定の状態では、積層セラミックコンデンサ１の充電がさらに進み、電流はさらに漸減する。一方、電圧が漸減すると、放電が起こるため、正逆が反対方向の電流が流れる。図３においては、電圧を直線的に漸減させている。   When the voltage is applied as described above, if the multilayer ceramic capacitor 1 has no structural defect, the current flowing through the multilayer ceramic capacitor 1 becomes as shown by the solid line graph in FIG. That is, first, when voltage application to the monolithic ceramic capacitor 1 is started, charging of the monolithic ceramic capacitor 1 is started. Therefore, the value of the current flowing through the monolithic ceramic capacitor 1 increases. In FIG. 3, the voltage is gradually increased linearly. After that, the current gradually decreases according to the DC bias characteristic of the monolithic ceramic capacitor 1. When the applied voltage is constant, the charging of the monolithic ceramic capacitor 1 further progresses, and the current further gradually decreases. On the other hand, when the voltage gradually decreases, discharge occurs, so that a current flows in the forward and reverse directions. In FIG. 3, the voltage is linearly gradually decreased.

図４に、測定工程において積層セラミックコンデンサに印加される電圧と、積層セラミックコンデンサに短絡不良が発生した場合に測定される電流とを表すグラフを示す。例えば、測定工程の途中で積層セラミックコンデンサ１に短絡不良が発生すると、積層セラミックコンデンサ１を流れる電流値が制限電流値に達し、積層セラミックコンデンサ１への電圧印加が終了するまで、制限電流値の電流が流れる。図４に示す例では、時間ｔ１において短絡不良が発生したため、時間ｔ１までは、図３に示す場合と同様に電流値が変化するが、時間ｔ１から積層セラミックコンデンサ１への電圧印加が終了する時間ｔ２までは、積層セラミックコンデンサ１に制限電流値の電流が流れ続ける。仮に、測定工程の実施前から積層セラミックコンデンサ１に短絡不良が発生している場合は、測定工程の全期間において積層セラミックコンデンサ１に制限電流値の電流が流れ続ける。   FIG. 4 is a graph showing the voltage applied to the laminated ceramic capacitor in the measurement process and the current measured when a short circuit defect occurs in the laminated ceramic capacitor. For example, if a short circuit failure occurs in the monolithic ceramic capacitor 1 during the measurement process, the current value flowing through the monolithic ceramic capacitor 1 reaches the limiting current value, and the limiting current value is kept until the voltage application to the monolithic ceramic capacitor 1 ends. An electric current flows. In the example shown in FIG. 4, since a short circuit failure has occurred at time t1, the current value changes until time t1 as in the case shown in FIG. 3, but the voltage application to the laminated ceramic capacitor 1 ends at time t1. Until the time t2, the current of the limited current value continues to flow in the monolithic ceramic capacitor 1. If a short circuit failure has occurred in the monolithic ceramic capacitor 1 before the measurement process is performed, the current of the limited current value continues to flow in the monolithic ceramic capacitor 1 during the entire period of the measurement process.

このため、測定工程において、測定された電流値が、制限電流値に達した場合は、測定対象である積層セラミックコンデンサ１に短絡不良があるものと判断することができる。   Therefore, when the measured current value reaches the limited current value in the measurement step, it can be determined that the multilayer ceramic capacitor 1 as the measurement target has a short circuit defect.

図５に、測定工程において積層セラミックコンデンサに印加する電圧と、積層セラミックコンデンサに短絡不良は発生しなかったものの、クラックが発生した場合に測定される電流とを表すグラフを示す。図５に示される例では、時間ｔ３において、図３に示される良品の場合とは異なり、積層セラミックコンデンサ１を流れる電流値の一時的な増大が生じている。すなわち、異常電流が検出されている。本発明者らが鋭意研究した結果、このような異常電流が検出された積層セラミックコンデンサ１には、クラックが発生していることが見いだされた。よって、積層セラミックコンデンサ１を流れる電流が制限電流値に至らないものの、図５に示されるような異常電流が発生した場合は、測定対象である積層セラミックコンデンサ１にクラックが発生したものと判断することができる。なお、このような異常電流が生じている区間において、積層セラミックコンデンサを流れる電流が制限電流値に達することはあり得る。   FIG. 5 is a graph showing the voltage applied to the monolithic ceramic capacitor in the measuring step and the current measured when a crack occurs although no short circuit failure has occurred in the monolithic ceramic capacitor. In the example shown in FIG. 5, unlike the non-defective product shown in FIG. 3, at time t3, the current value flowing through the monolithic ceramic capacitor 1 temporarily increases. That is, the abnormal current is detected. As a result of diligent research conducted by the present inventors, it was found that cracks occurred in the monolithic ceramic capacitor 1 in which such an abnormal current was detected. Therefore, when the abnormal current as shown in FIG. 5 occurs even though the current flowing through the monolithic ceramic capacitor 1 does not reach the limit current value, it is determined that a crack has occurred in the monolithic ceramic capacitor 1 to be measured. be able to. It is possible that the current flowing through the monolithic ceramic capacitor reaches the limiting current value in the section where such an abnormal current occurs.

本実施形態のように、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサ１を流れる電流が予め定められた電流値（例えば、制限電流値）を下回るように積層セラミックコンデンサ１に電圧を印加することにより、図５に示されるような異常電流を正確に検出することが可能となる。従って、絶縁不良が発生していないものの、クラックが発生した積層セラミックコンデンサ１を判別することが可能となる。よって、検査前に生じていた構造欠陥だけでなく、検査中に新たに生じたクラックも高い確実性で検出し得る。また、クラックの検出に、超音波探傷等の他の工程を必要としないため、積層セラミックコンデンサ１の測定工程に要する工数及び時間を低減することができる。   As in the present embodiment, in the measurement process, when a structural defect does not exist, a voltage is applied to the laminated ceramic capacitor 1 so that the current flowing through the laminated ceramic capacitor 1 falls below a predetermined current value (for example, a limited current value). By applying, it becomes possible to accurately detect the abnormal current as shown in FIG. Therefore, it is possible to discriminate the monolithic ceramic capacitor 1 in which a crack has occurred although no insulation failure has occurred. Therefore, not only a structural defect that has occurred before the inspection but also a crack that newly occurs during the inspection can be detected with high reliability. Further, since other steps such as ultrasonic flaw detection are not required for detecting cracks, it is possible to reduce the number of steps and the time required for the measurement step of the laminated ceramic capacitor 1.

一方、測定工程において、例えば電圧を一気に昇圧した場合は、積層セラミックコンデンサに流れる電流が制限電流値に達するため、その時点でクラックが生じたとしても、図５において観測されるような異常電流のピークは観測されない。電圧印加が開始する時間から電圧印加が終了する時間までの全区間において、積層セラミックコンデンサに流れる電流が制限電流値を下回ることが好ましい。   On the other hand, in the measurement process, for example, when the voltage is boosted at once, the current flowing through the multilayer ceramic capacitor reaches the limiting current value, so even if a crack occurs at that time, an abnormal current as observed in FIG. No peak is observed. In the entire section from the time when the voltage application starts to the time when the voltage application ends, it is preferable that the current flowing through the monolithic ceramic capacitor falls below the limiting current value.

なお、積層セラミックコンデンサ１にクラックが発生した場合に異常電流が流れる理由としては、定かではないが、クラックが発生した瞬間に積層セラミックコンデンサ１の性状が変化するためであると考えられる。   The reason why the abnormal current flows when a crack occurs in the monolithic ceramic capacitor 1 is not clear, but it is considered that the properties of the monolithic ceramic capacitor 1 change at the moment when the crack occurs.

本発明において、「異常電流」とは、測定工程において、良品である積層セラミックコンデンサに流れる電流の変化とは異なり、一時的な増大を示す電流のことである。「異常電流」は、例えば、積層セラミックコンデンサが良品である場合には検出されない電流のピーク（正電圧の場合は極大ピーク、負電圧の場合は極小ピーク）である。通常、「異常電流」は急峻なピークとして観測され、電流の増大が観測される時間は１〜３００μｓｅｃ程度である。この時間は、測定する積層セラミックコンデンサの静電容量などによって６０μｓｅｃ程度、１５０μｓｅｃ程度、２００μｓｅｃ程度などと変化する。   In the present invention, the “abnormal current” is a current that shows a temporary increase, unlike a change in the current flowing through a good quality laminated ceramic capacitor in the measurement process. The “abnormal current” is, for example, a peak of current that is not detected when the monolithic ceramic capacitor is a good product (a maximum peak when the voltage is positive, and a minimum peak when the voltage is negative). Usually, the "abnormal current" is observed as a steep peak, and the time when the increase in current is observed is about 1 to 300 µsec. This time changes to about 60 μsec, about 150 μsec, about 200 μsec, etc. depending on the capacitance of the multilayer ceramic capacitor to be measured.

本実施形態では、積層セラミックコンデンサ１に印加する電圧を漸増させた後ないし漸減させる前に、一定の電圧で保持する時間を設ける例について説明したが、図６に示されるように、電圧を漸増させた後に、直ちに電圧を漸減させてもよい。   In the present embodiment, an example in which the voltage applied to the monolithic ceramic capacitor 1 is held for a constant voltage after being gradually increased or before being gradually decreased has been described. However, as shown in FIG. 6, the voltage is gradually increased. The voltage may be gradually decreased immediately after the operation.

本実施形態では、電圧を漸増する速度、電圧を漸減する速度が、それぞれ一定である例について説明した。但し、本発明は、この構成に限定されない。例えば、図７及び図８に示されるように、電圧を漸増する速度、電圧を漸減する速度を、それぞれ変化させてもよい。図７及び図８に示す例では、電圧を漸増する速度を、時間と共に低くしている。図７に示す例では、電圧を漸減する速度を、時間と共に高くしている。図８に示す例では、電圧を漸減する速度を、時間と共に低くしている。   In this embodiment, the example in which the speed of gradually increasing the voltage and the speed of gradually decreasing the voltage are constant has been described. However, the present invention is not limited to this configuration. For example, as shown in FIGS. 7 and 8, the speed of gradually increasing the voltage and the speed of gradually decreasing the voltage may be changed. In the example shown in FIGS. 7 and 8, the rate of gradually increasing the voltage is lowered with time. In the example shown in FIG. 7, the speed of gradually decreasing the voltage is increased with time. In the example shown in FIG. 8, the speed at which the voltage is gradually reduced is lowered with time.

本実施形態では、電圧を漸増させた後に漸減させる例について説明したが、図９に示されるように、電圧を漸増させた後に、電圧を一気に低下させてもよい。また、電圧を一気に上昇させた後に、電圧を漸減してもよい。好ましくは、電圧を漸増させた後に漸減させる。   In the present embodiment, an example in which the voltage is gradually increased and then gradually decreased has been described. However, as shown in FIG. 9, the voltage may be gradually decreased after the voltage is gradually increased. Further, the voltage may be gradually decreased after the voltage is increased at once. Preferably, the voltage is gradually increased and then gradually decreased.

図１０に示されるように、定格電圧以下の電圧まで一気に昇圧した後に、電圧を漸増させ、その後、定格電圧以下の電圧まで漸減した後に、一気に電圧を低下させてもよい。このようにすることにより、クラックが発生する可能性の低い低電圧領域にかかる時間を縮め、測定工程の実施に要する時間を短縮することができる。   As shown in FIG. 10, the voltage may be boosted to a voltage equal to or lower than the rated voltage at once, then gradually increased, then gradually decreased to a voltage equal to or lower than the rated voltage, and then the voltage may be reduced at once. By doing so, it is possible to shorten the time required for the low voltage region where cracks are unlikely to occur and to shorten the time required for carrying out the measurement process.

図１１や図１２に示されるように、測定工程において、積層セラミックコンデンサ１に正電圧及び負電圧の一方を印加した後に、正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行ってもよい。例えば、正弦波状の電圧を積層セラミックコンデンサ１に印加してもよい。そうすることにより、積層セラミックコンデンサ１の検査中に新たに生じたクラックをさらに確実に検出することが可能となる。   As shown in FIG. 11 and FIG. 12, in the measurement step, after applying one of the positive voltage and the negative voltage to the monolithic ceramic capacitor 1, at least one cycle of applying the other of the positive voltage and the negative voltage is performed. Good. For example, a sinusoidal voltage may be applied to the monolithic ceramic capacitor 1. By doing so, it becomes possible to more reliably detect a crack newly generated during the inspection of the monolithic ceramic capacitor 1.

なお、積層セラミックコンデンサ１に流れる電流を測定する電流測定部と、異常電流を検出する異常電流検出部との間に、ＤＣカットフィルタ（ハイパスフィルタ）を配してもよい。そうすることにより、周波数の低い電流変化をカットすることができるため、異常電流の検出が容易となる。   A DC cut filter (high-pass filter) may be arranged between the current measuring unit that measures the current flowing through the monolithic ceramic capacitor 1 and the abnormal current detecting unit that detects the abnormal current. By doing so, it is possible to cut a current change having a low frequency, so that it becomes easy to detect an abnormal current.

１…積層セラミックコンデンサ
１０…セラミック素体
１０ａ…第１の主面
１０ｂ…第２の主面
１０ｃ…第１の側面
１０ｄ…第２の側面
１０ｅ…第１の端面
１０ｆ…第２の端面
１１，１２…内部電極
１３，１４…外部電極
１５…セラミック部 DESCRIPTION OF SYMBOLS 1 ... Multilayer ceramic capacitor 10 ... Ceramic element body 10a ... 1st main surface 10b ... 2nd main surface 10c ... 1st side surface 10d ... 2nd side surface 10e ... 1st end surface 10f ... 2nd end surface 11, 12 ... Internal electrodes 13, 14 ... External electrode 15 ... Ceramic part

Claims (6)

積層セラミックコンデンサに電圧を印加しながら、前記積層セラミックコンデンサに流れる電流値を測定する測定工程と、
前記測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程と、
を備え、
前記測定工程において、構造欠陥が存在しない場合に前記積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように前記積層セラミックコンデンサに電圧を印加する、積層セラミックコンデンサの検査方法。 While applying a voltage to the multilayer ceramic capacitor, a measurement step of measuring the current value flowing in the multilayer ceramic capacitor,
A determination step of determining that the multilayer ceramic capacitor in which an abnormal current is detected in the measurement step is abnormal,
Equipped with
A method for inspecting a monolithic ceramic capacitor, wherein in the measuring step, a voltage is applied to the monolithic ceramic capacitor such that a current flowing through the monolithic ceramic capacitor falls below a predetermined current value when no structural defect exists. 前記測定工程において、構造欠陥が存在しない場合に前記積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、前記積層セラミックコンデンサに印加する電圧を、前記積層セラミックコンデンサの定格電圧よりも高い電圧まで漸増させる、請求項１に記載の積層セラミックコンデンサの検査方法。   In the measuring step, the voltage applied to the monolithic ceramic capacitor is lower than the rated voltage of the monolithic ceramic capacitor so that the current flowing through the monolithic ceramic capacitor is lower than a predetermined current value when there is no structural defect. The method for inspecting a monolithic ceramic capacitor according to claim 1, wherein the voltage is gradually increased to a high voltage. 前記測定工程において、構造欠陥が存在しない場合に前記積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、前記積層セラミックコンデンサに印加する電圧を、前記積層セラミックコンデンサの定格電圧よりも高い電圧から定格電圧以下まで漸減させる、請求項１または２に記載の積層セラミックコンデンサの検査方法。   In the measuring step, the voltage applied to the monolithic ceramic capacitor is lower than the rated voltage of the monolithic ceramic capacitor so that the current flowing through the monolithic ceramic capacitor is lower than a predetermined current value when there is no structural defect. The method for inspecting a multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor is gradually reduced from a high voltage to a rated voltage or less. 前記測定工程において、前記積層セラミックコンデンサに印加する電圧を、前記積層セラミックコンデンサの定格電圧よりも高い電圧まで上昇させた後に、当該電圧で保持し、その後、前記積層セラミックコンデンサの定格電圧以下の電圧まで低下させる、請求項１〜３のいずれか一項に記載の積層セラミックコンデンサの検査方法。   In the measuring step, the voltage applied to the monolithic ceramic capacitor is raised to a voltage higher than the rated voltage of the monolithic ceramic capacitor and then held at the voltage, and then a voltage equal to or lower than the rated voltage of the monolithic ceramic capacitor. The method for inspecting a monolithic ceramic capacitor according to claim 1, wherein 前記測定工程において、前記積層セラミックコンデンサに正電圧及び負電圧の一方を印加した後に正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行う、請求項１〜４のいずれか一項に記載の積層セラミックコンデンサの検査方法。   5. In the measuring step, at least one cycle of applying one of a positive voltage and a negative voltage to the multilayer ceramic capacitor and then applying the other of the positive voltage and the negative voltage is performed. Inspection method for monolithic ceramic capacitors. 積層セラミックコンデンサを作製する工程と、
前記積層セラミックコンデンサに電圧を印加しながら、前記積層セラミックコンデンサに流れる電流値を測定する測定工程と、
前記測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程と、
を備え、
前記測定工程において、構造欠陥が存在しない場合に前記積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように前記積層セラミックコンデンサに電圧を印加する、積層セラミックコンデンサの製造方法。 A step of producing a monolithic ceramic capacitor,
While applying a voltage to the multilayer ceramic capacitor, a measurement step of measuring the current value flowing in the multilayer ceramic capacitor,
A determination step of determining that the multilayer ceramic capacitor in which an abnormal current is detected in the measurement step is abnormal,
Equipped with
In the measuring step, a method of manufacturing a laminated ceramic capacitor, wherein a voltage is applied to the laminated ceramic capacitor such that a current flowing through the laminated ceramic capacitor falls below a predetermined current value when no structural defect exists.
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