JP2000124088A - Method for sorting stacked ceramic capacitor - Google Patents

Method for sorting stacked ceramic capacitor

Info

Publication number
JP2000124088A
JP2000124088A JP10290331A JP29033198A JP2000124088A JP 2000124088 A JP2000124088 A JP 2000124088A JP 10290331 A JP10290331 A JP 10290331A JP 29033198 A JP29033198 A JP 29033198A JP 2000124088 A JP2000124088 A JP 2000124088A
Authority
JP
Japan
Prior art keywords
voltage
external electrodes
ceramic capacitor
multilayer ceramic
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10290331A
Other languages
Japanese (ja)
Inventor
Yukihito Yamashita
由起人 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10290331A priority Critical patent/JP2000124088A/en
Publication of JP2000124088A publication Critical patent/JP2000124088A/en
Pending legal-status Critical Current

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  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for sorting moducts having imperfect connections between the inner and outer electrodes of the stacked ceramic capacitors with good accuracy. SOLUTION: A stacked ceramic capacitor to be measured 1 has outer electrodes at both ends of a laminate so as to be electrically connected to inner electrodes. The laminate has dielectric ceramic layers and inner electrodes laminated alternately so that one side ends of the inner electrodes are alternately exposed at the facing opposite different faces sandwiching the dielectric ceramic layers. In the capacitor 1, (2) an a-c voltage is applied by at least two cycles between the outer electrodes and then (3) the outer electrodes are short-circuited to cause discharge of stored electric changes, and a capacitance sort step 4 follows to sort and remove the capacitor as a connection-imperfect product, if it has a low capacitance out of a fixed reference characteristic value range.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は積層セラミックコン
デンサの内部電極と外部電極間の接続不良品を選別する
積層セラミックコンデンサの選別方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of selecting a multilayer ceramic capacitor for selecting a defective connection between an internal electrode and an external electrode of the multilayer ceramic capacitor.

【0002】[0002]

【従来の技術】積層セラミックコンデンサの内部電極と
外部電極間の接続不良品の選別方法として特開平3−5
2212号公報、及び特開平9−330855号公報が
開示されている。
2. Description of the Related Art Japanese Patent Laid-Open Publication No. 3-5 / 1990 discloses a method for selecting a defective connection between an internal electrode and an external electrode of a multilayer ceramic capacitor.
No. 2212 and Japanese Patent Application Laid-Open No. 9-330855 are disclosed.

【0003】第一の特開平3−52212号公報に記載
の選別方法は、積層セラミックコンデンサを二つ以上の
異なる周波数帯で静電容量を測定し、各周波数帯におけ
る静電容量の比を求め、一定基準値範囲から外れるもの
を内部電極と外部電極間の接続不良品として選別除去す
るものである。
In the sorting method described in the first Japanese Patent Application Laid-Open No. 3-52212, the capacitance of a multilayer ceramic capacitor is measured in two or more different frequency bands, and the ratio of the capacitance in each frequency band is determined. In addition, those which are out of the predetermined reference value range are selectively removed as defective connection between the internal electrode and the external electrode.

【0004】第二の特開平9−330855号公報に記
載の選別方法は、積層セラミックコンデンサの外部電極
間に直流電圧を印加し、その時の漏洩電流波形の挙動変
化をとらえ、挙動が異常を示したものを一次選別除去
し、次に一次選別良品に対し静電容量を測定し基準特性
値範囲を外れるものを二次選別除去するものである。
In the sorting method described in the second Japanese Patent Application Laid-Open No. 9-330855, a DC voltage is applied between external electrodes of a multilayer ceramic capacitor, a change in the behavior of a leakage current waveform at that time is detected, and the behavior is abnormal. The product is first sorted and removed, and then the capacitance of the first sorted non-defective product is measured.

【0005】またその他に、積層セラミックコンデンサ
の内部電極と外部電極間の接続不良品は、一般に静電容
量値が設計値よりも小さくなることを利用し静電容量値
小を接続不良品として選別除去する方法も行われてい
る。
[0005] In addition, a defective connection between an internal electrode and an external electrode of a multilayer ceramic capacitor is generally selected as a defective connection by using the fact that the capacitance value is smaller than a design value by utilizing the fact that the capacitance value is smaller than a design value. A method of removing it has also been used.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、特開平
3−52212号公報の選別方法は、同一積層セラミッ
クコンデンサを異なる周波数帯で少なくとも2回以上の
測定を行い、測定周波数帯の静電容量値を1対1に対応
し、その比を求め選別するため非常に複雑となる。ま
た、特開平9−330855号公報の選別方法は、被測
定品の外部電極間に直流電圧を印加するため、外部電極
間に逆方向に電圧が印加された場合の異常をとらえるこ
とができない。
However, in the screening method disclosed in Japanese Patent Application Laid-Open No. 3-52212, the same multilayer ceramic capacitor is measured at least twice in different frequency bands, and the capacitance value in the measured frequency band is determined. One-to-one correspondence is required, and the ratio is determined and selected, which is very complicated. Further, in the sorting method disclosed in Japanese Patent Application Laid-Open No. 9-330855, a DC voltage is applied between the external electrodes of the device under test, so that it is not possible to detect abnormalities when a voltage is applied in the opposite direction between the external electrodes.

【0007】また、静電容量値小を内部電極と外部電極
の接続不良品としてとらえる方法は、接続不良品は静電
容量の測定値が不安定で、測定ごとに静電容量値が変動
し再現性が悪く、特性選別を数回繰り返しても完全に接
続不良品を除去できないという問題があった。
[0007] In addition, a method of treating a small capacitance value as a defective connection between the internal electrode and the external electrode is such that a defective connection has an unstable measured value of the capacitance, and the capacitance value fluctuates for each measurement. There is a problem that the reproducibility is poor and the defective connection cannot be completely removed even if the characteristic selection is repeated several times.

【0008】本発明は以上のような従来の欠点を除去
し、正確に特性選別できる積層セラミックコンデンサの
選別方法を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for selecting a multilayer ceramic capacitor which can eliminate the above-mentioned conventional drawbacks and can accurately select characteristics.

【0009】[0009]

【課題を解決するための手段】前記課題を解決するため
に本発明は、積層セラミックコンデンサの外部電極間に
正負の電圧を交互に印加した後、外部電極間を短絡し蓄
えられた電荷を放電させ、次に特性検査を行い、一定の
基準特性範囲から外れるものを選別除去する方法とした
ものである。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a multilayer ceramic capacitor in which positive and negative voltages are alternately applied between the external electrodes, and then the external electrodes are short-circuited to discharge the stored electric charge. Then, a characteristic inspection is performed, and a method of selecting and removing an object that is out of a predetermined reference characteristic range is adopted.

【0010】このように内部電極と外部電極間の接続が
不完全な箇所を放電破壊し所謂静電容量抜けの状態とし
た後、静電容量の測定で静電容量小の積層セラミックコ
ンデンサを確実に選別除去することができる。
In this way, after the portion where the connection between the internal electrode and the external electrode is incomplete is destroyed by discharge, so-called a state of missing capacitance, a multilayer ceramic capacitor having a small capacitance is surely measured by measuring the capacitance. Can be selectively removed.

【0011】[0011]

【発明の実施の形態】本発明の請求項1に記載の発明
は、誘電体セラミック層と内部電極とを交互に複数層積
層し、かつその内部電極の一方の端部を前記誘電体セラ
ミック層を挟んで対向する異なる端面に交互に露出させ
た積層体の両端面に内部電極と電気的に接続するように
形成した外部電極を備えた積層セラミックコンデンサに
おいて、前記外部電極間に正負の電圧を交互に印加した
後、外部電極間を短絡し蓄えられた電荷を放電させた後
に特性検査を行い、一定の基準特性値範囲から外れるも
のを選別除去する積層セラミックコンデンサの選別方法
である。外部電極間に正負の電圧を交互に印加すること
により、内部電極と外部電極間の接続不完全な箇所は確
実に放電破壊されるため、内部電極と外部電極との接続
不完全部分の誘電体セラミック層で形成される積層セラ
ミックコンデンサは外部電極との接続がされていないた
め所謂静電容量抜け状態となり、従ってその後の静電容
量の測定で、接続不完全な積層セラミックコンデンサは
確実に静電容量小となり選別除去することができ、また
外部電極間に正負の電圧を交互に印加することにより、
内部電極間に挟まれた誘電体セラミック層の絶縁抵抗が
劣化したものをその後の絶縁抵抗検査で選別除去される
という作用を有するものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a dielectric ceramic layer and an internal electrode are alternately laminated in a plurality of layers, and one end of the internal electrode is connected to the dielectric ceramic layer. In a multilayer ceramic capacitor having external electrodes formed so as to be electrically connected to the internal electrodes on both end surfaces of the laminate alternately exposed to different end surfaces opposed to each other with a positive and negative voltage between the external electrodes, This is a method for selecting a multilayer ceramic capacitor in which, after being alternately applied, a short circuit is caused between external electrodes to discharge a stored charge, a characteristic test is performed, and a capacitor out of a predetermined reference characteristic value range is selectively removed. By applying positive and negative voltages alternately between the external electrodes, the incomplete connection between the internal electrode and the external electrode is reliably destroyed by discharge. Since the multilayer ceramic capacitor formed of ceramic layers is not connected to an external electrode, the capacitor is in a so-called capacitance-loss state. It becomes small in capacity and can be selectively removed, and by alternately applying positive and negative voltages between external electrodes,
The dielectric ceramic layer sandwiched between the internal electrodes has a function of deteriorating the insulation resistance, and has a function of being selectively removed in a subsequent insulation resistance test.

【0012】本発明の請求項2に記載の発明は、外部電
極間に交流電圧を印加する請求項1に記載の積層セラミ
ックコンデンサの選別方法である。外部電極間に交流電
圧を印加すると、内部電極と外部電極間の接続不完全な
箇所は正方向、逆方向の電圧が印加され、接続不完全箇
所が確実に破壊されるため、その後の静電容量の測定で
積層セラミックコンデンサが静電容量小となり確実に選
別されるという作用を有するものである。
According to a second aspect of the present invention, there is provided the method for selecting a multilayer ceramic capacitor according to the first aspect, wherein an AC voltage is applied between external electrodes. When an AC voltage is applied between the external electrodes, a voltage in the forward and reverse directions is applied to a portion where the connection between the internal electrode and the external electrode is incomplete, and the portion where the connection is incomplete is destroyed without fail. This has the effect that the capacitance of the multilayer ceramic capacitor is small in the measurement of the capacitance and the capacitor is reliably selected.

【0013】本発明の請求項3に記載の発明は、外部電
極間に正弦波電圧を印加する請求項1または請求項2に
記載の積層セラミックコンデンサの選別方法である。外
部電極と内部電極間の接続不完全な箇所に正方向、逆方
向から電圧を印加し確実に放電破壊させるため確実に選
別できるものである。
According to a third aspect of the present invention, there is provided the method for selecting a multilayer ceramic capacitor according to the first or second aspect, wherein a sine wave voltage is applied between external electrodes. A voltage can be applied in a forward direction or a reverse direction to a portion where connection between the external electrode and the internal electrode is incomplete, and the discharge can be reliably destroyed.

【0014】本発明の請求項4に記載の発明は、外部電
極間に矩形波電圧を印加する請求項1または請求項2に
記載の積層セラミックコンデンサの選別方法である。こ
れにより内部電極と外部電極間の接続不完全な箇所に
は、正、負方向の最大値電圧を長時間保持できる矩形波
電圧が印加されるため、不完全な接続箇所を確実に破壊
することができ確実に選別できるものである。
According to a fourth aspect of the present invention, there is provided the method for selecting a multilayer ceramic capacitor according to the first or second aspect, wherein a rectangular wave voltage is applied between external electrodes. As a result, a rectangular wave voltage that can hold the maximum voltage in the positive and negative directions for a long time is applied to the incomplete connection between the internal electrode and the external electrode, so that the incomplete connection is reliably destroyed. Can be sorted out.

【0015】本発明の請求項5に記載の発明は、外部電
極間に二サイクル以上の電圧を印加する請求項1から請
求項4の何れか1つに記載の積層セラミックコンデンサ
の選別方法である。これにより内部電極と外部電極間の
接続不完全な箇所には、連続した正、負方向の電圧が二
回以上印加されるため、不完全な接続箇所をより確実に
破壊することができるという作用を有するものである。
According to a fifth aspect of the present invention, there is provided the method for selecting a multilayer ceramic capacitor according to any one of the first to fourth aspects, wherein a voltage of two cycles or more is applied between the external electrodes. . As a result, a continuous positive and negative voltage is applied twice or more to a portion where connection between the internal electrode and the external electrode is incomplete, so that the incomplete connection portion can be more reliably destroyed. It has.

【0016】本発明の請求項6に記載の発明は、外部電
極間に積層セラミックコンデンサの定格電圧より高い電
圧を印加する請求項1から請求項5の何れか1つに記載
の積層セラミックコンデンサの選別方法である。これに
より内部電極と外部電極間の接続不完全な箇所には積層
セラミックコンデンサの定格電圧以上の正、負方向の電
圧が印加されるため、不完全な接続箇所をより確実に破
壊すると共に、選別後の良品をその後定格電圧以下で使
用する際には、内部電極と外部電極間の接続不良に伴う
静電容量抜けを防止することが可能となるという作用を
有するものである。
According to a sixth aspect of the present invention, in the multilayer ceramic capacitor according to any one of the first to fifth aspects, a voltage higher than the rated voltage of the multilayer ceramic capacitor is applied between the external electrodes. It is a sorting method. As a result, a voltage in the positive and negative directions that is higher than the rated voltage of the multilayer ceramic capacitor is applied to the incomplete connection between the internal and external electrodes, so that the incomplete connection is more reliably destroyed and sorted. When a later non-defective product is used at a rated voltage or less, it has an effect that it is possible to prevent capacitance loss due to poor connection between the internal electrode and the external electrode.

【0017】本発明の請求項7に記載の発明は、恒湿中
で外部電極間に正負の電圧を交互に印加し、恒湿中で特
性検査を行う請求項1から請求項6の何れか1つに記載
の積層セラミックコンデンサの選別方法であり、これに
より、外部電極間に電圧を印加した際の、湿度の影響に
伴う外部電極間の表面リークを防止し、不完全な接続部
分に確実に電圧を印加し不完全箇所を確実に破壊すると
共に、静電容量を測定する際の温度変化の影響を受ける
ことなく、確実に静電容量を測定することが可能とな
る。
According to a seventh aspect of the present invention, the positive or negative voltage is alternately applied between the external electrodes in a constant humidity, and the characteristic inspection is performed in the constant humidity. (1) A method for selecting a multilayer ceramic capacitor according to (1), which prevents a surface leak between external electrodes due to the influence of humidity when a voltage is applied between external electrodes, and ensures a defective connection portion. Voltage is applied to the incomplete portion to reliably destroy the incomplete portion, and the capacitance can be reliably measured without being affected by a temperature change in measuring the capacitance.

【0018】本発明の請求項8に記載の発明は、積層セ
ラミックコンデンサを高温、低温槽中に交互に数サイク
ル所定時間保持した後、外部電極間に電圧を印加する請
求項1から請求項7の何れか1つに記載の積層セラミッ
クコンデンサの選別方法である。これにより内部電極と
外部電極間の不完全な接続箇所に、熱膨張と熱収縮の繰
返し応力を加え、その箇所を金属疲労させ外部電極間に
電圧を印加した際に、破壊し易くすることができるとい
う作用を有するものである。
According to an eighth aspect of the present invention, after the multilayer ceramic capacitor is alternately held in a high-temperature and low-temperature bath for several cycles for a predetermined time, a voltage is applied between the external electrodes. A method for selecting a multilayer ceramic capacitor according to any one of the above. In this way, repeated stress of thermal expansion and thermal contraction is applied to the imperfect connection between the internal electrode and the external electrode, so that the metal is fatigued at that point, and when a voltage is applied between the external electrodes, it can be easily broken. It has the effect of being able to.

【0019】本発明の請求項9に記載の発明は、最初に
積層セラミックコンデンサの静電容量を測定し一次不良
品を選別除去した後、次に一定の基準特性値範囲内の品
物に対し外部電極間に電圧を印加する請求項1から請求
項8の何れか1つに記載の積層セラミックコンデンサの
選別方法である。これにより内部電極と外部電極間の接
続が不完全で静電容量が規定の値に達しないものを予め
静電容量測定で選別除去し、次に接続が不完全でも静電
容量が規定の値に達しているものには正負の電圧の印加
で接続不完全な箇所を確実に破壊し、その後の静電容量
測定で確実に選別除去することが可能となるものであ
る。
According to a ninth aspect of the present invention, after first measuring the electrostatic capacitance of a multilayer ceramic capacitor and sorting out and removing a primary defective product, an external product within a predetermined reference characteristic value range is externally removed. The method for selecting a multilayer ceramic capacitor according to any one of claims 1 to 8, wherein a voltage is applied between the electrodes. In this way, if the connection between the internal electrode and the external electrode is incomplete and the capacitance does not reach the specified value, it is selected and removed in advance by capacitance measurement. In the case where the voltage has reached, the portion where connection is incomplete is surely destroyed by application of positive and negative voltages, and it can be surely removed by the subsequent capacitance measurement.

【0020】図1は本発明の一実施の形態の積層セラミ
ックコンデンサの選別方法、図2(a)は同交流電圧印
加の回路図、(b)は同交流電圧の波形図、(表1)は
本発明の実施の形態と従来の選別方法の選別効果の比較
を示す。図1、図2において、1は被測定物としての積
層セラミックコンデンサ、2は交流電圧印加工程、3は
放電工程、4は静電容量と誘電損失の測定工程、5は絶
縁抵抗測定工程、6は積層セラミックコンデンサ1に印
加する交流電圧波形、7は交流電圧を印加する回路図、
8はスイッチ、9は交流電圧電源である。
FIG. 1 shows a method of selecting a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 2A is a circuit diagram showing the application of the AC voltage, FIG. 2B is a waveform diagram of the AC voltage, and FIG. Shows a comparison of the sorting effect between the embodiment of the present invention and the conventional sorting method. 1 and 2, reference numeral 1 denotes a multilayer ceramic capacitor as an object to be measured, 2 denotes an AC voltage applying step, 3 denotes a discharging step, 4 denotes a measuring step of capacitance and dielectric loss, 5 denotes an insulating resistance measuring step, and 6 denotes an insulating resistance measuring step. Is a waveform of an AC voltage applied to the multilayer ceramic capacitor 1; 7 is a circuit diagram for applying an AC voltage;
Reference numeral 8 denotes a switch, and 9 denotes an AC voltage power supply.

【0021】[0021]

【表1】 [Table 1]

【0022】以上の工程フローでの積層セラミックコン
デンサの選別方法について説明する。
A method for selecting a multilayer ceramic capacitor in the above process flow will be described.

【0023】先ず、内部電極をNi、外部電極にCuを
用いた長さ2.0mm、幅1.25mm、厚さ0.65mm、
静電容量10nF、定格電圧50VのF特性の積層セラ
ミックコンデンサ1を400個準備し、その内の200
個について、図1に示す本発明の選別方法を用い、図2
に示す最大値が+300V、最小値が−300Vで一周
期が0.2秒の交流矩形波電圧を3サイクル外部電極間
に印加し、その直後、外部電極間を短絡し残留電荷を放
電させた後、静電容量、誘電損失及び絶縁抵抗を測定し
一次良品選別を行った。尚、良品選別範囲は、静電容量
=8〜18nF、誘電損失≦5.0%、絶縁抵抗≧1×
1010Ω。また静電容量と誘電損失の測定は1Vrmsの
電圧を印加し1kHzの周波数帯で、絶縁抵抗は定格50
(V)×1分値で行った。
First, Ni was used for the internal electrode and Cu was used for the external electrode. The length was 2.0 mm, the width was 1.25 mm, and the thickness was 0.65 mm.
400 multilayer ceramic capacitors 1 having an F-characteristic having a capacitance of 10 nF and a rated voltage of 50 V were prepared.
Using the sorting method of the present invention shown in FIG.
The AC rectangular wave voltage having a maximum value of +300 V, a minimum value of -300 V and a cycle of 0.2 seconds between the external electrodes was applied between the external electrodes for 3 cycles, and immediately thereafter, the external electrodes were short-circuited to discharge residual charges. Thereafter, the capacitance, the dielectric loss, and the insulation resistance were measured, and primary non-defective products were selected. The non-defective product selection range is as follows: capacitance = 8 to 18 nF, dielectric loss ≦ 5.0%, insulation resistance ≧ 1 ×
10 10 Ω. The capacitance and dielectric loss were measured at a frequency of 1 kHz by applying a voltage of 1 Vrms.
(V) × 1 minute value.

【0024】次に、残りの200個について従来方法の
静電容量、誘電損失及び絶縁抵抗を測定し、同様に一次
良品選別を行った。尚、良品範囲と各測定条件は本発明
の選別と同条件を用いた。
Next, the capacitance, dielectric loss and insulation resistance according to the conventional method were measured for the remaining 200 pieces, and the primary non-defective items were similarly selected. The non-defective range and each measurement condition were the same as those used in the selection of the present invention.

【0025】次いで、本発明の選別方法による良品と、
従来方法による良品について、二次選別、三次選別をそ
れぞれ一次選別と同じ条件、方法、選別範囲で行い、そ
れぞれの選別効果を確認し、その結果を(表1)に併せ
て示した。
Next, a non-defective product according to the screening method of the present invention,
Secondary screening and tertiary screening were performed under the same conditions, method, and screening range as those of the primary screening, and the effects of each screening were confirmed. The results are shown in Table 1 below.

【0026】(表1)に示すように、従来方法の一次選
別では8nF以下の静電容量不良(C小不良)が8個発
生し、誘電損失不良(DNG)と絶縁抵抗不良(IRN
G)は発生しなかった。続いて、一次選別の良品192
個について更に二次選別を行うと、C小不良が5個発生
し、DNG、IRNGは発生しなかった。続いて更に二
次選別の良品187個について三次選別を行うと、C小
不良が3個発生しDNGとIRNGは発生しなかった。
As shown in Table 1, in the primary screening of the conventional method, eight capacitance defects (small C defects) of 8 nF or less occur, and dielectric loss defects (DNG) and insulation resistance defects (IRN).
G) did not occur. Next, the primary sorting good products 192
When secondary sorting was further performed on the individual pieces, five small C defects occurred, and no DNG or IRNG occurred. Subsequently, tertiary sorting was performed on 187 non-defective products in secondary sorting, and three small C defects occurred, and neither DNG nor IRNG occurred.

【0027】従来の選別方法のC小不良品を、それぞれ
樹脂に埋め込み内部電極と直交するように側面から研磨
し、内部電極と外部電極の接続状態を確認したところ、
全てのC小不良品に接続不完全な箇所が確認された。
The small C defective products of the conventional sorting method were respectively buried in resin and polished from the side so as to be orthogonal to the internal electrodes, and the connection state between the internal electrodes and the external electrodes was confirmed.
Incomplete connection was confirmed in all of the small C defective products.

【0028】これに対し本発明の選別方法では、交流矩
形波を印加した後の一次選別では8nF以下のC小不良
が21個発生し、DNG,IRNGは発生しなかった。
続いて、一次選別良品179個について、更に二次選
別、続いて更に三次選別を行ったところ、C小不良、D
NG、IRNGは一切発生しなかった。
On the other hand, in the sorting method of the present invention, 21 small C defects of 8 nF or less occurred in the primary sorting after the application of the AC rectangular wave, and DNG and IRNG did not occur.
Next, 179 primary sorted good products were further subjected to secondary sorting, followed by tertiary sorting.
NG and IRNG did not occur at all.

【0029】一次選別でのC小不良の21個を樹脂に埋
め込み研磨し、内部電極と外部電極の接続状態を確認し
たところ、21個の全てに接続不完全な箇所が確認され
た。このことから本発明の選別方法では、交流矩形波を
外部電極間に3サイクル印加した後の一次選別で200
個中から21個の内部電極と外部電極間の接続不良品を
完全に選別除去することが可能となることが明らかとな
る。尚、一次、二次、三次選別でIRNGが発生してい
ないことから、交流矩形波を印加することで誘電体セラ
ミック層を絶縁破壊させないことがわかる。
[0029] Twenty-one small C defects in the primary sorting were buried in a resin and polished, and the connection state between the internal electrode and the external electrode was confirmed. From this, in the sorting method of the present invention, the first sorting after applying the AC square wave between the external electrodes for three cycles is performed.
It becomes clear that defective connection between the 21 internal electrodes and the external electrodes can be completely removed by screening. In addition, since no IRNG is generated in the primary, secondary, and tertiary sorting, it is understood that the dielectric ceramic layer does not cause dielectric breakdown by applying an AC rectangular wave.

【0030】次に図3に示す交流矩形波を外部電極間に
1サイクル印加した場合の選別効果について(表2)を
用いて説明する。
Next, the selection effect when the AC rectangular wave shown in FIG. 3 is applied between the external electrodes for one cycle will be described with reference to (Table 2).

【0031】[0031]

【表2】 [Table 2]

【0032】(表2)に示すように試料200個に、最
大値が+300V、最小値が−300Vで一周期が0.
2秒の交流矩形波電圧を1サイクル外部電極間に印加
し、その直後、外部電極間を短絡し残留電荷を放電させ
た後、静電容量、誘電損失及び絶縁抵抗を測定し一次良
品選別を行った。一次選別では8nF以下のC小不良が
10個発生し、DNG、IRNGは発生しなかった。続
いて、一次選別良品190個について更に二次選別を行
うと、8nF以下のC小不良が5個発生し、DNG、I
RNGは発生しなかった。
As shown in Table 2, for 200 samples, the maximum value is +300 V, the minimum value is -300 V, and one cycle is 0.
A 2-second AC rectangular wave voltage is applied between the external electrodes for one cycle. Immediately after that, the external electrodes are short-circuited to discharge residual charges. Then, the capacitance, dielectric loss and insulation resistance are measured, and the primary non-defective product is selected. went. In the primary screening, 10 small defects of 8 nF or less occurred, and neither DNG nor IRNG occurred. Subsequently, when secondary sorting was further performed on 190 primary sorted good products, five small C defects of 8 nF or less occurred, and DNG, I
RNG did not occur.

【0033】更に二次選別良品185個について三次選
別を行うと、8nF以下のC小不良が2個発生し、DN
G、IRNGは発生しなかった。一次、二次、三次選別
での各C小不良の10個、5個、2個を樹脂に埋め込み
研磨し、内部電極と外部電極の接続状態を確認したとこ
ろ、全てに接続不完全な箇所が確認された。このことか
ら交流矩形波を外部電極間に1サイクル印加しただけで
は、内部電極と外部電極間の接続不完全箇所を完全に放
電破壊し静電容量抜けの状態で選別除去することが不可
能であることが明らかとなる。
Further, when the 185 second-ordered non-defective products are tertiary-sorted, two small C defects of 8 nF or less occur, and DN
G and IRNG did not occur. After embedding and polishing 10 pieces, 5 pieces, and 2 pieces of each small C defect in the primary, secondary, and tertiary sorting in resin, and checking the connection state between the internal electrode and the external electrode, all of the incompletely connected portions were found. confirmed. For this reason, it is impossible to completely remove the incomplete connection between the internal electrode and the external electrode by simply applying an AC rectangular wave between the external electrodes for one cycle, and to selectively remove the defective electrode in a state where the capacitance is missing. It becomes clear that there is.

【0034】次に定格電圧以下の交流矩形波を外部電極
間に印加した場合の選別効果について図4と(表3)を
用いて説明する。
Next, the sorting effect when an AC rectangular wave having a voltage equal to or lower than the rated voltage is applied between the external electrodes will be described with reference to FIG. 4 and (Table 3).

【0035】[0035]

【表3】 [Table 3]

【0036】(表3)に示すように試料200個に、図
4に示す最大値が+25V、最小値が−25Vで一周期
が0.2秒の交流矩形波電圧を3サイクル外部電極間に
印加し、その直後、外部電極間を短絡し残留電荷を放電
させた後、静電容量、誘電損失及び絶縁抵抗を測定し一
次良品選別を行った。一次選別では8nF以下のC小不
良が6個発生し、DNG、IRNGは発生しなかった。
続いて、一次選別良品194個について、更に二次選別
を行うと、8nF以下のC小不良が4個発生し、DN
G、IRNGは発生しなかった。
As shown in Table 3, an AC rectangular wave voltage having a maximum value of +25 V, a minimum value of −25 V, and a cycle of 0.2 seconds shown in FIG. Immediately after that, the external electrodes were short-circuited to discharge residual charges, and then the capacitance, dielectric loss, and insulation resistance were measured, and primary non-defective products were selected. In the primary screening, 6 small defects of 8 nF or less occurred, and neither DNG nor IRNG occurred.
Subsequently, when the secondary sorting was further performed on 194 primary sorted good products, four small C defects of 8 nF or less occurred, and DN
G and IRNG did not occur.

【0037】更に二次選別良品190個について、三次
選別を行うと、8nF以下のC小不良が3個発生し、D
NG、IRNGは発生しなかった。一次、二次、三次選
別での各C小不良の6個、4個、3個を樹脂に埋め込み
研磨し、内部電極と外部電極の接続状態を確認したとこ
ろ、全てに接続不完全な箇所が確認された。これは一
次、二次、三次選別で絶縁抵抗を測定する時に定格電圧
である50Vを1分間印加したために、その影響で内部
電極と外部電極の接続不完全な箇所が放電破壊され、所
謂静電容量抜けの状態となり、C小不良が発生したもの
である。このことから定格電圧以下の交流矩形波を外部
電極間に印加した場合、内部電極と外部電極間の接続不
良品を完全に選別除去することが不可能であることが明
らかとなる。
Further, when tertiary sorting is performed on 190 good secondary sorting products, three small C defects of 8 nF or less occur, and
NG and IRNG did not occur. The primary, secondary, and tertiary sorting of each of the C small defects of 6, 4, and 3 were buried in resin and polished, and the connection state of the internal and external electrodes was confirmed. confirmed. This is because the rated voltage of 50 V was applied for 1 minute when measuring the insulation resistance in primary, secondary, and tertiary sorting, so that the incomplete connection between the internal electrode and the external electrode was destroyed by discharge. In this state, the capacity was lost, and a small C defect occurred. From this, it is clear that when an AC rectangular wave having a voltage equal to or lower than the rated voltage is applied between the external electrodes, it is impossible to completely remove the defective connection between the internal electrode and the external electrode.

【0038】次に高電圧の交流矩形波を外部電極間に印
加した場合の選別効果について図5と(表4)を用いて
説明する。
Next, the sorting effect when a high-voltage AC rectangular wave is applied between the external electrodes will be described with reference to FIG. 5 and (Table 4).

【0039】[0039]

【表4】 [Table 4]

【0040】(表4)に示すように試料200個に、図
5に示す最大値が+1000V、最小値が−1000V
で一周期が0.2秒の交流矩形波電圧を3サイクル外部
電極間に印加し、その直後、外部電極間を短絡し残留電
荷を放電させた後、静電容量、誘電損失及び絶縁抵抗を
測定し一次良品選別を行った。一次選別では8nF以下
のC小不良が22個発生し、IRNGが3個発生し、D
NGは発生しなかった。
As shown in Table 4, 200 samples had a maximum value of +1000 V and a minimum value of -1000 V shown in FIG.
Apply an AC rectangular wave voltage of 0.2 seconds per cycle between the external electrodes for 3 cycles, immediately thereafter, short-circuit the external electrodes to discharge the residual charge, and then change the capacitance, dielectric loss, and insulation resistance. The measurement was performed and the primary non-defective product was selected. In the primary selection, 22 small C defects of 8 nF or less are generated, 3 IRNGs are generated, and D
NG did not occur.

【0041】続いて、一次選別良品175個について更
に二次選別を行うと、8nF以下のC小不良とDNGは
発生しなかったが、IRNGが1個発生した。更に二次
選別良品174個について三次選別を行うと、8nF以
下のC小不良とDNGは発生しなかったが、IRNGが
1個発生した。一次選別での各C小不良の22個を樹脂
に埋め込み研磨し、内部電極と外部電極の接続状態を確
認したところ、全てに接続不完全な箇所が確認された。
同様に一次、二次、三次選別でのIRNG3個、1個、
1個を各々樹脂に埋め込み研磨しセラミック誘電体層を
確認したところ、高電圧印加に伴う絶縁破壊箇所が確認
された。これは1000Vの高電圧交流矩形波を外部電
極間に印加したためにセラミック誘電体層が絶縁破壊し
たものである。
Subsequently, when the secondary sorting was further performed on 175 primary sorting non-defective products, a small C defect of 8 nF or less and DNG did not occur, but one IRNG occurred. Further, when tertiary sorting was performed on 174 second-order non-defective products, a small C defect of 8 nF or less and DNG did not occur, but one IRNG occurred. When 22 pieces of each small C defect in the primary screening were buried in resin and polished, and the connection state between the internal electrode and the external electrode was confirmed, all of them were incompletely connected.
Similarly, three, one, and three IRNGs in primary, secondary, and tertiary sorting
When one of them was buried in a resin and polished to confirm the ceramic dielectric layer, a dielectric breakdown caused by application of a high voltage was confirmed. This is due to the dielectric breakdown of the ceramic dielectric layer due to the application of a high voltage AC rectangular wave of 1000 V between the external electrodes.

【0042】このことから高電圧の交流矩形波を外部電
極間に印加した場合は、内部電極と外部電極間の接続不
良品を選別除去することは可能であるが、高電圧印加に
伴いセラミック誘電体層が絶縁破壊を起こしIR不良品
を作るため、適切な選別方法とはならない。尚、請求項
6に記載の定格電圧より高い電圧とは、定格電圧の5〜
6倍程度の電圧であり、それ以上高い電圧を印加すると
セラミック誘電体層が絶縁破壊を起こし、それより低い
電圧では内部電極と外部電極間の接続不良品を完全に選
別除去することが不可能である。
From this fact, when a high-voltage AC rectangular wave is applied between the external electrodes, it is possible to selectively remove the defective connection between the internal electrode and the external electrode. Since the body layer causes dielectric breakdown and produces an IR defective product, it is not an appropriate sorting method. In addition, the voltage higher than the rated voltage according to claim 6 is 5 to 5 of the rated voltage.
The voltage is about 6 times, and when a higher voltage is applied, the dielectric breakdown of the ceramic dielectric layer occurs. At a lower voltage, defective connection between the internal and external electrodes cannot be completely removed. It is.

【0043】本実施の形態は、湿度が60〜65%の恒
湿中で外部電極間に矩形波電圧を印加したものであり、
これは湿度の影響に伴う外部電極間の表面リークを防止
し、内部電極と外部電極の接続が不完全な箇所に確実に
電圧を印加し不完全箇所を確実に破壊する効果をもたら
す。更に温度が20〜22℃の恒温中で静電容量を測定
したものであり、これは温度変化の影響を受けることな
く確実に静電容量を測定する効果をもたらす。
In this embodiment, a rectangular wave voltage is applied between external electrodes in a constant humidity of 60 to 65%.
This prevents surface leakage between the external electrodes due to the influence of humidity, and has the effect of reliably applying a voltage to a portion where the connection between the internal electrode and the external electrode is incomplete and destroying the incomplete portion. Further, the capacitance is measured at a constant temperature of 20 to 22 ° C., which has the effect of reliably measuring the capacitance without being affected by a temperature change.

【0044】次に冷熱サイクル実施後に交流矩形波を外
部電極間に印加した場合のスクリーニング効果について
図6と(表5)を用いて説明する。
Next, the screening effect when an AC rectangular wave is applied between the external electrodes after performing the cooling / heating cycle will be described with reference to FIG. 6 and (Table 5).

【0045】[0045]

【表5】 [Table 5]

【0046】(表5)に示すように試料200個に、図
6(a)に示す+20℃→+80℃→+25℃→−20
℃→+25℃の冷熱サイクルを3回繰り返した後、図6
(b)に示す最大値が+200V、最小値が−200V
で一周期が0.2秒の交流矩形波電圧を3サイクル外部
電極間に印加し、その直後、外部電極間を短絡し残留電
荷を放電させた後、静電容量、誘電損失及び絶縁抵抗を
測定し一次良品選別を行った。一次選別では8nF以下
のC小不良が22個発生し、DNG、IRNGは発生し
なかった。続いて、一次選別良品178個について、更
に二次選別を行うと、8nF以下のC小不良、DNG、
IRNGは発生しなかった。更に二次選別良品178個
について、三次選別を行うと、8nF以下のC小不良、
DNG、IRNGは発生しなかった。
As shown in (Table 5), 200 samples were subjected to + 20 ° C. → + 80 ° C. → + 25 ° C. → −20 shown in FIG.
After repeating the cooling / heating cycle of 30 ° C. → + 25 ° C. three times, FIG.
The maximum value shown in (b) is + 200V, and the minimum value is -200V.
Apply an AC rectangular wave voltage of 0.2 seconds per cycle between the external electrodes for 3 cycles, immediately thereafter, short-circuit the external electrodes to discharge the residual charge, and then change the capacitance, dielectric loss, and insulation resistance. The measurement was performed and the primary non-defective product was selected. In the primary sorting, 22 small defects of 8 nF or less occurred, and neither DNG nor IRNG occurred. Next, when 178 primary sorting good products were further subjected to secondary sorting, C small defects of 8 nF or less, DNG,
No IRNG occurred. Furthermore, when tertiary sorting is performed on 178 secondary sorting good products, a small C defect of 8 nF or less,
DNG and IRNG did not occur.

【0047】一次選別でのC小不良の22個を樹脂に埋
め込み研磨し、内部電極と外部電極の接続状態を確認し
たところ、全てに接続不完全な箇所が確認された。これ
により試料に冷熱サイクルを施し、内部電極と外部電極
間の不完全な接続箇所に熱膨張と熱収縮の繰返し応力を
加えその箇所を金属疲労させると破壊し易くなり、外部
電極間に定格電圧の3倍程度の交流矩形波電圧を印加し
た場合でも、内部電極と外部電極の接続不完全な箇所が
放電破壊され、所謂静電容量抜けの状態となり接続不良
品を確実に選別除去することが可能となる。
When 22 pieces of small C defects in the primary sorting were buried in resin and polished, and the connection state between the internal electrode and the external electrode was confirmed, all of them were incompletely connected. This allows the sample to be subjected to thermal cycling, applying repeated thermal expansion and contraction stresses to the incomplete connection between the internal electrode and the external electrode. Even when an AC rectangular wave voltage of about three times the applied voltage is applied, the incomplete connection between the internal electrode and the external electrode is destroyed by discharge, resulting in a so-called capacitance loss state, and the defective connection can be reliably removed. It becomes possible.

【0048】次に一次選別後に電圧を印加する効果につ
いて図7と(表6)を用いて説明する。
Next, the effect of applying a voltage after the primary sorting will be described with reference to FIG. 7 and (Table 6).

【0049】[0049]

【表6】 [Table 6]

【0050】(表6)に示すように試料200個の静電
容量、誘電損失、及び絶縁抵抗を測定し一次良品選別を
行った。一次選別では8nF以下のC小不良が3個発生
し、DNG、IRNGは発生しなかった。続いて、一次
選別の良品197個に図7に示す最大値が+300V、
最小値が−300Vで一周期が0.2秒の交流矩形波電
圧を3サイクル印加し、その直後、外部電極間を短絡し
残留電荷を放電させた後、静電容量、誘電損失、及び絶
縁抵抗を測定し二次良品選別を行うと8nF以下のC小
不良が17個発生し、DNG、IRNGは発生しなかっ
た。更に二次選別良品180個について、三次選別を行
うと、8nF以下のC小不良、DNG、IRNGは発生
しなかった。
As shown in Table 6, the capacitance, the dielectric loss, and the insulation resistance of 200 samples were measured, and primary non-defective products were selected. In the primary screening, three small defects of 8 nF or less occurred, and neither DNG nor IRNG occurred. Subsequently, the maximum value shown in FIG.
Three cycles of an AC rectangular wave voltage with a minimum value of -300V and a cycle of 0.2 seconds are applied, immediately after that, a short circuit is made between external electrodes to discharge residual charges, and then capacitance, dielectric loss, and insulation are applied. When the resistance was measured and the secondary non-defective product was selected, 17 small C defects of 8 nF or less were generated, and DNG and IRNG were not generated. Further, tertiary sorting of 180 secondary sorting good products did not produce small C defects, DNG and IRNG of 8 nF or less.

【0051】一次、二次選別での各C小不良の3個、1
7個を樹脂に埋め込み研磨し、内部電極と外部電極の接
続状態を確認したところ、全てに接続不完全な箇所が確
認された。すなわち最初に積層セラミックコンデンサを
一次選別し、静電容量良品のみに対し外部電極間に交流
矩形波電圧を印加する。これにより内部電極と外部電極
間の接続が不完全で静電容量が規定の値に達しないもの
を一次選別で予め除去し、次に接続が不完全でも静電容
量が規定の値に達しているものには交流矩形波電圧を印
加し接続不完全な箇所を完全に破壊し、その後の静電容
量測定で確実に選別除去することが可能となる。
In the primary and secondary sorting, three C small defects, 1
Seven were buried in resin and polished, and the connection state between the internal electrode and the external electrode was checked. As a result, incomplete connection was found in all of them. That is, first, the multilayer ceramic capacitor is firstly sorted, and an AC rectangular wave voltage is applied between the external electrodes only for the capacitors having good capacitance. In this way, the connection between the internal electrode and the external electrode is incomplete and the capacitance that does not reach the specified value is removed in advance by primary screening, and then the capacitance reaches the specified value even if the connection is incomplete. In such a case, an AC square wave voltage is applied to completely break a portion where connection is incomplete, and it is possible to surely remove the portion in a subsequent capacitance measurement.

【0052】以上の結果から従来の選別方法では、内部
電極と外部電極間の接続箇所が不安定な状態のまま静電
容量を測定するため、静電容量が測定ごとに変動し再現
性が悪く、接続不完全品を良品と判断し、また不良品と
判断したりする場合が発生する。このため内部電極、外
部電極間の接続不完全品を確実に選別除去することが不
可能であるのに対し、本発明の外部電極間に交流電圧を
印加することで内部電極と外部電極間の接続が不完全な
箇所を確実に放電破壊させた後に静電容量を測定する選
別方法では、内部電極と外部電極間の接続が不完全な誘
電体セラミック層で形成される積層セラミックコンデン
サは、外部電極との接続が断たれ所謂静電容量抜けの状
態となるため、その後の静電容量の測定で確実に静電容
量小となり、接続不良品を確実に選別除去することがで
きる。従って本発明の方法によれば信頼性の高い積層セ
ラミックコンデンサを提供することが可能となる。
From the above results, in the conventional selection method, since the capacitance is measured while the connection between the internal electrode and the external electrode is in an unstable state, the capacitance fluctuates for each measurement and the reproducibility is poor. In some cases, an incompletely connected product is determined as a non-defective product and a defective product is determined. For this reason, it is impossible to sort out and remove incompletely connected products between the internal electrode and the external electrode. On the other hand, by applying an AC voltage between the external electrodes according to the present invention, the connection between the internal electrode and the external electrode can be prevented. In the selection method of measuring the capacitance after reliably discharging and destroying the incompletely connected portion, the multilayer ceramic capacitor formed by the dielectric ceramic layer in which the connection between the internal electrode and the external electrode is incompletely connected is externally connected. Since the connection with the electrode is cut off, that is, a so-called capacitance loss state occurs, the capacitance is surely reduced in the subsequent measurement of the capacitance, and the defective connection can be surely removed. Therefore, according to the method of the present invention, a highly reliable multilayer ceramic capacitor can be provided.

【0053】[0053]

【発明の効果】以上のように本発明によれば、積層セラ
ミックコンデンサの外部電極間に正負の電圧を交互に印
加し、内部電極と外部電極間の接続が不完全な箇所を放
電破壊し、所謂静電容量抜けの状態とすることができ、
従ってその後の積層セラミックコンデンサの静電容量測
定により、内部電極、外部電極間の接続不完全品を静電
容量小として確実に選別することが可能となる。
As described above, according to the present invention, positive and negative voltages are alternately applied between the external electrodes of the multilayer ceramic capacitor, and the incomplete connection between the internal electrodes and the external electrodes is discharged and destroyed. It can be in a state of so-called capacitance loss,
Therefore, the incomplete connection between the internal electrode and the external electrode can be reliably selected as having a small capacitance by the subsequent measurement of the capacitance of the multilayer ceramic capacitor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態の積層セラミックコンデ
ンサの選別方法を示すフローチャート
FIG. 1 is a flowchart showing a method for selecting a multilayer ceramic capacitor according to an embodiment of the present invention.

【図2】(a)同実施の形態の交流電圧を印加する回路
図 (b)同交流電圧の電圧波形図
FIG. 2A is a circuit diagram for applying an AC voltage according to the embodiment; FIG. 2B is a voltage waveform diagram of the AC voltage;

【図3】矩形波を1サイクル印加する時の電圧波形図FIG. 3 is a voltage waveform diagram when a rectangular wave is applied for one cycle.

【図4】定格電圧以下の矩形波を印加する時の電圧波形
FIG. 4 is a voltage waveform diagram when a rectangular wave of a rated voltage or less is applied.

【図5】高電圧の矩形波を印加する時の電圧波形図FIG. 5 is a voltage waveform diagram when a high-voltage rectangular wave is applied.

【図6】(a)冷熱サイクルを示す説明図 (b)同矩形波を印加する時の電圧波形図FIG. 6A is an explanatory diagram showing a cooling / heating cycle. FIG. 6B is a voltage waveform diagram when the rectangular wave is applied.

【図7】一次選別後に矩形波を印加する時の電圧波形図FIG. 7 is a voltage waveform diagram when a rectangular wave is applied after primary sorting.

【符号の説明】[Explanation of symbols]

1 被測定物 2 交流電圧印加工程 3 放電工程 4 静電容量と誘電損失の測定工程 5 絶縁抵抗測定工程 6 交流電圧波形 7 交流電圧を印加する回路図 8 スイッチ 9 交流電圧電源 DESCRIPTION OF SYMBOLS 1 DUT 2 AC voltage application process 3 Discharge process 4 Measurement process of capacitance and dielectric loss 5 Insulation resistance measurement process 6 AC voltage waveform 7 Circuit diagram of applying AC voltage 8 Switch 9 AC voltage power supply

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 誘電体セラミック層と内部電極とを交互
に複数層積層し、かつその内部電極の一方の端部を前記
誘電体セラミック層を挟んで対向する異なる端面に交互
に露出させた積層体の両端面に内部電極と電気的に接続
するように形成した外部電極を備えた積層セラミックコ
ンデンサにおいて、前記外部電極間に正負の電圧を交互
に印加した後、外部電極間を短絡し蓄えられた電荷を放
電させた後に特性検査を行い、一定の基準特性値範囲か
ら外れるものを選別除去する積層セラミックコンデンサ
の選別方法。
1. A lamination in which a plurality of dielectric ceramic layers and internal electrodes are alternately laminated, and one end of the internal electrodes is alternately exposed to different end faces opposed to each other with the dielectric ceramic layer interposed therebetween. In a multilayer ceramic capacitor having external electrodes formed on both end surfaces of the body so as to be electrically connected to internal electrodes, after alternately applying positive and negative voltages between the external electrodes, the external electrodes are short-circuited and stored. A method for selecting a multilayer ceramic capacitor in which a characteristic test is performed after discharging discharged electric charges, and those that are out of a predetermined reference characteristic value range are selectively removed.
【請求項2】 外部電極間に交流電圧を印加する請求項
1に記載の積層セラミックコンデンサの選別方法。
2. The method according to claim 1, wherein an AC voltage is applied between the external electrodes.
【請求項3】 外部電極間に正弦波電圧を印加する請求
項1または請求項2に記載の積層セラミックコンデンサ
の選別方法。
3. The method for selecting a multilayer ceramic capacitor according to claim 1, wherein a sine wave voltage is applied between the external electrodes.
【請求項4】 外部電極間に矩形波電圧を印加する請求
項1または請求項2に記載の積層セラミックコンデンサ
の選別方法。
4. The method according to claim 1, wherein a rectangular wave voltage is applied between the external electrodes.
【請求項5】 外部電極間に二サイクル以上の電圧を印
加する請求項1から請求項4の何れか1つに記載の積層
セラミックコンデンサの選別方法。
5. The method for selecting a multilayer ceramic capacitor according to claim 1, wherein a voltage of two cycles or more is applied between the external electrodes.
【請求項6】 外部電極間に積層セラミックコンデンサ
の定格電圧より高い電圧を印加する請求項1から請求項
5の何れか1つに記載の積層セラミックコンデンサの選
別方法。
6. The method for selecting a multilayer ceramic capacitor according to claim 1, wherein a voltage higher than the rated voltage of the multilayer ceramic capacitor is applied between the external electrodes.
【請求項7】 恒湿中で外部電極間に正負の電圧を交互
に印加し、恒湿中で特性検査を行う請求項1から請求項
6の何れか1つに記載の積層セラミックコンデンサの選
別方法。
7. The multi-layer ceramic capacitor according to claim 1, wherein positive and negative voltages are alternately applied between the external electrodes during the constant humidity to perform a characteristic test under the constant humidity. Method.
【請求項8】 積層セラミックコンデンサを高温、低温
槽中に交互に数サイクル所定時間保持した後、外部電極
間に電圧を印加する請求項1から請求項7の何れか1つ
に記載の積層セラミックコンデンサの選別方法。
8. The multilayer ceramic according to claim 1, wherein the multilayer ceramic capacitor is alternately held in a high-temperature and low-temperature bath for several cycles for a predetermined time, and then a voltage is applied between external electrodes. How to sort capacitors.
【請求項9】 最初に積層セラミックコンデンサの静電
容量を測定し一次不良品を選別除去した後、次に一定の
基準特性値範囲内のものに対し外部電極間に電圧を印加
する請求項1から請求項8の何れか1つに記載の積層セ
ラミックコンデンサの選別方法。
9. The method according to claim 1, wherein the capacitance of the multilayer ceramic capacitor is measured first to sort out and remove primary defective products, and then a voltage is applied between the external electrodes for those within a certain reference characteristic value range. The method for selecting a multilayer ceramic capacitor according to any one of claims 1 to 8.
JP10290331A 1998-10-13 1998-10-13 Method for sorting stacked ceramic capacitor Pending JP2000124088A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10290331A JP2000124088A (en) 1998-10-13 1998-10-13 Method for sorting stacked ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10290331A JP2000124088A (en) 1998-10-13 1998-10-13 Method for sorting stacked ceramic capacitor

Publications (1)

Publication Number Publication Date
JP2000124088A true JP2000124088A (en) 2000-04-28

Family

ID=17754695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10290331A Pending JP2000124088A (en) 1998-10-13 1998-10-13 Method for sorting stacked ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2000124088A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199168A (en) * 2009-02-24 2010-09-09 Murata Mfg Co Ltd Method of manufacturing ceramic capacitor
JP2019212843A (en) * 2018-06-07 2019-12-12 株式会社村田製作所 Quality determination method of multilayer ceramic capacitor
KR20200043279A (en) * 2018-10-17 2020-04-27 가부시키가이샤 무라타 세이사쿠쇼 Method for inspecting multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199168A (en) * 2009-02-24 2010-09-09 Murata Mfg Co Ltd Method of manufacturing ceramic capacitor
JP2019212843A (en) * 2018-06-07 2019-12-12 株式会社村田製作所 Quality determination method of multilayer ceramic capacitor
JP7127369B2 (en) 2018-06-07 2022-08-30 株式会社村田製作所 Determination method for quality of multilayer ceramic capacitors
KR20200043279A (en) * 2018-10-17 2020-04-27 가부시키가이샤 무라타 세이사쿠쇼 Method for inspecting multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor
KR102253401B1 (en) * 2018-10-17 2021-05-18 가부시키가이샤 무라타 세이사쿠쇼 Method for inspecting multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

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