JP2020043242A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 74
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Abstract
Description
実施の形態1にかかる半導体装置は、シリコン(Si)よりもバンドギャップが広い半導体(ワイドバンドギャップ半導体とする)を用いて構成される。この実施の形態1にかかる半導体装置の構造について、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた場合を例に説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。図1には、図2の切断線A−A’における断面構造を示す。図2は、図1を半導体基板30のおもて面側から見たレイアウトを示す平面図である。また、図1,2には、MOSFETの1つの単位セル(素子の構成単位)と、当該単位セルの両側にそれぞれ隣接する他の単位セルの1/2と、を示す(図3〜13においても同様)。
次に、実施の形態2にかかる半導体装置の構造について説明する。図9は、実施の形態2にかかる半導体装置の構造を示す断面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、ゲート絶縁膜8の、ゲート電極9と導電層21との間の部分の厚さt2を、トレンチ7の一方の側壁7aに沿った部分の厚さt1よりも厚くした点である。
次に、実施の形態3にかかる半導体装置の構造について説明する。図10は、実施の形態3にかかる半導体装置の構造を示す断面図である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、トレンチ7’の底面7cに、一方の側壁7a側の底面7c−1を他方の側壁7b側の底面7c−2よりも深くした段差7fを設けた点である。
次に、実施の形態4にかかる半導体装置の構造について説明する。図11は、実施の形態4にかかる半導体装置の構造を示す断面図である。図12は、実施の形態4にかかる半導体装置の別の一例の構造を示す断面図である。実施の形態4にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、トレンチ7の各底面コーナー部7d,7eともにp+型領域22’で覆われている点である(図11参照)。
次に、実施の形態5にかかる半導体装置の構造について説明する。図13は、実施の形態5にかかる半導体装置の構造を示す断面図である。実施の形態5にかかる半導体装置が図11に示す実施の形態4にかかる半導体装置と異なる点は、トレンチ側壁SBD20を構成する導電層21’を、トレンチ7の他方の側壁7bおよび底面7cに沿って、トレンチ7の他方の側壁7bから一方の側壁7a側の底面コーナー部7dにわたるように設けた点である。すなわち、導電層21’は、トレンチ7の他方の側壁7bから、トレンチ7の底面7cとゲート絶縁膜8’との間に延在している。
2 n-型ドリフト領域
3 n型電流拡散領域
3a,3b n型部分領域
4 p型ベース領域
5 n+型ソース領域
6 p++型コンタクト領域
7 トレンチ
7a,7b トレンチの側壁
7c,7c−1,7c−2 トレンチの底面
7d,7e,7g トレンチの底面コーナー部
7f トレンチの底面の段差
8,8’ ゲート絶縁膜
9,9’ ゲート電極
10 層間絶縁膜
10a コンタクトホール
11 ソース電極
12 ドレイン電極
20 トレンチ側壁SBD
21,21' 導電層
22,22' p+型領域
30 半導体基板
31 n-型炭化珪素層
32 p型炭化珪素層
B MOSFETの単位セル
X 半導体基板のおもて面に平行な方向(第1方向)
Y 半導体基板のおもて面に平行で、かつ第1方向と直交する方向(第2方向)
Z 深さ方向
Claims (6)
- シリコンよりもバンドギャップの広い半導体からなる半導体基板と、
前記半導体基板のおもて面に設けられた、シリコンよりもバンドギャップの広い半導体からなる第1導電型の第1半導体層と、
前記第1半導体層の、前記半導体基板側に対して反対側に設けられた、シリコンよりもバンドギャップの広い半導体からなる第2導電型の第2半導体層と、
前記第2半導体層の内部に選択的に設けられた第1導電型の第1半導体領域と、
前記第2半導体層の内部に選択的に設けられ、前記半導体基板のおもて面に平行な方向に前記第1半導体領域と接する、前記第2半導体層よりも不純物濃度の高い第2導電型の第2半導体領域と、
前記第2半導体層の、前記第1半導体領域および前記第2半導体領域以外の部分であり、前記第1半導体領域および前記第2半導体領域よりも前記半導体基板側に配置された第2導電型の第3半導体領域と、
前記第1半導体領域と前記第2半導体領域との境界において、前記第1半導体領域、前記第2半導体領域および前記第3半導体領域を貫通して前記第1半導体層に達するトレンチと、
前記トレンチの一方の側壁および底面に沿って設けられたゲート絶縁膜と、
前記トレンチの一方の側壁の表面に前記ゲート絶縁膜を介して設けられ、前記第3半導体領域の、前記第1半導体領域と前記第1半導体層とに挟まれた部分に対向するゲート電極と、
前記トレンチの他方の側壁に沿って設けられ、前記トレンチの他方の側壁において前記第2半導体領域、前記第3半導体領域および前記第1半導体層とショットキー接触またはヘテロ接触する電極層と、
前記第1半導体層の内部に、前記第3半導体領域と離して設けられ、前記トレンチの他方の側壁と底面との境界を覆う第2導電型の第4半導体領域と、
前記第1半導体領域、前記第2半導体領域、前記第4半導体領域および前記電極層に電気的に接続された第1電極と、
前記半導体基板の裏面に設けられた第2電極と、
を備えることを特徴とする半導体装置。 - 前記ゲート絶縁膜は、前記ゲート電極と前記電極層との間に延在し、前記ゲート電極と前記電極層とを電気的に絶縁することを特徴とする請求項1に記載の半導体装置。
- 前記ゲート絶縁膜の、前記ゲート電極と前記電極層との間の部分の厚さは、前記ゲート絶縁膜の、前記トレンチの一方の側壁に沿った部分の厚さよりも厚いことを特徴とする請求項1または2に記載の半導体装置。
- 前記トレンチの底面に、一方の側壁側の底面を他方の側壁側の底面よりも深くした段差を有し、
前記第4半導体領域は、前記トレンチの一方の側壁側の底面と他方の側壁側の底面との連結部と、前記トレンチの一方の側壁側の底面と、の境界を覆うことを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。 - 前記第4半導体領域は、前記トレンチの一方の側壁と底面との境界から前記トレンチの他方の側壁と底面との境界にわたって、前記トレンチの底面を覆うことを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。
- 前記電極層は、前記トレンチの他方の側壁から、前記トレンチの底面と前記ゲート絶縁膜との間に延在していることを特徴とする請求項5に記載の半導体装置。
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