JP2019522376A5 - - Google Patents

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Publication number
JP2019522376A5
JP2019522376A5 JP2019503414A JP2019503414A JP2019522376A5 JP 2019522376 A5 JP2019522376 A5 JP 2019522376A5 JP 2019503414 A JP2019503414 A JP 2019503414A JP 2019503414 A JP2019503414 A JP 2019503414A JP 2019522376 A5 JP2019522376 A5 JP 2019522376A5
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JP
Japan
Prior art keywords
aspect ratio
high aspect
voltage rail
width
ratio voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019503414A
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English (en)
Japanese (ja)
Other versions
JP6985366B2 (ja
JP2019522376A (ja
Filing date
Publication date
Priority claimed from US15/634,039 external-priority patent/US10090244B2/en
Application filed filed Critical
Publication of JP2019522376A publication Critical patent/JP2019522376A/ja
Publication of JP2019522376A5 publication Critical patent/JP2019522376A5/ja
Application granted granted Critical
Publication of JP6985366B2 publication Critical patent/JP6985366B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2019503414A 2016-07-27 2017-06-29 低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路 Active JP6985366B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662367230P 2016-07-27 2016-07-27
US62/367,230 2016-07-27
US15/634,039 2017-06-27
US15/634,039 US10090244B2 (en) 2016-07-27 2017-06-27 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
PCT/US2017/039870 WO2018022244A1 (en) 2016-07-27 2017-06-29 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Publications (3)

Publication Number Publication Date
JP2019522376A JP2019522376A (ja) 2019-08-08
JP2019522376A5 true JP2019522376A5 (enExample) 2020-07-27
JP6985366B2 JP6985366B2 (ja) 2021-12-22

Family

ID=61010100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019503414A Active JP6985366B2 (ja) 2016-07-27 2017-06-29 低減された抵抗のために高アスペクト比電圧レールを採用する標準セル回路

Country Status (9)

Country Link
US (1) US10090244B2 (enExample)
EP (1) EP3491668B1 (enExample)
JP (1) JP6985366B2 (enExample)
KR (2) KR102693848B1 (enExample)
CN (2) CN118039636A (enExample)
BR (1) BR112019001429B1 (enExample)
SG (1) SG11201810982UA (enExample)
TW (1) TWI742103B (enExample)
WO (1) WO2018022244A1 (enExample)

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* Cited by examiner, † Cited by third party
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US11017146B2 (en) * 2018-07-16 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of forming the same
EP3723127A1 (en) 2019-04-10 2020-10-14 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US11444029B2 (en) 2020-02-24 2022-09-13 International Business Machines Corporation Back-end-of-line interconnect structures with varying aspect ratios
US11290109B1 (en) * 2020-09-23 2022-03-29 Qualcomm Incorporated Multibit multi-height cell to improve pin accessibility
US11778803B2 (en) * 2021-09-29 2023-10-03 Advanced Micro Devices, Inc. Cross FET SRAM cell layout
US12482746B2 (en) 2021-10-22 2025-11-25 International Business Machines Corporation Early backside first power delivery network

Family Cites Families (24)

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Publication number Priority date Publication date Assignee Title
JP3917683B2 (ja) * 1996-04-25 2007-05-23 株式会社ルネサステクノロジ 半導体集積回路装置
US6838713B1 (en) 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
US6483131B1 (en) 2000-01-11 2002-11-19 Texas Instruments Incorporated High density and high speed cell array architecture
JP2002110805A (ja) 2000-09-28 2002-04-12 Toshiba Corp 半導体デバイス
JP2003303885A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 集積回路及びその設計方法
JP2004039724A (ja) * 2002-07-01 2004-02-05 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005136060A (ja) * 2003-10-29 2005-05-26 Yamaha Corp 半導体装置及びその製造方法
US9009641B2 (en) * 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
CN100559576C (zh) * 2006-10-24 2009-11-11 株式会社电装 半导体器件
JP4535136B2 (ja) * 2008-01-17 2010-09-01 ソニー株式会社 半導体集積回路、および、スイッチの配置配線方法
US8102059B2 (en) * 2008-03-15 2012-01-24 Kabushiki Kaisha Toshiba Interconnect structure for high frequency signal transmissions
JP2009260158A (ja) * 2008-04-21 2009-11-05 Toshiba Corp 半導体集積回路装置における配線方法及び半導体集積回路装置
US7821039B2 (en) 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance
JP2011082223A (ja) * 2009-10-02 2011-04-21 Renesas Electronics Corp 半導体集積回路装置
US8212321B2 (en) * 2009-10-30 2012-07-03 Freescale Semiconductor, Inc. Semiconductor device with feedback control
US8336018B2 (en) 2010-06-09 2012-12-18 Lsi Corporation Power grid optimization
JP2012039073A (ja) * 2010-07-13 2012-02-23 Renesas Electronics Corp 半導体装置
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US9026977B2 (en) 2013-08-16 2015-05-05 Globalfoundries Inc. Power rail layout for dense standard cell library
US9070552B1 (en) 2014-05-01 2015-06-30 Qualcomm Incorporated Adaptive standard cell architecture and layout techniques for low area digital SoC
US9887209B2 (en) * 2014-05-15 2018-02-06 Qualcomm Incorporated Standard cell architecture with M1 layer unidirectional routing
KR102310122B1 (ko) * 2014-06-10 2021-10-08 삼성전자주식회사 논리 셀 및 이를 포함하는 집적회로 소자와 논리 셀의 제조 방법 및 집적회로 소자의 제조 방법
US9337149B2 (en) * 2014-07-29 2016-05-10 Samsung Electronics Co, Ltd. Semiconductor devices and methods of fabricating the same
US10510688B2 (en) * 2015-10-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Via rail solution for high power electromigration

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