JP2019511803A - 抵抗変化型メモリ(rram)セルフィラメントを形成するためのマルチステップ電圧 - Google Patents
抵抗変化型メモリ(rram)セルフィラメントを形成するためのマルチステップ電圧 Download PDFInfo
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- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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Abstract
Description
本願は、2016年3月4日に出願され、「Multi−Step Voltage For Forming Resistive Random Access Memory(RRAM)Cell Filament」と題する星国特許出願第10201601703U号に対する優先権を主張し、その内容は、参照により本明細書に組み込まれる。
Claims (32)
- 第1の導電性電極と第2の導電性電極との間に配設され、前記第1の導電性電極及び前記第2の導電性電極と電気的に接続している金属酸化物材料中に導電性フィラメントを形成する方法であって、前記方法は、
正しいテンポで離間された複数の電圧パルスを前記第1の導電性電極と前記第2の導電性電極との間に印加することを含み、
前記電圧パルスの各々に関して、電圧の振幅が前記電圧パルスの間に増加する、方法。 - 前記電圧パルスの各々に関して、電圧の振幅の最大値が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの電圧の振幅も上回る、請求項1に記載の方法。
- 前記電圧パルスの各々に関して、
前記電圧パルスの間、前記第1の導電性電極と前記第2の導電性電極との間に印加される電流を電流限界に制限することを更に含む、請求項1に記載の方法。 - 前記電圧パルスの各々に関して、前記電流限界が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの電流限界も上回る、請求項3に記載の方法。
- 前記電圧パルスの各々に関して、直後の電圧パルスの前記電流限界が、乗数で乗じた分前記1つの電圧パルスの前記電流限界よりも大きい、請求項4に記載の方法。
- 前記電圧パルスの各々に関して、前記電圧の前記振幅が、離散的なステップで増加する、請求項1に記載の方法。
- 前記電圧パルスの各々に関して、前記離散的なステップの数が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの離散的なステップの数も上回る、請求項6に記載の方法。
- 前記電圧パルスの各々に関して、前記1つの電圧パルスの継続時間が、前記1つのパルスに先行する前記複数の電圧パルスのいずれかの継続時間も上回る、請求項1に記載の方法。
- 前記複数の電圧パルスの全てが、同じ継続時間を有する、請求項1に記載の方法。
- 前記電圧パルスの各々に関して、前記電圧の前記振幅が、漸増する、請求項1に記載の方法。
- 前記電圧パルスの各々に関して、前記電圧の振幅の前記漸増が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの漸増も上回る割合である、請求項10に記載の方法。
- 前記電圧パルスの各々に関して、前記電圧の振幅の前記漸増が、前記複数の電圧パルスの他の全ての漸増と同じ割合である、請求項10に記載の方法。
- 前記電圧パルスの各々に関して、前記1つの電圧パルスが、前記1つの電圧パルスの直前の前記複数の電圧パルスのいずれかの終了電圧の振幅とも等しい開始電圧の振幅を有する、請求項2に記載の方法。
- 前記電圧パルスの各々が、逆極性の電圧で終了する、請求項1に記載の方法。
- 前記複数の電圧パルスの各々の後で、前記金属酸化物材料の抵抗を測定することと、
前記測定された抵抗が所定の閾値未満であることに応答して、前記電圧パルスの前記印加を停止することと、を更に含む、請求項1に記載の方法。 - 前記電圧パルスのうちの1つの間の前記第1の導電性電極と前記第2の導電性電極との間に印加された電流が所定の値を上回ったことに応答して、前記電圧パルスの前記印加を停止すること、を更に含む、請求項1に記載の方法。
- 第1の導電性電極と第2の導電性電極との間に配設され、前記第1の導電性電極及び前記第2の導電性電極と電気的に接続している金属酸化物材料と、
正しいテンポで離間された複数の電圧パルスを前記第1の導電性電極と前記第2の導電性電極との間に印加するように構成された電圧源と、を含み
前記電圧パルスの各々に関して、電圧の振幅が、前記電圧パルスの間増加する、メモリデバイス。 - 前記電圧パルスの各々に関して、前記振幅の最大値が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの振幅の最大値も上回る、請求項17に記載のメモリデバイス。
- 前記電圧源が、前記電圧パルスの各々に関して、前記電圧パルスの間、前記第1の導電性電極と前記第2の導電性電極との間に印加された電流を電流限界に制限するように更に構成されている、請求項17に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記電流限界が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの電流限界も上回る、請求項19に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、直後の電圧パルスの前記電流限界が、乗数で乗じた分前記1つの電圧パルスの電流限界よりも大きい、請求項20に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記電圧の前記振幅が、離散的なステップで増加する、請求項17に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記離散的なステップの数が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの離散的なステップの数も上回る、請求項22に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記1つの電圧パルスの継続時間が、前記1つのパルスに先行する前記複数の電圧パルスのいずれかの継続時間も上回る、請求項17に記載のメモリデバイス。
- 前記複数の電圧パルスの全てが、同じ継続時間を有する、請求項17に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記電圧の前記振幅が、漸増する、請求項17に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記電圧の振幅の前記漸増が、前記1つの電圧パルスに先行する前記複数の電圧パルスのいずれかの漸増も上回る割合である、請求項26に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記電圧の振幅の前記漸増が、前記複数の電圧パルスの他の全ての漸増と同じ割合である、請求項26に記載のメモリデバイス。
- 前記電圧パルスの各々に関して、前記1つの電圧パルスは、前記1つの電圧パルスの直前の前記複数の電圧パルスのいずれの終了電圧の振幅とも等しい開始電圧の振幅を有する、請求項18に記載のメモリデバイス。
- 前記電圧パルスの各々が、逆極性の電圧で終了する、請求項17に記載のメモリデバイス。
- 前記複数の電圧パルスの各々の後に、前記金属酸化物材料の抵抗を測定するための抵抗検出器、を更に含み、前記電圧源は、前記測定された抵抗が所定の閾値未満であることに応答して、前記電圧パルスの前記印加を停止するように構成されている、請求項17に記載のメモリデバイス。
- 前記電圧源は、前記電圧パルスのうちの1つの間、前記第1の導電性電極と前記第2の導電性電極との間に印加された電流が所定の値を上回ったことに応答して、前記電圧パルスの前記印加を停止するように構成されている、請求項17に記載のメモリデバイス。
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SG10201601703UA SG10201601703UA (en) | 2016-03-04 | 2016-03-04 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
SG10201601703U | 2016-03-04 | ||
US15/404,087 US9959927B2 (en) | 2016-03-04 | 2017-01-11 | Multi-step voltage for forming resistive access memory (RRAM) cell filament |
US15/404,087 | 2017-01-11 | ||
PCT/US2017/017543 WO2017151296A1 (en) | 2016-03-04 | 2017-02-10 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
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EP (1) | EP3424087A4 (ja) |
JP (1) | JP2019511803A (ja) |
KR (1) | KR101981911B1 (ja) |
CN (1) | CN108886094A (ja) |
SG (1) | SG10201601703UA (ja) |
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WO2018106450A1 (en) | 2016-12-09 | 2018-06-14 | Microsemi Soc Corp. | Resistive random access memory cell |
US10522224B2 (en) | 2017-08-11 | 2019-12-31 | Microsemi Soc Corp. | Circuitry and methods for programming resistive random access memory devices |
US10515697B1 (en) * | 2018-06-29 | 2019-12-24 | Intel Corporation | Apparatuses and methods to control operations performed on resistive memory cells |
KR102670952B1 (ko) * | 2019-07-16 | 2024-05-30 | 삼성전자주식회사 | 저항성 메모리 장치 및 저항성 메모리 장치의 동작 방법 |
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KR20180113631A (ko) | 2018-10-16 |
SG10201601703UA (en) | 2017-10-30 |
EP3424087A4 (en) | 2019-11-06 |
TWI621122B (zh) | 2018-04-11 |
US9959927B2 (en) | 2018-05-01 |
KR101981911B1 (ko) | 2019-05-23 |
CN108886094A (zh) | 2018-11-23 |
TW201802817A (zh) | 2018-01-16 |
EP3424087A1 (en) | 2019-01-09 |
US20170316823A1 (en) | 2017-11-02 |
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