JP2019153756A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019153756A JP2019153756A JP2018039958A JP2018039958A JP2019153756A JP 2019153756 A JP2019153756 A JP 2019153756A JP 2018039958 A JP2018039958 A JP 2018039958A JP 2018039958 A JP2018039958 A JP 2018039958A JP 2019153756 A JP2019153756 A JP 2019153756A
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- JP
- Japan
- Prior art keywords
- semiconductor element
- terminal
- semiconductor device
- plate
- radiator plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
第1下側放熱板26、はんだ層60、N端子15が、それぞれ、「放熱板」、「接合材」、「電力端子」の一例である。Z方向が、「厚み方向」の一例である。
12 :封止体
14 :P端子
15 :N端子
15a :屈曲部
16 :O端子
18、19 :信号端子
20、40 :第1半導体素子
22 :第1上側放熱板
22c :第1上側継手部
22e :第1上側継手部のはんだ吸収溝
23、25、27、43、45、47、50、60 :はんだ層
24 :導体スペーサ
26 :第1下側放熱板
40 :第2半導体素子
42 :第2上側放熱板
42c :第2上側継手部
42e :第2上側継手部のはんだ吸収溝
46 :第2下側放熱板
46c :第2下側継手部
B :境界
S1 :接合エリア
S2 :非接合エリア
Claims (1)
- 半導体装置であって、
半導体素子と、
前記半導体素子に接続された放熱板と、
前記放熱板に接合材を介して接合された電力端子と、を備え、
前記電力端子は、前記接合材に接触する接合エリアとそれに隣接する非接合エリアとの境界において、前記電力端子の厚み方向に屈曲する屈曲部が形成されている、
半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018039958A JP7069848B2 (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018039958A JP7069848B2 (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019153756A true JP2019153756A (ja) | 2019-09-12 |
JP7069848B2 JP7069848B2 (ja) | 2022-05-18 |
Family
ID=67946972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2018039958A Active JP7069848B2 (ja) | 2018-03-06 | 2018-03-06 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP7069848B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012169044A1 (ja) * | 2011-06-09 | 2012-12-13 | 三菱電機株式会社 | 半導体装置 |
US20140103510A1 (en) * | 2012-10-17 | 2014-04-17 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20150214139A1 (en) * | 2014-01-30 | 2015-07-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2017208385A (ja) * | 2016-05-16 | 2017-11-24 | 株式会社デンソー | 電子装置 |
-
2018
- 2018-03-06 JP JP2018039958A patent/JP7069848B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012169044A1 (ja) * | 2011-06-09 | 2012-12-13 | 三菱電機株式会社 | 半導体装置 |
US20140103510A1 (en) * | 2012-10-17 | 2014-04-17 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
JP2014082384A (ja) * | 2012-10-17 | 2014-05-08 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US20150214139A1 (en) * | 2014-01-30 | 2015-07-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2015142072A (ja) * | 2014-01-30 | 2015-08-03 | 株式会社東芝 | 半導体装置 |
JP2017208385A (ja) * | 2016-05-16 | 2017-11-24 | 株式会社デンソー | 電子装置 |
US20190221490A1 (en) * | 2016-05-16 | 2019-07-18 | Denso Corporation | Electronic device |
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Publication number | Publication date |
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JP7069848B2 (ja) | 2022-05-18 |
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