JP2019145659A5 - - Google Patents

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Publication number
JP2019145659A5
JP2019145659A5 JP2018028057A JP2018028057A JP2019145659A5 JP 2019145659 A5 JP2019145659 A5 JP 2019145659A5 JP 2018028057 A JP2018028057 A JP 2018028057A JP 2018028057 A JP2018028057 A JP 2018028057A JP 2019145659 A5 JP2019145659 A5 JP 2019145659A5
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JP
Japan
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region
impurity
semiconductor substrate
semiconductor device
gate electrode
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JP2018028057A
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English (en)
Japanese (ja)
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JP2019145659A (ja
JP6971877B2 (ja
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Priority to JP2018028057A priority Critical patent/JP6971877B2/ja
Priority claimed from JP2018028057A external-priority patent/JP6971877B2/ja
Priority to US16/248,251 priority patent/US10950600B2/en
Publication of JP2019145659A publication Critical patent/JP2019145659A/ja
Publication of JP2019145659A5 publication Critical patent/JP2019145659A5/ja
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JP2018028057A 2018-02-20 2018-02-20 半導体装置 Active JP6971877B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018028057A JP6971877B2 (ja) 2018-02-20 2018-02-20 半導体装置
US16/248,251 US10950600B2 (en) 2018-02-20 2019-01-15 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018028057A JP6971877B2 (ja) 2018-02-20 2018-02-20 半導体装置

Publications (3)

Publication Number Publication Date
JP2019145659A JP2019145659A (ja) 2019-08-29
JP2019145659A5 true JP2019145659A5 (enExample) 2020-09-10
JP6971877B2 JP6971877B2 (ja) 2021-11-24

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Family Applications (1)

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JP2018028057A Active JP6971877B2 (ja) 2018-02-20 2018-02-20 半導体装置

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US (1) US10950600B2 (enExample)
JP (1) JP6971877B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10944001B1 (en) * 2020-01-06 2021-03-09 Nxp Usa, Inc. Deep trench and junction hybrid isolation
JP7759855B2 (ja) * 2022-08-10 2025-10-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3509552B2 (ja) * 1998-04-30 2004-03-22 株式会社デンソー 半導体装置
JP2011029466A (ja) * 2009-07-28 2011-02-10 Hitachi Ltd 半導体装置
JP5460279B2 (ja) * 2009-12-11 2014-04-02 株式会社日立製作所 半導体装置およびその製造方法
US8841723B2 (en) * 2010-03-10 2014-09-23 Richtek Technology Corporation, R.O.C. LDMOS device having increased punch-through voltage and method for making same
KR101710599B1 (ko) * 2011-01-12 2017-02-27 삼성전자 주식회사 반도체 장치 및 그 제조 방법
JP6271157B2 (ja) 2013-05-24 2018-01-31 ルネサスエレクトロニクス株式会社 半導体装置
JP6252022B2 (ja) * 2013-08-05 2017-12-27 セイコーエプソン株式会社 半導体装置
JP5725230B2 (ja) * 2014-04-09 2015-05-27 株式会社デンソー 半導体装置
JP6383325B2 (ja) * 2014-06-27 2018-08-29 株式会社東芝 半導体装置
US9306060B1 (en) * 2014-11-20 2016-04-05 Freescale Semiconductor Inc. Semiconductor devices and related fabrication methods
CN106206561B (zh) * 2015-04-29 2019-05-10 无锡华润上华科技有限公司 Ldmos可控硅结构的静电保护器件
JP6664261B2 (ja) * 2016-04-07 2020-03-13 キヤノン株式会社 半導体装置及び液体吐出ヘッド用基板

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