JP2019129350A5 - - Google Patents

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Publication number
JP2019129350A5
JP2019129350A5 JP2018008321A JP2018008321A JP2019129350A5 JP 2019129350 A5 JP2019129350 A5 JP 2019129350A5 JP 2018008321 A JP2018008321 A JP 2018008321A JP 2018008321 A JP2018008321 A JP 2018008321A JP 2019129350 A5 JP2019129350 A5 JP 2019129350A5
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JP
Japan
Prior art keywords
effect transistor
channel field
circuit
duty ratio
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018008321A
Other languages
English (en)
Japanese (ja)
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JP2019129350A (ja
JP7071621B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2018008321A priority Critical patent/JP7071621B2/ja
Priority claimed from JP2018008321A external-priority patent/JP7071621B2/ja
Priority to US16/215,210 priority patent/US10666234B2/en
Priority to EP18211875.2A priority patent/EP3518420B1/en
Priority to CN201910039213.8A priority patent/CN110071705B/zh
Publication of JP2019129350A publication Critical patent/JP2019129350A/ja
Publication of JP2019129350A5 publication Critical patent/JP2019129350A5/ja
Application granted granted Critical
Publication of JP7071621B2 publication Critical patent/JP7071621B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2018008321A 2018-01-22 2018-01-22 送信回路及び集積回路 Active JP7071621B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018008321A JP7071621B2 (ja) 2018-01-22 2018-01-22 送信回路及び集積回路
US16/215,210 US10666234B2 (en) 2018-01-22 2018-12-10 Transmission circuit and integrated circuit
EP18211875.2A EP3518420B1 (en) 2018-01-22 2018-12-12 Transmission circuit and integrated circuit
CN201910039213.8A CN110071705B (zh) 2018-01-22 2019-01-16 发送电路以及集成电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018008321A JP7071621B2 (ja) 2018-01-22 2018-01-22 送信回路及び集積回路

Publications (3)

Publication Number Publication Date
JP2019129350A JP2019129350A (ja) 2019-08-01
JP2019129350A5 true JP2019129350A5 (enExample) 2021-01-07
JP7071621B2 JP7071621B2 (ja) 2022-05-19

Family

ID=64901833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018008321A Active JP7071621B2 (ja) 2018-01-22 2018-01-22 送信回路及び集積回路

Country Status (4)

Country Link
US (1) US10666234B2 (enExample)
EP (1) EP3518420B1 (enExample)
JP (1) JP7071621B2 (enExample)
CN (1) CN110071705B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10833656B2 (en) * 2018-04-30 2020-11-10 Micron Technology, Inc. Autonomous duty cycle calibration
US11309876B2 (en) * 2019-11-18 2022-04-19 Macom Technology Solutions Holdings, Inc. Digitally programmable analog duty-cycle correction circuit
US11005464B1 (en) * 2020-03-26 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Delay line circuit
US11658644B2 (en) * 2020-12-07 2023-05-23 Macom Technology Solutions Holdings, Inc. Programmable duty cycle distortion generator
US11632115B2 (en) * 2021-05-14 2023-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Clock synthesizer
IT202300007998A1 (it) 2023-04-24 2024-10-24 St Microelectronics Int Nv Circuito di calibrazione del duty-cycle, trasmettitore, sistema di comunicazione e procedimento corrispondenti

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188931A (ja) * 1990-11-21 1992-07-07 Nec Corp ラインドライバ回路
US6445253B1 (en) * 2000-12-18 2002-09-03 Api Networks, Inc. Voltage-controlled oscillator with ac coupling to produce highly accurate duty cycle square wave output
US6507220B1 (en) * 2001-09-28 2003-01-14 Xilinx, Inc. Correction of duty-cycle distortion in communications and other circuits
JP2007006060A (ja) 2005-06-23 2007-01-11 Sony Corp 集積回路、再生装置及び再生方法
US20070159224A1 (en) * 2005-12-21 2007-07-12 Amar Dwarka Duty-cycle correction circuit for differential clocking
US7310010B2 (en) * 2006-04-13 2007-12-18 Infineon Technologies Ag Duty cycle corrector
US7518425B2 (en) * 2007-02-05 2009-04-14 Promos Technologies Pte.Ltd Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices
JP5038738B2 (ja) 2007-02-08 2012-10-03 株式会社東芝 デューティ調整回路
US8149978B2 (en) 2007-03-12 2012-04-03 Nippon Telegraph And Telephone Corporation Clock/data recovery circuit
JP5231289B2 (ja) 2009-03-02 2013-07-10 ルネサスエレクトロニクス株式会社 デューティ比補正回路及びデューティ比補正方法
JP2011254226A (ja) 2010-06-01 2011-12-15 Renesas Electronics Corp パルス幅調整回路及びこれを用いたデューティ比補正回路
US8462906B1 (en) * 2011-09-15 2013-06-11 Altera Corporation Apparatus and methods for detection and correction of transmitter duty cycle distortion
US9143121B2 (en) 2012-08-29 2015-09-22 Qualcomm Incorporated System and method of adjusting a clock signal
JP2016039626A (ja) * 2014-08-05 2016-03-22 富士通株式会社 半導体装置、電源供給制御回路及び電源供給制御方法

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