JP2019047682A - 半導体集積回路 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 230000003071 parasitic effect Effects 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- 239000012535 impurity Substances 0.000 claims description 13
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 description 11
- 230000005669 field effect Effects 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005524 hole trap Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K2017/066—Maximizing the OFF-resistance instead of minimizing the ON-resistance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Abstract
Description
本発明の第1実施形態に係る電力用半導体集積回路(以下において、単に「半導体集積回路」という。)10,20は、図1に示すように、高電位側スイッチング素子S1及び低電位側スイッチング素子S2のゲートを駆動する高耐圧のゲート駆動回路である。
第1実施形態においては、負電圧クランプダイオードD1を、駆動回路13のpチャネルMOSトランジスタTR1及びnチャネルMOSトランジスタTR2と素子分離して設けた場合を例示したが、斯かる例示に限定されるものではない。本発明の第2実施形態として、駆動回路13のpチャネルMOSトランジスタTR1及びnチャネルMOSトランジスタTR2の一部と領域を共有するように負電圧クランプダイオードを設ける場合を説明する。
第1実施形態においては、図1に示すように、負電圧源15,25を用いた場合を例示したが、例示に過ぎない。ここでは、本発明の第3実施形態として負電圧源を用いない構成を説明する。
上記のように、本発明は第1〜第3実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
11,21…入力制御回路
12…レベルシフト回路
13,23…駆動回路
14,24…正電圧源
15,25…負電圧源
30,50a,50b…寄生pnpバイポーラトランジスタ
31,51…支持基板
32,52…SOI絶縁層
33,53…SOI半導体層
34,44,54a,54b,54c…オフセット領域
35,45…アノード領域
36,46,56a,56b…表面短絡領域
37,47,55a,55b…カソード領域
38a,38b,60a,60b…トレンチ絶縁膜
39,48,61…フィールド絶縁膜
41…半導体基板
42a,42b,43…ウェル領域
58a,58b,58c…バックゲート領域
59a,59b,59c,59d…ソース領域
62a,62b,62c,62d…ゲート電極
C1,C2,C3,C4…コンデンサ
D1,D2,D11,D12…負電圧クランプダイオード
D3,D4…整流ダイオード
Rg1,Rg2,Rg3,Rg4…ゲート抵抗
S1…高電位側スイッチング素子
S2…低電位側スイッチング素子
TR1,TR2,TR3,TR4…電界効果トランジスタ
Claims (8)
- スイッチング素子の制御端子を駆動する半導体集積回路であって、
正電圧源から供給される正電圧と、負電圧源から供給される負電圧とを交互に前記制御端子に印加することにより前記スイッチング素子をオン・オフする駆動回路と、
前記駆動回路が設けられた半導体チップに内蔵され、前記負電圧源にアノードが接続され、且つ前記制御端子にカソードが接続された負電圧クランプダイオード
とを備えることを特徴とする半導体集積回路。 - スイッチング素子の制御端子を駆動する半導体集積回路であって、
正電圧源から供給される正電圧と、前記スイッチング素子の低位電極端子の電位とを交互に前記制御端子に印加することにより前記スイッチング素子をオン・オフする駆動回路と、
前記駆動回路が設けられた半導体チップに内蔵され、前記低位電極端子にアノードが接続され、且つ前記制御端子にカソードが接続された負電圧クランプダイオード
とを備えることを特徴とする半導体集積回路。 - 前記負電圧クランプダイオードが前記負電圧源の電圧以下でクランプすることを特徴とする請求項1に記載の半導体集積回路。
- 前記負電圧クランプダイオードがゲート駆動電圧以上の逆耐圧特性を有することを特徴とする請求項1〜3のいずれか1項に記載の半導体集積回路。
- 前記負電圧クランプダイオードがゲート抵抗を介さずに前記制御端子に接続されていることを特徴とする請求項1〜4のいずれか1項に記載の半導体集積回路。
- 前記半導体チップが、
第1導電型の半導体基板の上部に設けられた第2導電型のオフセット領域と、
前記オフセット領域の上部に設けられ、前記オフセット領域よりも高不純物密度の第2導電型のアノード領域と、
前記半導体基板の上部に設けられ、前記半導体基板よりも高不純物密度の第1導電型のカソード領域
とを備え、前記負電圧クランプダイオードが前記アノード領域及び前記カソード領域を有することを特徴とする請求項1〜5のいずれか1項に記載の半導体集積回路。 - 前記半導体チップが、前記半導体基板の上部に、前記カソード領域に接して設けられ、前記カソード領域と表面配線で短絡する第2導電型の表面短絡領域を更に備え、
前記アノード領域をエミッタ領域、前記カソード領域をベース領域、前記表面短絡領域をコレクタ領域とする寄生バイポーラトランジスタが形成されていることを特徴とする請求項6に記載の半導体集積回路。 - 前記駆動回路が、
第1能動素子と、
前記第1能動素子と直列に接続された第2能動素子
とを備え、
前記アノード領域が、前記第2能動素子のバックゲート領域と兼用されることを特徴とする請求項6又は7に記載の半導体集積回路。
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US16/100,597 US10547304B2 (en) | 2017-09-05 | 2018-08-10 | Semiconductor integrated circuit for driving switching device with integrated negative voltage clamp diode |
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CN111082638A (zh) * | 2019-12-12 | 2020-04-28 | 中国科学院上海微系统与信息技术研究所 | 一种电压切换器与其控制方法 |
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JP2020167612A (ja) * | 2019-03-29 | 2020-10-08 | 住友電装株式会社 | 給電制御装置 |
EP3872990A1 (en) * | 2020-02-28 | 2021-09-01 | Infineon Technologies AG | Semiconductor switching assembly and gate driver circuit |
CN113422595B (zh) * | 2021-08-24 | 2021-11-19 | 成都市易冲半导体有限公司 | 一种处理负压ac信号的电子开关及其控制方法 |
EP4346102A1 (en) * | 2022-09-29 | 2024-04-03 | Infineon Technologies Austria AG | Gate driver circuit and power switching assembly with gate driver circuit |
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