JP2012004460A - 半導体装置およびその製造方法 - Google Patents
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Abstract
【解決手段】P型半導体基板1内にN型拡散領域2を備え、N型拡散領域2内に、P型拡散領域3と、P型拡散領域3とは平面的に離間した位置に形成された高濃度N型拡散領域4とを備えている。P型拡散領域3内には、高濃度N型拡散領域5と高濃度P型拡散領域6が形成され、P型拡散領域3の上で高濃度N型拡散領域5と高濃度N型拡散領域4の間には、ゲート酸化膜を介してゲート電極7が形成され、ゲート電極7の一方端部が高濃度N型拡散領域5上にオーバーラップして形成されている。
【選択図】図1
Description
図1は、本発明の実施形態1の半導体装置としての高耐圧ダイオードの要部構成例を模式的に示す縦断面図である。
本実施形態2では、上記実施形態1の構成に加えて、第2導電型の第1拡散領域(N型拡散領域2)内に第2導電型の第3拡散領域(N型拡散領域8)を備え、第3拡散領域(N型拡散領域8)内に第3高濃度拡散領域(高濃度N型拡散領域4)を備えた場合について説明する。
本実施形態3では、上記実施形態1の構成に加えて、第2導電型の第1拡散領域(N型拡散領域2)内の、第1導電型の第2拡散領域(P型拡散領域3)と第3高濃度拡散領域(高濃度N型拡散領域4)との間に形成された絶縁分離膜を備えるた場合について説明する。
本実施形態3によれば、絶縁分離膜9を設けたことにより、上記実施形態1の場合と比較して、逆バイアス時の電界を大幅に緩和することができるため、更なる高耐圧化が可能となる。上記実施形態1において、逆バイアス時に、ゲート電極7のカソード側のゲートエッジ(領域Aとする)で電界が集中するため、高耐圧化には限界があったが、図10に示す絶縁分離膜9により、領域A(ゲート電極7の一端)の電界を大幅に緩和することができて更なる高耐圧化を実現することができる。
本実施形態4では、上記実施形態1の構成に加えて、第2導電型の第1拡散領域(N型拡散領域2)内に、第1導電型の第2拡散領域(P型拡散領域3)と第2導電型の第3拡散領域(N型拡散領域8A)を備え、第3拡散領域(N型拡散領域8A)内に第3高濃度拡散領域(高濃度N型拡散領域4)を備え、第1導電型の第2拡散領域(P型拡散領域3)と第3高濃度拡散領域(高濃度N型拡散領域4)との間に形成された絶縁分離膜9を備えた場合について説明する。
本実施形態5では、第1導電型の第2拡散領域(P型拡散領域3)の底部に、高エネルギー注入により形成されたN型埋め込み拡散領域(後述するN型埋め込み拡散領域10)を備えた場合について説明する。
上記実施形態1〜5では、第1導電型の半導体層が第1導電型の半導体基板(P型半導体基板1)である場合について説明し、このP型半導体基板1上に高耐圧ダイオード21〜25を形成したが、本実施形態6では、第1導電型の半導体層が第1導電型の拡散領域である場合について説明し、このP型拡散領域上に高耐圧ダイオード26を形成する場合について説明する。
1A P型拡散領域(Pウェル層)
2 N型拡散領域
3 P型拡散領域
4 高濃度N型拡散領域
5 高濃度N型拡散領域
6 高濃度P型拡散領域
7 ゲート電極
7A トレンチゲート
8、8A N型拡散領域
9 絶縁分離膜
10 N型埋め込み拡散領域
11 N型半導体基板
21〜26 高耐圧ダイオード
Ib 順方向電流
Ibp ベース電流
Ien エミッタ電流
IMOS 逆バイアスMOSFET(Q1)の電流
Vth 逆バイアスMOSFETの閾値電圧
Ic 基板リーク電流
VA1 逆バイアスMOSFETが有る場合のアノード電圧
VA2 逆MOSFETがない場合のアノード電圧
Ic1 逆バイアスMOSFETが有る場合の基板リーク電流
Ic2 逆バイアスMOSFETがないい場合の基板リーク電流
L 長さ
VF、VF1、VF2 順方向電圧
Claims (19)
- 第1導電型の半導体層上に形成される半導体装置において、
該半導体層上に形成された第2導電型の第1拡散領域と、
該第1拡散領域内に形成された第1導電型の第2拡散領域と、
該第2拡散領域内に形成された第2導電型の第1高濃度拡散領域および第1導電型の第2高濃度拡散領域と、
該第1拡散領域内で該第2拡散領域と所定距離だけ離間した位置に形成された第2導電型の第3高濃度拡散領域と、
該第1高濃度拡散領域と該第3高濃度拡散領域の間上にゲート絶縁膜を介して形成されたゲート電極とを備え、
該ゲート電極が該第1高濃度拡散領域上にオーバーラップして形成され、該ゲート電極が、該第1高濃度拡散領域および該第2高濃度拡散領域と同電位に電気的に接続されている半導体装置。 - 前記第1高濃度拡散領域、前記第3高濃度拡散領域および、これらの間上に設けられた前記ゲート電極により逆バイアスMOSFETが構成されている請求項1に記載の半導体装置。
- 前記ゲート電極の一端と前記第3高濃度拡散領域とは所定距離だけ離間している請求項1に記載の半導体装置。
- 前記第1高濃度拡散領域、前記第2高濃度拡散領域および前記ゲート電極がアノード電極に接続され、前記第3高濃度拡散領域がカソード電極に接続されている請求項1に記載の半導体装置。
- 前記第2導電型の第1拡散領域内に第2導電型の第3拡散領域を備え、該第3拡散領域内に前記第3高濃度拡散領域を備えた請求項1に記載の半導体装置。
- 前記第2導電型の第1拡散領域内に、前記第1導電型の第2拡散領域と前記第3高濃度拡散領域との間に形成された絶縁分離膜を備えた請求項1に記載の半導体装置。
- 前記第2導電型の第1拡散領域内に第2導電型の第3拡散領域を備え、該第3拡散領域内に前記第3高濃度拡散領域および絶縁分離膜を備え、該絶縁分離膜は前記第1導電型の第2拡散領域と該第3高濃度拡散領域との間に形成された請求項1に記載の半導体装置。
- 前記第2拡散領域と前記第3拡散領域とは、前記ゲート電極下で所定距離だけ離間している請求項5または7に記載の半導体装置。
- 前記第2拡散領域と前記絶縁分離膜とは、前記ゲート電極下で所定距離だけ離間している請求項7に記載の半導体装置。
- 前記絶縁分離膜は、前記ゲート電極の前記第3高濃度拡散領域側の一端下を含む所定距離だけ設けられている請求項6、7および9のいずれかに記載の半導体装置。
- 前記第1導電型の第2拡散領域の底部に、高エネルギー注入により形成された第2導電型の埋め込み拡散領域を備えた請求項1に記載の半導体装置。
- 前記第1導電型の半導体層が第1導電型の半導体基板である請求項1に記載の半導体装置。
- 前記第1導電型の半導体層が第1導電型の拡散領域である請求項1に記載の半導体装置。
- 高耐圧ダイオードである請求項1に記載の半導体装置。
- 第1導電型の半導体層上に形成される半導体装置の製造方法において、
該半導体層上に第2導電型の第1拡散領域を形成する工程と、
該第1拡散領域内に第1導電型の第2拡散領域を形成する工程と、
該第2拡散領域内に第2導電型の第1高濃度拡散領域および第1導電型の第2高濃度拡散領域を形成する工程と、
該第1拡散領域内で該第2拡散領域と所定距離だけ離間した位置に第2導電型の第3高濃度拡散領域を形成する工程と、
該第1高濃度拡散領域と該第3高濃度拡散領域の間上にゲート絶縁膜を介して、該第1高濃度拡散領域と上下でオーバーラップするようにゲート電極を形成する工程と、
該ゲート電極を、該第1高濃度拡散領域および該第2高濃度拡散領域と同電位に電気的に接続する工程とを有する半導体装置の製造方法。 - 前記第1拡散領域内に第1導電型の第2拡散領域を形成する工程は、該第1拡散領域内に該第2拡散領域と所定距離を置いて第2導電型の第3拡散領域を形成する工程を含み、前記第1拡散領域内で該第2拡散領域と所定距離だけ離間した位置に第2導電型の第3高濃度拡散領域を形成する工程は、該第1拡散領域内の該第3拡散領域内に該第3高濃度拡散領域を形成する請求項15に記載の半導体装置の製造方法。
- 前記第1拡散領域内に第1導電型の第2拡散領域を形成する工程は、該第1拡散領域内に該第2拡散領域と所定距離を置いて絶縁分離膜を形成する工程を含む請求項15に記載の半導体装置の製造方法。
- 前記第1拡散領域内に第1導電型の第2拡散領域を形成する工程は、該第1拡散領域内に該第2拡散領域と所定距離を置いて第2導電型の第3拡散領域を形成すると共に、該第3拡散領域内に該第2拡散領域と所定距離を置いて絶縁分離膜を形成する工程を含み、前記第1拡散領域内で該第2拡散領域と所定距離だけ離間した位置に第2導電型の第3高濃度拡散領域を形成する工程は、該第1拡散領域内の該第3拡散領域内に該第3高濃度拡散領域を形成する請求項15に記載の半導体装置の製造方法。
- 前記第1拡散領域内に第1導電型の第2拡散領域を形成する工程は、該第2拡散領域の底部に、高エネルギー注入により第2導電型の埋め込み拡散領域を形成する工程を含む請求項15に記載の半導体装置の製造方法。
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US8952483B2 (en) | 2012-12-13 | 2015-02-10 | Renesas Electronics Corporation | Semiconductor device |
JP2015115365A (ja) * | 2013-12-09 | 2015-06-22 | ローム株式会社 | ダイオードおよびそれを含む信号出力回路 |
JP2019047682A (ja) * | 2017-09-05 | 2019-03-22 | 富士電機株式会社 | 半導体集積回路 |
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US20130334648A1 (en) * | 2012-06-15 | 2013-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for High Voltage Diodes |
US10290702B2 (en) | 2012-07-31 | 2019-05-14 | Silanna Asia Pte Ltd | Power device on bulk substrate |
US9412881B2 (en) * | 2012-07-31 | 2016-08-09 | Silanna Asia Pte Ltd | Power device integration on a common substrate |
WO2014128950A1 (ja) * | 2013-02-25 | 2014-08-28 | 株式会社 日立製作所 | 半導体装置および半導体回路の駆動装置ならびに電力変換装置 |
US9923059B1 (en) | 2017-02-20 | 2018-03-20 | Silanna Asia Pte Ltd | Connection arrangements for integrated lateral diffusion field effect transistors |
US10083897B2 (en) | 2017-02-20 | 2018-09-25 | Silanna Asia Pte Ltd | Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact |
FR3086798B1 (fr) * | 2018-09-28 | 2022-12-09 | St Microelectronics Tours Sas | Structure de diode |
CN117673160A (zh) * | 2024-01-31 | 2024-03-08 | 深圳天狼芯半导体有限公司 | 碳化硅高k超结功率mosfet及其制备方法、芯片 |
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US5818084A (en) * | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
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US8952483B2 (en) | 2012-12-13 | 2015-02-10 | Renesas Electronics Corporation | Semiconductor device |
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