JP2018533254A5 - - Google Patents

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Publication number
JP2018533254A5
JP2018533254A5 JP2018511372A JP2018511372A JP2018533254A5 JP 2018533254 A5 JP2018533254 A5 JP 2018533254A5 JP 2018511372 A JP2018511372 A JP 2018511372A JP 2018511372 A JP2018511372 A JP 2018511372A JP 2018533254 A5 JP2018533254 A5 JP 2018533254A5
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Japan
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output
error
decoder
double
vector signal
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JP2018511372A
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Japanese (ja)
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JP6884138B2 (ja
JP2018533254A (ja
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Priority claimed from US14/852,988 external-priority patent/US9800271B2/en
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JP2018511372A 2015-09-14 2016-08-25 低電力ダブルエラー訂正−トリプルエラー検出（ｄｅｃ−ｔｅｄ）デコーダ Expired - Fee Related JP6884138B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/852,988 US9800271B2 (en) 2015-09-14 2015-09-14 Error correction and decoding
US14/852,988 2015-09-14
PCT/US2016/048604 WO2017048474A1 (en) 2015-09-14 2016-08-25 Low-power double error correcting-triple error detecting (deb-ted) decoder

Publications (3)

Publication Number Publication Date
JP2018533254A JP2018533254A (ja) 2018-11-08
JP2018533254A5 true JP2018533254A5 (enExample) 2019-09-19
JP6884138B2 JP6884138B2 (ja) 2021-06-09

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JP2018511372A Expired - Fee Related JP6884138B2 (ja) 2015-09-14 2016-08-25 低電力ダブルエラー訂正−トリプルエラー検出（ｄｅｃ−ｔｅｄ）デコーダ

Country Status (7)

Country Link
US (2) US9800271B2 (enExample)
EP (1) EP3350930B1 (enExample)
JP (1) JP6884138B2 (enExample)
KR (1) KR102599033B1 (enExample)
CN (1) CN108055876B (enExample)
TW (2) TWI662796B (enExample)
WO (1) WO2017048474A1 (enExample)

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