CN108055876B - 低功率双纠错-三检错(deb-ted)解码器 - Google Patents

低功率双纠错-三检错(deb-ted)解码器 Download PDF

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CN108055876B
CN108055876B CN201680052581.0A CN201680052581A CN108055876B CN 108055876 B CN108055876 B CN 108055876B CN 201680052581 A CN201680052581 A CN 201680052581A CN 108055876 B CN108055876 B CN 108055876B
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error
double
decoder
vector signal
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CN108055876A (zh
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S-O·郑
S·崔
B·K·宋
T·那
J·金
J·P·金
S·金
T·金
S·H·康
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Industry Academic Cooperation Foundation of Yonsei University
Qualcomm Inc
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Qualcomm Inc
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615Use of computational or mathematical techniques
    • H03M13/616Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • H03M13/15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152Bose-Chaudhuri-Hocquenghem [BCH] codes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • H03M13/15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615Use of computational or mathematical techniques
    • H03M13/617Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6502Reduction of hardware complexity or efficient processing

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Algebra (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
CN201680052581.0A 2015-09-14 2016-08-25 低功率双纠错-三检错(deb-ted)解码器 Active CN108055876B (zh)

Applications Claiming Priority (3)

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US14/852,988 US9800271B2 (en) 2015-09-14 2015-09-14 Error correction and decoding
US14/852,988 2015-09-14
PCT/US2016/048604 WO2017048474A1 (en) 2015-09-14 2016-08-25 Low-power double error correcting-triple error detecting (deb-ted) decoder

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CN (1) CN108055876B (enExample)
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9800271B2 (en) 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding
US10268539B2 (en) * 2015-12-28 2019-04-23 Intel Corporation Apparatus and method for multi-bit error detection and correction
KR102453437B1 (ko) 2018-01-25 2022-10-12 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
KR102583797B1 (ko) * 2018-04-09 2023-10-05 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102105428B1 (ko) * 2018-08-29 2020-04-28 남서울대학교 산학협력단 Sec부호에서 멀티오류정정을 위한 복호기 및 그 복호 방법
KR102045437B1 (ko) * 2018-09-07 2019-12-02 고려대학교 산학협력단 저복잡도 신드롬 기반 복호 장치 및 그 방법
RU2704499C1 (ru) * 2018-11-22 2019-10-29 Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный университет аэрокосмического приборостроения" Декодер кода Боуза-Чоудхури-Хоквингема с каноническим декодером Хэмминга
US11016843B2 (en) * 2018-12-06 2021-05-25 Micron Technology, Inc. Direct-input redundancy scheme with adaptive syndrome decoder
KR102758952B1 (ko) * 2018-12-17 2025-01-23 삼성전자주식회사 에러 정정 코드 회로, 반도체 메모리 장치 및 메모리 시스템
CN111835320A (zh) * 2019-04-22 2020-10-27 珠海格力电器股份有限公司 一种信号的边沿检测装置
KR102705065B1 (ko) * 2019-07-29 2024-09-09 에스케이하이닉스 주식회사 낮은 레이턴시를 갖는 에러정정코드 디코더
US11095313B2 (en) 2019-10-21 2021-08-17 International Business Machines Corporation Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
KR20210092391A (ko) * 2020-01-16 2021-07-26 삼성전자주식회사 반도체 메모리 장치의 에러 정정 회로 및 반도체 메모리 장치
JP7631126B2 (ja) * 2021-06-29 2025-02-18 ルネサスエレクトロニクス株式会社 半導体装置
US12461812B2 (en) 2021-10-18 2025-11-04 Micron Technology, Inc. ECC power consumption optimization in memories
US12250005B2 (en) 2023-06-16 2025-03-11 Microsoft Technology Licensing, Llc Error correction systems and methods
DE102023119646A1 (de) * 2023-07-25 2025-01-30 Infineon Technologies Ag Verarbeitung eines datenworts

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111647A (ja) * 1994-10-20 1996-04-30 Hiroichi Okano 単一誤り訂正および多重誤り検出bch符号の復号装置
CN1637713A (zh) * 2003-12-23 2005-07-13 国际商业机器公司 用于双重错误修正和三重错误检测的(18,9)错误修正码
CN101493804A (zh) * 2008-01-24 2009-07-29 国际商业机器公司 数据总线系统及其编/解码器和编/解码方法
KR20090092628A (ko) * 2008-02-27 2009-09-01 삼성전자주식회사 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3650107A (en) * 1970-08-12 1972-03-21 Sperry Rand Corp Power transmission
US4030067A (en) 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4397022A (en) * 1981-01-30 1983-08-02 Weng Ming I Weighted erasure codec for the (24, 12) extended Golay code
US4556977A (en) 1983-09-15 1985-12-03 International Business Machines Corporation Decoding of BCH double error correction - triple error detection (DEC-TED) codes
US4979174A (en) * 1988-12-29 1990-12-18 At&T Bell Laboratories Error correction and detection apparatus and method
US5323402A (en) * 1991-02-14 1994-06-21 The Mitre Corporation Programmable systolic BCH decoder
KR950008789B1 (ko) * 1992-07-30 1995-08-08 삼성전자주식회사 멀티-이씨씨(ecc)회로를 내장하는 반도체 메모리 장치
DE69317766T2 (de) 1993-06-10 1998-07-30 Bull Hn Information Syst Fehlerkorrekturgerät für digitale Daten zur Korrektur von Einfachfehlern (sec), von Doppelfehlern (ded) und Vielfacheinzelbytefehlern (sbd) und zur Korrektur von Einzelbytefehlern ungerader Anzahl (odd sbc)
US5666371A (en) * 1995-02-24 1997-09-09 Unisys Corporation Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements
JP3258897B2 (ja) * 1996-03-18 2002-02-18 富士通株式会社 軟判定誤り訂正復号装置
CN1154908C (zh) * 1997-04-02 2004-06-23 松下电器产业株式会社 数据输入存贮器并对存储器内存入的数据进行运算输出并能高速操作的数据输入输出装置
US6662336B1 (en) * 1999-07-06 2003-12-09 Cirrus Logic, Inc. Error correction method and apparatus
US6662333B1 (en) * 2000-02-04 2003-12-09 Hewlett-Packard Development Company, L.P. Shared error correction for memory design
US6701480B1 (en) * 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US7634709B2 (en) 2001-10-05 2009-12-15 Unisys Corporation Familial correction with non-familial double bit error detection
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
GB2391769B (en) * 2002-07-31 2005-07-06 Hewlett Packard Co Reed-Solomon decoder and decoding method for errors and erasures decoding
TWI234937B (en) * 2003-05-22 2005-06-21 Edimax Technology Co Ltd Encoding technology to detect and correct error
JP3892832B2 (ja) * 2003-08-11 2007-03-14 株式会社東芝 半導体記憶装置
EP1612949B1 (en) 2004-06-30 2010-04-21 STMicroelectronics Srl Method and system for correcting errors in electronic memory devices
US7502986B2 (en) * 2005-02-09 2009-03-10 International Business Machines Corporation Method and apparatus for collecting failure information on error correction code (ECC) protected data
KR100732628B1 (ko) * 2005-07-28 2007-06-27 삼성전자주식회사 멀티-비트 데이터 및 싱글-비트 데이터를 저장하는 플래시메모리 장치
US7793195B1 (en) * 2006-05-11 2010-09-07 Link—A—Media Devices Corporation Incremental generation of polynomials for decoding reed-solomon codes
JP5162763B2 (ja) * 2007-08-07 2013-03-13 株式会社メガチップス メモリアクセスシステム
KR101433620B1 (ko) * 2007-08-17 2014-08-25 삼성전자주식회사 처리량을 높이기 위하여 더블 버퍼링 구조와 파이프라이닝기법을 이용하는 디코더 및 그 디코딩 방법
US8261165B2 (en) 2008-11-14 2012-09-04 Silicon Laboratories Inc. Multi-syndrome error correction circuit
TWI399042B (zh) * 2009-06-06 2013-06-11 Univ Ishou To detect the wrong position of the detection device
US8381083B2 (en) * 2009-10-22 2013-02-19 Arm Limited Error control coding for single error correction and double error detection
WO2011109713A2 (en) 2010-03-05 2011-09-09 Board Of Regents Of The University Of Texas System Error detecting/correcting code enhanced self-checked/corrected/timed nanoelectronic circuits
US8984367B2 (en) * 2011-02-25 2015-03-17 Altera Corporation Error detection and correction circuitry
US8612834B2 (en) * 2011-03-08 2013-12-17 Intel Corporation Apparatus, system, and method for decoding linear block codes in a memory controller
GB201114831D0 (en) * 2011-08-26 2011-10-12 Univ Oxford Brookes Circuit with error correction
US8762821B2 (en) * 2012-03-30 2014-06-24 Intel Corporation Method of correcting adjacent errors by using BCH-based error correction coding
US8694862B2 (en) * 2012-04-20 2014-04-08 Arm Limited Data processing apparatus using implicit data storage data storage and method of implicit data storage
US8745472B2 (en) 2012-09-01 2014-06-03 Texas Instruments Incorporated Memory with segmented error correction codes
US8984368B2 (en) * 2012-10-11 2015-03-17 Advanced Micro Devices, Inc. High reliability memory controller
US9246516B2 (en) * 2012-12-20 2016-01-26 Intel Corporation Techniques for error correction of encoded data
US9054742B2 (en) * 2013-03-14 2015-06-09 Intel Corporation Error and erasure decoding apparatus and method
US9417957B2 (en) * 2013-10-04 2016-08-16 Infineon Technologies Ag Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device
US9800271B2 (en) 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08111647A (ja) * 1994-10-20 1996-04-30 Hiroichi Okano 単一誤り訂正および多重誤り検出bch符号の復号装置
CN1637713A (zh) * 2003-12-23 2005-07-13 国际商业机器公司 用于双重错误修正和三重错误检测的(18,9)错误修正码
CN101493804A (zh) * 2008-01-24 2009-07-29 国际商业机器公司 数据总线系统及其编/解码器和编/解码方法
KR20090092628A (ko) * 2008-02-27 2009-09-01 삼성전자주식회사 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BCH(31,16)、CRC-32与交织码级联的实现及分析;白婷等;《遥测遥控》;20071115(第06期);全文 *
SEU Tolerant Latch Based on Error Detection;Xiaoxuan She;《IEEE Transactions on Nuclear Science》;20120105;全文 *
三值汉明码检错纠错原理和方法;沈云付;《计算机学报》;20150831;全文 *

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TWI662796B (zh) 2019-06-11
KR20180053700A (ko) 2018-05-23
TW201818666A (zh) 2018-05-16
EP3350930A1 (en) 2018-07-25
US10263645B2 (en) 2019-04-16
JP2018533254A (ja) 2018-11-08
KR102599033B1 (ko) 2023-11-03
JP6884138B2 (ja) 2021-06-09
US9800271B2 (en) 2017-10-24
US20170077963A1 (en) 2017-03-16
TWI625943B (zh) 2018-06-01
EP3350930B1 (en) 2023-07-26
CN108055876A (zh) 2018-05-18
TW201714411A (zh) 2017-04-16
WO2017048474A1 (en) 2017-03-23
US20180019767A1 (en) 2018-01-18

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