CN108055876B - 低功率双纠错-三检错(deb-ted)解码器 - Google Patents
低功率双纠错-三检错(deb-ted)解码器 Download PDFInfo
- Publication number
- CN108055876B CN108055876B CN201680052581.0A CN201680052581A CN108055876B CN 108055876 B CN108055876 B CN 108055876B CN 201680052581 A CN201680052581 A CN 201680052581A CN 108055876 B CN108055876 B CN 108055876B
- Authority
- CN
- China
- Prior art keywords
- output
- error
- double
- decoder
- vector signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/617—Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Algebra (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/852,988 US9800271B2 (en) | 2015-09-14 | 2015-09-14 | Error correction and decoding |
| US14/852,988 | 2015-09-14 | ||
| PCT/US2016/048604 WO2017048474A1 (en) | 2015-09-14 | 2016-08-25 | Low-power double error correcting-triple error detecting (deb-ted) decoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108055876A CN108055876A (zh) | 2018-05-18 |
| CN108055876B true CN108055876B (zh) | 2022-11-18 |
Family
ID=56896776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680052581.0A Active CN108055876B (zh) | 2015-09-14 | 2016-08-25 | 低功率双纠错-三检错(deb-ted)解码器 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US9800271B2 (enExample) |
| EP (1) | EP3350930B1 (enExample) |
| JP (1) | JP6884138B2 (enExample) |
| KR (1) | KR102599033B1 (enExample) |
| CN (1) | CN108055876B (enExample) |
| TW (2) | TWI625943B (enExample) |
| WO (1) | WO2017048474A1 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9800271B2 (en) | 2015-09-14 | 2017-10-24 | Qualcomm Incorporated | Error correction and decoding |
| US10268539B2 (en) * | 2015-12-28 | 2019-04-23 | Intel Corporation | Apparatus and method for multi-bit error detection and correction |
| KR102453437B1 (ko) | 2018-01-25 | 2022-10-12 | 삼성전자주식회사 | 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법 |
| KR102583797B1 (ko) * | 2018-04-09 | 2023-10-05 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
| KR102105428B1 (ko) * | 2018-08-29 | 2020-04-28 | 남서울대학교 산학협력단 | Sec부호에서 멀티오류정정을 위한 복호기 및 그 복호 방법 |
| KR102045437B1 (ko) * | 2018-09-07 | 2019-12-02 | 고려대학교 산학협력단 | 저복잡도 신드롬 기반 복호 장치 및 그 방법 |
| RU2704499C1 (ru) * | 2018-11-22 | 2019-10-29 | Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный университет аэрокосмического приборостроения" | Декодер кода Боуза-Чоудхури-Хоквингема с каноническим декодером Хэмминга |
| US11016843B2 (en) * | 2018-12-06 | 2021-05-25 | Micron Technology, Inc. | Direct-input redundancy scheme with adaptive syndrome decoder |
| KR102758952B1 (ko) * | 2018-12-17 | 2025-01-23 | 삼성전자주식회사 | 에러 정정 코드 회로, 반도체 메모리 장치 및 메모리 시스템 |
| CN111835320A (zh) * | 2019-04-22 | 2020-10-27 | 珠海格力电器股份有限公司 | 一种信号的边沿检测装置 |
| KR102705065B1 (ko) * | 2019-07-29 | 2024-09-09 | 에스케이하이닉스 주식회사 | 낮은 레이턴시를 갖는 에러정정코드 디코더 |
| US11095313B2 (en) | 2019-10-21 | 2021-08-17 | International Business Machines Corporation | Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures |
| KR20210092391A (ko) * | 2020-01-16 | 2021-07-26 | 삼성전자주식회사 | 반도체 메모리 장치의 에러 정정 회로 및 반도체 메모리 장치 |
| JP7631126B2 (ja) * | 2021-06-29 | 2025-02-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US12461812B2 (en) | 2021-10-18 | 2025-11-04 | Micron Technology, Inc. | ECC power consumption optimization in memories |
| US12250005B2 (en) | 2023-06-16 | 2025-03-11 | Microsoft Technology Licensing, Llc | Error correction systems and methods |
| DE102023119646A1 (de) * | 2023-07-25 | 2025-01-30 | Infineon Technologies Ag | Verarbeitung eines datenworts |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111647A (ja) * | 1994-10-20 | 1996-04-30 | Hiroichi Okano | 単一誤り訂正および多重誤り検出bch符号の復号装置 |
| CN1637713A (zh) * | 2003-12-23 | 2005-07-13 | 国际商业机器公司 | 用于双重错误修正和三重错误检测的(18,9)错误修正码 |
| CN101493804A (zh) * | 2008-01-24 | 2009-07-29 | 国际商业机器公司 | 数据总线系统及其编/解码器和编/解码方法 |
| KR20090092628A (ko) * | 2008-02-27 | 2009-09-01 | 삼성전자주식회사 | 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법 |
Family Cites Families (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3623155A (en) * | 1969-12-24 | 1971-11-23 | Ibm | Optimum apparatus and method for check bit generation and error detection, location and correction |
| US3650107A (en) * | 1970-08-12 | 1972-03-21 | Sperry Rand Corp | Power transmission |
| US4030067A (en) | 1975-12-29 | 1977-06-14 | Honeywell Information Systems, Inc. | Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes |
| US4397022A (en) * | 1981-01-30 | 1983-08-02 | Weng Ming I | Weighted erasure codec for the (24, 12) extended Golay code |
| US4556977A (en) | 1983-09-15 | 1985-12-03 | International Business Machines Corporation | Decoding of BCH double error correction - triple error detection (DEC-TED) codes |
| US4979174A (en) * | 1988-12-29 | 1990-12-18 | At&T Bell Laboratories | Error correction and detection apparatus and method |
| US5323402A (en) * | 1991-02-14 | 1994-06-21 | The Mitre Corporation | Programmable systolic BCH decoder |
| KR950008789B1 (ko) * | 1992-07-30 | 1995-08-08 | 삼성전자주식회사 | 멀티-이씨씨(ecc)회로를 내장하는 반도체 메모리 장치 |
| DE69317766T2 (de) | 1993-06-10 | 1998-07-30 | Bull Hn Information Syst | Fehlerkorrekturgerät für digitale Daten zur Korrektur von Einfachfehlern (sec), von Doppelfehlern (ded) und Vielfacheinzelbytefehlern (sbd) und zur Korrektur von Einzelbytefehlern ungerader Anzahl (odd sbc) |
| US5666371A (en) * | 1995-02-24 | 1997-09-09 | Unisys Corporation | Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements |
| JP3258897B2 (ja) * | 1996-03-18 | 2002-02-18 | 富士通株式会社 | 軟判定誤り訂正復号装置 |
| CN1154908C (zh) * | 1997-04-02 | 2004-06-23 | 松下电器产业株式会社 | 数据输入存贮器并对存储器内存入的数据进行运算输出并能高速操作的数据输入输出装置 |
| US6662336B1 (en) * | 1999-07-06 | 2003-12-09 | Cirrus Logic, Inc. | Error correction method and apparatus |
| US6662333B1 (en) * | 2000-02-04 | 2003-12-09 | Hewlett-Packard Development Company, L.P. | Shared error correction for memory design |
| US6701480B1 (en) * | 2000-03-08 | 2004-03-02 | Rockwell Automation Technologies, Inc. | System and method for providing error check and correction in memory systems |
| US7634709B2 (en) | 2001-10-05 | 2009-12-15 | Unisys Corporation | Familial correction with non-familial double bit error detection |
| US7051264B2 (en) * | 2001-11-14 | 2006-05-23 | Monolithic System Technology, Inc. | Error correcting memory and method of operating same |
| GB2391769B (en) * | 2002-07-31 | 2005-07-06 | Hewlett Packard Co | Reed-Solomon decoder and decoding method for errors and erasures decoding |
| TWI234937B (en) * | 2003-05-22 | 2005-06-21 | Edimax Technology Co Ltd | Encoding technology to detect and correct error |
| JP3892832B2 (ja) * | 2003-08-11 | 2007-03-14 | 株式会社東芝 | 半導体記憶装置 |
| EP1612949B1 (en) | 2004-06-30 | 2010-04-21 | STMicroelectronics Srl | Method and system for correcting errors in electronic memory devices |
| US7502986B2 (en) * | 2005-02-09 | 2009-03-10 | International Business Machines Corporation | Method and apparatus for collecting failure information on error correction code (ECC) protected data |
| KR100732628B1 (ko) * | 2005-07-28 | 2007-06-27 | 삼성전자주식회사 | 멀티-비트 데이터 및 싱글-비트 데이터를 저장하는 플래시메모리 장치 |
| US7793195B1 (en) * | 2006-05-11 | 2010-09-07 | Link—A—Media Devices Corporation | Incremental generation of polynomials for decoding reed-solomon codes |
| JP5162763B2 (ja) * | 2007-08-07 | 2013-03-13 | 株式会社メガチップス | メモリアクセスシステム |
| KR101433620B1 (ko) * | 2007-08-17 | 2014-08-25 | 삼성전자주식회사 | 처리량을 높이기 위하여 더블 버퍼링 구조와 파이프라이닝기법을 이용하는 디코더 및 그 디코딩 방법 |
| US8261165B2 (en) | 2008-11-14 | 2012-09-04 | Silicon Laboratories Inc. | Multi-syndrome error correction circuit |
| TWI399042B (zh) * | 2009-06-06 | 2013-06-11 | Univ Ishou | To detect the wrong position of the detection device |
| US8381083B2 (en) * | 2009-10-22 | 2013-02-19 | Arm Limited | Error control coding for single error correction and double error detection |
| WO2011109713A2 (en) | 2010-03-05 | 2011-09-09 | Board Of Regents Of The University Of Texas System | Error detecting/correcting code enhanced self-checked/corrected/timed nanoelectronic circuits |
| US8984367B2 (en) * | 2011-02-25 | 2015-03-17 | Altera Corporation | Error detection and correction circuitry |
| US8612834B2 (en) * | 2011-03-08 | 2013-12-17 | Intel Corporation | Apparatus, system, and method for decoding linear block codes in a memory controller |
| GB201114831D0 (en) * | 2011-08-26 | 2011-10-12 | Univ Oxford Brookes | Circuit with error correction |
| US8762821B2 (en) * | 2012-03-30 | 2014-06-24 | Intel Corporation | Method of correcting adjacent errors by using BCH-based error correction coding |
| US8694862B2 (en) * | 2012-04-20 | 2014-04-08 | Arm Limited | Data processing apparatus using implicit data storage data storage and method of implicit data storage |
| US8745472B2 (en) | 2012-09-01 | 2014-06-03 | Texas Instruments Incorporated | Memory with segmented error correction codes |
| US8984368B2 (en) * | 2012-10-11 | 2015-03-17 | Advanced Micro Devices, Inc. | High reliability memory controller |
| US9246516B2 (en) * | 2012-12-20 | 2016-01-26 | Intel Corporation | Techniques for error correction of encoded data |
| US9054742B2 (en) * | 2013-03-14 | 2015-06-09 | Intel Corporation | Error and erasure decoding apparatus and method |
| US9417957B2 (en) * | 2013-10-04 | 2016-08-16 | Infineon Technologies Ag | Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device |
| US9800271B2 (en) | 2015-09-14 | 2017-10-24 | Qualcomm Incorporated | Error correction and decoding |
-
2015
- 2015-09-14 US US14/852,988 patent/US9800271B2/en not_active Expired - Fee Related
-
2016
- 2016-08-25 WO PCT/US2016/048604 patent/WO2017048474A1/en not_active Ceased
- 2016-08-25 JP JP2018511372A patent/JP6884138B2/ja not_active Expired - Fee Related
- 2016-08-25 EP EP16763625.7A patent/EP3350930B1/en active Active
- 2016-08-25 CN CN201680052581.0A patent/CN108055876B/zh active Active
- 2016-08-25 KR KR1020187010280A patent/KR102599033B1/ko active Active
- 2016-08-29 TW TW105127673A patent/TWI625943B/zh active
- 2016-08-29 TW TW107106147A patent/TWI662796B/zh active
-
2017
- 2017-09-26 US US15/716,451 patent/US10263645B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111647A (ja) * | 1994-10-20 | 1996-04-30 | Hiroichi Okano | 単一誤り訂正および多重誤り検出bch符号の復号装置 |
| CN1637713A (zh) * | 2003-12-23 | 2005-07-13 | 国际商业机器公司 | 用于双重错误修正和三重错误检测的(18,9)错误修正码 |
| CN101493804A (zh) * | 2008-01-24 | 2009-07-29 | 国际商业机器公司 | 数据总线系统及其编/解码器和编/解码方法 |
| KR20090092628A (ko) * | 2008-02-27 | 2009-09-01 | 삼성전자주식회사 | 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법 |
Non-Patent Citations (3)
| Title |
|---|
| BCH(31,16)、CRC-32与交织码级联的实现及分析;白婷等;《遥测遥控》;20071115(第06期);全文 * |
| SEU Tolerant Latch Based on Error Detection;Xiaoxuan She;《IEEE Transactions on Nuclear Science》;20120105;全文 * |
| 三值汉明码检错纠错原理和方法;沈云付;《计算机学报》;20150831;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI662796B (zh) | 2019-06-11 |
| KR20180053700A (ko) | 2018-05-23 |
| TW201818666A (zh) | 2018-05-16 |
| EP3350930A1 (en) | 2018-07-25 |
| US10263645B2 (en) | 2019-04-16 |
| JP2018533254A (ja) | 2018-11-08 |
| KR102599033B1 (ko) | 2023-11-03 |
| JP6884138B2 (ja) | 2021-06-09 |
| US9800271B2 (en) | 2017-10-24 |
| US20170077963A1 (en) | 2017-03-16 |
| TWI625943B (zh) | 2018-06-01 |
| EP3350930B1 (en) | 2023-07-26 |
| CN108055876A (zh) | 2018-05-18 |
| TW201714411A (zh) | 2017-04-16 |
| WO2017048474A1 (en) | 2017-03-23 |
| US20180019767A1 (en) | 2018-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108055876B (zh) | 低功率双纠错-三检错(deb-ted)解码器 | |
| US11683050B2 (en) | Memory controller and method of data bus inversion using an error detection correction code | |
| CN104247273B (zh) | 用于重构码字的设备及计算机实现的方法 | |
| CN104583964B (zh) | 与用于编码的数据的纠错相关联的方法和设备 | |
| US10291258B2 (en) | Error correcting code for correcting single symbol errors and detecting double bit errors | |
| CN102939590B (zh) | 为在存储器元件内存储的数据提供数据保护的方法及其集成电路器件 | |
| CN103890732B (zh) | 数字错误校正 | |
| TWI550628B (zh) | 解碼方法、記憶體儲存裝置及記憶體控制電路單元 | |
| CN104409103A (zh) | 一种新颖的宇航用存储器二维编码加固方法及电路装置 | |
| CN103218271B (zh) | 一种数据纠错方法及装置 | |
| CN110322922A (zh) | 带内动态随机存取存储器纠错编码的设备和系统 | |
| Farheen et al. | Error detection and correction using RP SEC-DED | |
| US9032270B2 (en) | Device and method for storing encoded and/or decoded codes by re-using encoder | |
| JP3743915B2 (ja) | スポッティバイト誤り訂正・検出方法及び装置 | |
| BR112018004992B1 (pt) | Aparelho e método de detecção e correção de erros para um código bose-chaudhuri-hocquenghem, bch, de correção de erros duplos e detecção de erros triplos, dec-ted, e, memória | |
| Sunita et al. | Pipeline architecture for fast decoding of bch codes For nor flash memory | |
| CN109669804B (zh) | 用于降低ecc存储器的存储区实际软错误率的方法和装置 | |
| Kang et al. | Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |