KR102599033B1 - 저전력 이중 에러 정정―삼중 에러 검출（deb―ted） 디코더 - Google Patents

저전력 이중 에러 정정―삼중 에러 검출（deb―ted） 디코더 Download PDF

Info

Publication number
KR102599033B1
KR102599033B1 KR1020187010280A KR20187010280A KR102599033B1 KR 102599033 B1 KR102599033 B1 KR 102599033B1 KR 1020187010280 A KR1020187010280 A KR 1020187010280A KR 20187010280 A KR20187010280 A KR 20187010280A KR 102599033 B1 KR102599033 B1 KR 102599033B1
Authority
KR
South Korea
Prior art keywords
output
error
input
correction
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187010280A
Other languages
English (en)
Korean (ko)
Other versions
KR20180053700A (ko
Inventor
승욱 정
사라 최
병규 송
태희 나
지수 김
정필 김
성률 김
태현 김
승혁 강
Original Assignee
퀄컴 인코포레이티드
연세대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드, 연세대학교 산학협력단 filed Critical 퀄컴 인코포레이티드
Publication of KR20180053700A publication Critical patent/KR20180053700A/ko
Application granted granted Critical
Publication of KR102599033B1 publication Critical patent/KR102599033B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/617—Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Algebra (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
KR1020187010280A 2015-09-14 2016-08-25 저전력 이중 에러 정정―삼중 에러 검출（deb―ted） 디코더 Active KR102599033B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/852,988 US9800271B2 (en) 2015-09-14 2015-09-14 Error correction and decoding
US14/852,988 2015-09-14
PCT/US2016/048604 WO2017048474A1 (en) 2015-09-14 2016-08-25 Low-power double error correcting-triple error detecting (deb-ted) decoder

Publications (2)

Publication Number Publication Date
KR20180053700A KR20180053700A (ko) 2018-05-23
KR102599033B1 true KR102599033B1 (ko) 2023-11-03

Family

ID=56896776

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187010280A Active KR102599033B1 (ko) 2015-09-14 2016-08-25 저전력 이중 에러 정정―삼중 에러 검출（deb―ted） 디코더

Country Status (7)

Country Link
US (2) US9800271B2 (enExample)
EP (1) EP3350930B1 (enExample)
JP (1) JP6884138B2 (enExample)
KR (1) KR102599033B1 (enExample)
CN (1) CN108055876B (enExample)
TW (2) TWI662796B (enExample)
WO (1) WO2017048474A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9800271B2 (en) 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding
US10268539B2 (en) * 2015-12-28 2019-04-23 Intel Corporation Apparatus and method for multi-bit error detection and correction
KR102453437B1 (ko) 2018-01-25 2022-10-12 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
KR102583797B1 (ko) * 2018-04-09 2023-10-05 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR102105428B1 (ko) * 2018-08-29 2020-04-28 남서울대학교 산학협력단 Sec부호에서 멀티오류정정을 위한 복호기 및 그 복호 방법
KR102045437B1 (ko) * 2018-09-07 2019-12-02 고려대학교 산학협력단 저복잡도 신드롬 기반 복호 장치 및 그 방법
RU2704499C1 (ru) * 2018-11-22 2019-10-29 Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный университет аэрокосмического приборостроения" Декодер кода Боуза-Чоудхури-Хоквингема с каноническим декодером Хэмминга
US11016843B2 (en) * 2018-12-06 2021-05-25 Micron Technology, Inc. Direct-input redundancy scheme with adaptive syndrome decoder
KR102758952B1 (ko) * 2018-12-17 2025-01-23 삼성전자주식회사 에러 정정 코드 회로, 반도체 메모리 장치 및 메모리 시스템
CN111835320A (zh) * 2019-04-22 2020-10-27 珠海格力电器股份有限公司 一种信号的边沿检测装置
KR102705065B1 (ko) * 2019-07-29 2024-09-09 에스케이하이닉스 주식회사 낮은 레이턴시를 갖는 에러정정코드 디코더
US11095313B2 (en) 2019-10-21 2021-08-17 International Business Machines Corporation Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
KR20210092391A (ko) * 2020-01-16 2021-07-26 삼성전자주식회사 반도체 메모리 장치의 에러 정정 회로 및 반도체 메모리 장치
JP7631126B2 (ja) * 2021-06-29 2025-02-18 ルネサスエレクトロニクス株式会社 半導体装置
WO2023067367A1 (en) 2021-10-18 2023-04-27 Micron Technology, Inc. Ecc power consumption optimization in memories
US12250005B2 (en) * 2023-06-16 2025-03-11 Microsoft Technology Licensing, Llc Error correction systems and methods
DE102023119646A1 (de) * 2023-07-25 2025-01-30 Infineon Technologies Ag Verarbeitung eines datenworts

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623155A (en) * 1969-12-24 1971-11-23 Ibm Optimum apparatus and method for check bit generation and error detection, location and correction
US3650107A (en) * 1970-08-12 1972-03-21 Sperry Rand Corp Power transmission
US4030067A (en) 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4397022A (en) * 1981-01-30 1983-08-02 Weng Ming I Weighted erasure codec for the (24, 12) extended Golay code
US4556977A (en) 1983-09-15 1985-12-03 International Business Machines Corporation Decoding of BCH double error correction - triple error detection (DEC-TED) codes
US4979174A (en) * 1988-12-29 1990-12-18 At&T Bell Laboratories Error correction and detection apparatus and method
US5323402A (en) * 1991-02-14 1994-06-21 The Mitre Corporation Programmable systolic BCH decoder
KR950008789B1 (ko) * 1992-07-30 1995-08-08 삼성전자주식회사 멀티-이씨씨(ecc)회로를 내장하는 반도체 메모리 장치
EP0629051B1 (en) 1993-06-10 1998-04-01 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Digital information error correcting apparatus for correcting single errors(sec),detecting double errors(ded)and single byte multiple errors(sbd),and the correction of an odd number of single byte errors(odd sbc).
JP2691973B2 (ja) * 1994-10-20 1997-12-17 博一 岡野 単一誤り訂正および多重誤り検出ｂｃｈ符号の復号装置
US5666371A (en) * 1995-02-24 1997-09-09 Unisys Corporation Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements
JP3258897B2 (ja) * 1996-03-18 2002-02-18 富士通株式会社 軟判定誤り訂正復号装置
TW432362B (en) * 1997-04-02 2001-05-01 Matsushita Electric Industrial Co Ltd High speed data input-output device which fetches data into internal memory and performs operations on the data before outputting the data
US6662336B1 (en) * 1999-07-06 2003-12-09 Cirrus Logic, Inc. Error correction method and apparatus
US6662333B1 (en) * 2000-02-04 2003-12-09 Hewlett-Packard Development Company, L.P. Shared error correction for memory design
US6701480B1 (en) * 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US7634709B2 (en) 2001-10-05 2009-12-15 Unisys Corporation Familial correction with non-familial double bit error detection
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
GB2391769B (en) * 2002-07-31 2005-07-06 Hewlett Packard Co Reed-Solomon decoder and decoding method for errors and erasures decoding
TWI234937B (en) * 2003-05-22 2005-06-21 Edimax Technology Co Ltd Encoding technology to detect and correct error
JP3892832B2 (ja) * 2003-08-11 2007-03-14 株式会社東芝 半導体記憶装置
US7243293B2 (en) * 2003-12-23 2007-07-10 International Business Machines Corporation (18, 9) Error correction code for double error correction and triple error detection
DE602004026707D1 (de) * 2004-06-30 2010-06-02 St Microelectronics Srl Verfahren und Vorrichtung für die Fehlerkorrektur in elektronischen Speichern
US7502986B2 (en) * 2005-02-09 2009-03-10 International Business Machines Corporation Method and apparatus for collecting failure information on error correction code (ECC) protected data
KR100732628B1 (ko) * 2005-07-28 2007-06-27 삼성전자주식회사 멀티-비트 데이터 및 싱글-비트 데이터를 저장하는 플래시메모리 장치
US7793195B1 (en) * 2006-05-11 2010-09-07 Link—A—Media Devices Corporation Incremental generation of polynomials for decoding reed-solomon codes
JP5162763B2 (ja) * 2007-08-07 2013-03-13 株式会社メガチップス メモリアクセスシステム
KR101433620B1 (ko) * 2007-08-17 2014-08-25 삼성전자주식회사 처리량을 높이기 위하여 더블 버퍼링 구조와 파이프라이닝기법을 이용하는 디코더 및 그 디코딩 방법
CN101493804B (zh) * 2008-01-24 2011-07-20 国际商业机器公司 数据总线系统及其编解码器和编解码方法
KR101437396B1 (ko) * 2008-02-27 2014-09-05 삼성전자주식회사 레이턴시를 줄일 수 있는 에러 정정 블록을 포함하는메모리 시스템 및 그것의 에러 정정 방법
US8261165B2 (en) 2008-11-14 2012-09-04 Silicon Laboratories Inc. Multi-syndrome error correction circuit
TWI399042B (zh) * 2009-06-06 2013-06-11 Univ Ishou To detect the wrong position of the detection device
US8381083B2 (en) * 2009-10-22 2013-02-19 Arm Limited Error control coding for single error correction and double error detection
WO2011109713A2 (en) 2010-03-05 2011-09-09 Board Of Regents Of The University Of Texas System Error detecting/correcting code enhanced self-checked/corrected/timed nanoelectronic circuits
US8984367B2 (en) * 2011-02-25 2015-03-17 Altera Corporation Error detection and correction circuitry
US8612834B2 (en) * 2011-03-08 2013-12-17 Intel Corporation Apparatus, system, and method for decoding linear block codes in a memory controller
GB201114831D0 (en) * 2011-08-26 2011-10-12 Univ Oxford Brookes Circuit with error correction
US8762821B2 (en) * 2012-03-30 2014-06-24 Intel Corporation Method of correcting adjacent errors by using BCH-based error correction coding
US8694862B2 (en) * 2012-04-20 2014-04-08 Arm Limited Data processing apparatus using implicit data storage data storage and method of implicit data storage
US8745472B2 (en) 2012-09-01 2014-06-03 Texas Instruments Incorporated Memory with segmented error correction codes
US8984368B2 (en) * 2012-10-11 2015-03-17 Advanced Micro Devices, Inc. High reliability memory controller
US9246516B2 (en) * 2012-12-20 2016-01-26 Intel Corporation Techniques for error correction of encoded data
US9054742B2 (en) * 2013-03-14 2015-06-09 Intel Corporation Error and erasure decoding apparatus and method
US9417957B2 (en) * 2013-10-04 2016-08-16 Infineon Technologies Ag Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device
US9800271B2 (en) 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding

Also Published As

Publication number Publication date
TW201714411A (zh) 2017-04-16
TW201818666A (zh) 2018-05-16
US10263645B2 (en) 2019-04-16
WO2017048474A1 (en) 2017-03-23
US20180019767A1 (en) 2018-01-18
CN108055876A (zh) 2018-05-18
EP3350930B1 (en) 2023-07-26
JP2018533254A (ja) 2018-11-08
US9800271B2 (en) 2017-10-24
US20170077963A1 (en) 2017-03-16
JP6884138B2 (ja) 2021-06-09
TWI625943B (zh) 2018-06-01
TWI662796B (zh) 2019-06-11
EP3350930A1 (en) 2018-07-25
CN108055876B (zh) 2022-11-18
KR20180053700A (ko) 2018-05-23

Similar Documents

Publication Publication Date Title
KR102599033B1 (ko) 저전력 이중 에러 정정―삼중 에러 검출（deb―ted） 디코더
US11349496B2 (en) Memory controller and method of data bus inversion using an error detection correction code
US11740960B2 (en) Detection and correction of data bit errors using error correction codes
JP4036338B2 (ja) 誤りバイト数を制限したバイト内複数スポッティバイト誤り訂正・検出方法及び装置
US10725841B1 (en) Method and apparatus for error detection and correction
US20110246853A1 (en) Semiconductor device and decoding method thereof
US10860419B2 (en) Minimal aliasing bit-error correction code
US10291258B2 (en) Error correcting code for correcting single symbol errors and detecting double bit errors
US10263644B1 (en) Hybrid architecture for LDPC channel coding in data center
CN113489995B (zh) 用以解码接收信息的解码方法与相关解码装置
Farheen et al. Error detection and correction using RP SEC-DED
US20250038769A1 (en) Syndrome decoder circuit
JP3743915B2 (ja) スポッティバイト誤り訂正・検出方法及び装置
US10003360B2 (en) Device and method for finding error location
BR112018004992B1 (pt) Aparelho e método de detecção e correção de erros para um código bose-chaudhuri-hocquenghem, bch, de correção de erros duplos e detecção de erros triplos, dec-ted, e, memória
Vishwa Sri et al. Design of majority logic gates-based HT-LDPC for multiple adjacent and non-adjacent bits error correction
JP2006101429A (ja) バイト内複数スポッティバイト誤り訂正・検出方法及び装置
CN114974353A (zh) 一种基于动态ecc的抗单粒子翻转加固方法及系统

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20180411

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20210811

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20230215

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20230803

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20231101

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20231101

End annual number: 3

Start annual number: 1

PG1601 Publication of registration