JP2018530098A - メモリコントローラとメモリとの間のリフレッシュタイマ同期 - Google Patents

メモリコントローラとメモリとの間のリフレッシュタイマ同期 Download PDF

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Publication number
JP2018530098A
JP2018530098A JP2018516132A JP2018516132A JP2018530098A JP 2018530098 A JP2018530098 A JP 2018530098A JP 2018516132 A JP2018516132 A JP 2018516132A JP 2018516132 A JP2018516132 A JP 2018516132A JP 2018530098 A JP2018530098 A JP 2018530098A
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Prior art keywords
refresh
dram
memory controller
self
mode
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JP2018516132A
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Japanese (ja)
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JP2018530098A5 (enExample
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エドウィン・ホセ
マイケル・ドロップ
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クアルコム，インコーポレイテッド
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Publication of JP2018530098A publication Critical patent/JP2018530098A/ja
Publication of JP2018530098A5 publication Critical patent/JP2018530098A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
JP2018516132A 2015-10-01 2016-08-25 メモリコントローラとメモリとの間のリフレッシュタイマ同期 Pending JP2018530098A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562236008P 2015-10-01 2015-10-01
US62/236,008 2015-10-01
US15/246,371 US9875785B2 (en) 2015-10-01 2016-08-24 Refresh timer synchronization between memory controller and memory
US15/246,371 2016-08-24
PCT/US2016/048771 WO2017058417A1 (en) 2015-10-01 2016-08-25 Refresh timer synchronization between memory controller and memory

Publications (2)

Publication Number Publication Date
JP2018530098A true JP2018530098A (ja) 2018-10-11
JP2018530098A5 JP2018530098A5 (enExample) 2019-09-19

Family

ID=56852438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018516132A Pending JP2018530098A (ja) 2015-10-01 2016-08-25 メモリコントローラとメモリとの間のリフレッシュタイマ同期

Country Status (7)

Country Link
US (1) US9875785B2 (enExample)
EP (1) EP3357065B1 (enExample)
JP (1) JP2018530098A (enExample)
KR (1) KR102593418B1 (enExample)
CN (1) CN108140406B (enExample)
BR (1) BR112018006477B1 (enExample)
WO (1) WO2017058417A1 (enExample)

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US20190074051A1 (en) * 2017-09-07 2019-03-07 Mediatek Inc. Memory system and refresh control method thereof
US10489316B1 (en) 2018-06-04 2019-11-26 Micron Technology, Inc. Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
KR102578002B1 (ko) 2018-07-03 2023-09-14 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US10685722B1 (en) * 2019-01-24 2020-06-16 Western Digital Technologies, Inc. Method and system for improving performance of a storage device using asynchronous independent plane read functionality
US11250902B2 (en) * 2019-09-26 2022-02-15 Intel Corporation Method and apparatus to reduce power consumption for refresh of memory devices on a memory module
KR102839272B1 (ko) * 2020-07-02 2025-07-29 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
KR102786984B1 (ko) 2020-09-03 2025-03-27 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템, 그것을 제어하는 제어기 및 그것의 동작 방법
KR20220091162A (ko) 2020-12-23 2022-06-30 삼성전자주식회사 온도에 대한 리프레쉬 레이트 승수와 상관없는 메모리 장치의 리프레쉬 방법
TWI740773B (zh) * 2021-01-27 2021-09-21 華邦電子股份有限公司 半導體記憶裝置
US12142312B2 (en) 2022-09-13 2024-11-12 Nanya Technology Corporation Memory control circuit and refresh method for dynamic random access memory array

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JPH09213071A (ja) * 1996-02-02 1997-08-15 Hitachi Ltd 半導体記憶装置
JP2000315385A (ja) * 1999-04-30 2000-11-14 Nec Ic Microcomput Syst Ltd セルフリフレッシュ回路及びセルフリフレッシュ方法
US20050259493A1 (en) * 2004-05-21 2005-11-24 Walker Robert M Method and system for controlling refresh in volatile memories
US20060159156A1 (en) * 2005-01-20 2006-07-20 Seung-Hoon Lee Method for outputting internal temperature data in semiconductor memory device and circuit of outputting internal temperature data thereby
JP2006344257A (ja) * 2005-06-07 2006-12-21 Fujitsu Ltd 半導体記憶装置及び情報処理システム
US20120030420A1 (en) * 2009-04-22 2012-02-02 Rambus Inc. Protocol for refresh between a memory controller and a memory device

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JPH09213071A (ja) * 1996-02-02 1997-08-15 Hitachi Ltd 半導体記憶装置
JP2000315385A (ja) * 1999-04-30 2000-11-14 Nec Ic Microcomput Syst Ltd セルフリフレッシュ回路及びセルフリフレッシュ方法
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Also Published As

Publication number Publication date
CN108140406A (zh) 2018-06-08
US20170098470A1 (en) 2017-04-06
WO2017058417A1 (en) 2017-04-06
KR102593418B1 (ko) 2023-10-23
CN108140406B (zh) 2022-03-22
EP3357065A1 (en) 2018-08-08
KR20180063230A (ko) 2018-06-11
EP3357065B1 (en) 2019-06-26
BR112018006477A2 (pt) 2018-10-09
BR112018006477B1 (pt) 2023-03-14
US9875785B2 (en) 2018-01-23

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