BR112018006477A2 - sincronização de temporizador de atualização de entre controlador de memória e memória - Google Patents

sincronização de temporizador de atualização de entre controlador de memória e memória

Info

Publication number
BR112018006477A2
BR112018006477A2 BR112018006477A BR112018006477A BR112018006477A2 BR 112018006477 A2 BR112018006477 A2 BR 112018006477A2 BR 112018006477 A BR112018006477 A BR 112018006477A BR 112018006477 A BR112018006477 A BR 112018006477A BR 112018006477 A2 BR112018006477 A2 BR 112018006477A2
Authority
BR
Brazil
Prior art keywords
memory
memory controller
update timer
timer synchronization
controller
Prior art date
Application number
BR112018006477A
Other languages
English (en)
Other versions
BR112018006477B1 (pt
Inventor
Jose Edwin
Drop Michael
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018006477A2 publication Critical patent/BR112018006477A2/pt
Publication of BR112018006477B1 publication Critical patent/BR112018006477B1/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

um controlador de memória é configurado para comunicar a uma dram uma indicação de quando um ciclo de atualização acionado por controlador de memória ocorrer antes de uma transição a um modo de auto-atualização de operação em que a dram auto-aciona seus ciclos de atualização.
BR112018006477-7A 2015-10-01 2016-08-25 Sincronização de temporizador de atualização de entre controlador de memória e memória BR112018006477B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562236008P 2015-10-01 2015-10-01
US62/236,008 2015-10-01
US15/246,371 US9875785B2 (en) 2015-10-01 2016-08-24 Refresh timer synchronization between memory controller and memory
US15/246,371 2016-08-24
PCT/US2016/048771 WO2017058417A1 (en) 2015-10-01 2016-08-25 Refresh timer synchronization between memory controller and memory

Publications (2)

Publication Number Publication Date
BR112018006477A2 true BR112018006477A2 (pt) 2018-10-09
BR112018006477B1 BR112018006477B1 (pt) 2023-03-14

Family

ID=56852438

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018006477-7A BR112018006477B1 (pt) 2015-10-01 2016-08-25 Sincronização de temporizador de atualização de entre controlador de memória e memória

Country Status (7)

Country Link
US (1) US9875785B2 (pt)
EP (1) EP3357065B1 (pt)
JP (1) JP2018530098A (pt)
KR (1) KR102593418B1 (pt)
CN (1) CN108140406B (pt)
BR (1) BR112018006477B1 (pt)
WO (1) WO2017058417A1 (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180061484A1 (en) * 2016-08-29 2018-03-01 Apple Inc. Systems and Methods for Memory Refresh Timing
US20190074051A1 (en) * 2017-09-07 2019-03-07 Mediatek Inc. Memory system and refresh control method thereof
US10552087B2 (en) * 2018-06-04 2020-02-04 Micron Technology, Inc. Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
KR102578002B1 (ko) * 2018-07-03 2023-09-14 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US10685722B1 (en) * 2019-01-24 2020-06-16 Western Digital Technologies, Inc. Method and system for improving performance of a storage device using asynchronous independent plane read functionality
US11250902B2 (en) * 2019-09-26 2022-02-15 Intel Corporation Method and apparatus to reduce power consumption for refresh of memory devices on a memory module
KR20220003837A (ko) * 2020-07-02 2022-01-11 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
KR20220031793A (ko) 2020-09-03 2022-03-14 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템, 그것을 제어하는 제어기 및 그것의 동작 방법
KR20220091162A (ko) 2020-12-23 2022-06-30 삼성전자주식회사 온도에 대한 리프레쉬 레이트 승수와 상관없는 메모리 장치의 리프레쉬 방법
TWI740773B (zh) * 2021-01-27 2021-09-21 華邦電子股份有限公司 半導體記憶裝置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182857A (ja) * 1993-12-24 1995-07-21 Toshiba Corp マイコンシステム
JPH09213071A (ja) * 1996-02-02 1997-08-15 Hitachi Ltd 半導体記憶装置
US5808952A (en) * 1996-10-28 1998-09-15 Silicon Magic Corporation Adaptive auto refresh
US6212599B1 (en) * 1997-11-26 2001-04-03 Intel Corporation Method and apparatus for a memory control system including a secondary controller for DRAM refresh during sleep mode
US6118719A (en) * 1998-05-20 2000-09-12 International Business Machines Corporation Self-initiated self-refresh mode for memory modules
CN1184644C (zh) * 2001-03-16 2005-01-12 矽统科技股份有限公司 存储器刷新系统
US6693837B2 (en) * 2002-04-23 2004-02-17 Micron Technology, Inc. System and method for quick self-refresh exit with transitional refresh
JP4246971B2 (ja) * 2002-07-15 2009-04-02 富士通マイクロエレクトロニクス株式会社 半導体メモリ
KR100529033B1 (ko) * 2003-05-23 2005-11-17 주식회사 하이닉스반도체 동기식 반도체 메모리 소자
US7236416B2 (en) * 2004-05-21 2007-06-26 Qualcomm Incorporated Method and system for controlling refresh in volatile memories
US7088633B2 (en) 2004-05-27 2006-08-08 Qualcomm Incorporated Method and system for providing seamless self-refresh for directed bank refresh in volatile memories
US7206244B2 (en) * 2004-12-01 2007-04-17 Freescale Semiconductor, Inc. Temperature based DRAM refresh
KR100655076B1 (ko) * 2005-01-20 2006-12-08 삼성전자주식회사 반도체 메모리 장치의 내부 온도 데이터 출력 방법 및그에 따른 내부 온도 데이터 출력회로
US9384818B2 (en) 2005-04-21 2016-07-05 Violin Memory Memory power management
JP4516483B2 (ja) * 2005-06-07 2010-08-04 富士通セミコンダクター株式会社 半導体記憶装置及び情報処理システム
US7313047B2 (en) * 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
CN101000798B (zh) * 2007-01-12 2010-05-19 威盛电子股份有限公司 存储器刷新方法及存储器刷新系统
US8392650B2 (en) * 2010-04-01 2013-03-05 Intel Corporation Fast exit from self-refresh state of a memory device
US9292426B2 (en) * 2010-09-24 2016-03-22 Intel Corporation Fast exit from DRAM self-refresh
US9053812B2 (en) * 2010-09-24 2015-06-09 Intel Corporation Fast exit from DRAM self-refresh
US10157657B2 (en) * 2012-08-28 2018-12-18 Rambus Inc. Selective refresh with software components
KR20140076735A (ko) * 2012-12-13 2014-06-23 삼성전자주식회사 휘발성 메모리 장치 및 메모리 시스템
US9704557B2 (en) * 2013-09-25 2017-07-11 Qualcomm Incorporated Method and apparatus for storing retention time profile information based on retention time and temperature
US9001608B1 (en) * 2013-12-06 2015-04-07 Intel Corporation Coordinating power mode switching and refresh operations in a memory device
KR20160122586A (ko) * 2015-04-14 2016-10-24 에스케이하이닉스 주식회사 반도체장치 및 이를 포함하는 반도체시스템
KR102326018B1 (ko) * 2015-08-24 2021-11-12 삼성전자주식회사 메모리 시스템
KR102354987B1 (ko) * 2015-10-22 2022-01-24 삼성전자주식회사 온도에 따라 셀프 리프레쉬 사이클을 제어하는 리프레쉬 방법
KR102393426B1 (ko) * 2015-11-10 2022-05-04 에스케이하이닉스 주식회사 반도체장치
US9721640B2 (en) * 2015-12-09 2017-08-01 Intel Corporation Performance of additional refresh operations during self-refresh mode
KR102419535B1 (ko) * 2016-03-18 2022-07-13 에스케이하이닉스 주식회사 메모리 장치

Also Published As

Publication number Publication date
KR20180063230A (ko) 2018-06-11
US9875785B2 (en) 2018-01-23
BR112018006477B1 (pt) 2023-03-14
CN108140406B (zh) 2022-03-22
CN108140406A (zh) 2018-06-08
WO2017058417A1 (en) 2017-04-06
KR102593418B1 (ko) 2023-10-23
US20170098470A1 (en) 2017-04-06
EP3357065A1 (en) 2018-08-08
EP3357065B1 (en) 2019-06-26
JP2018530098A (ja) 2018-10-11

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 25/08/2016, OBSERVADAS AS CONDICOES LEGAIS