JP2018513517A - サブアレイを有するマルチビットスピントルクトランスファ磁気抵抗ランダムアクセスメモリ - Google Patents

サブアレイを有するマルチビットスピントルクトランスファ磁気抵抗ランダムアクセスメモリ Download PDF

Info

Publication number
JP2018513517A
JP2018513517A JP2017546972A JP2017546972A JP2018513517A JP 2018513517 A JP2018513517 A JP 2018513517A JP 2017546972 A JP2017546972 A JP 2017546972A JP 2017546972 A JP2017546972 A JP 2017546972A JP 2018513517 A JP2018513517 A JP 2018513517A
Authority
JP
Japan
Prior art keywords
mtj
mtj element
subarray
memory
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017546972A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018513517A5 (enExample
Inventor
ユ・ル
シア・リ
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2018513517A publication Critical patent/JP2018513517A/ja
Publication of JP2018513517A5 publication Critical patent/JP2018513517A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
JP2017546972A 2015-03-11 2016-02-01 サブアレイを有するマルチビットスピントルクトランスファ磁気抵抗ランダムアクセスメモリ Pending JP2018513517A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/645,213 2015-03-11
US14/645,213 US9437272B1 (en) 2015-03-11 2015-03-11 Multi-bit spin torque transfer magnetoresistive random access memory with sub-arrays
PCT/US2016/015932 WO2016144436A2 (en) 2015-03-11 2016-02-01 Multi-bit spin torque transfer magnetoresistive random access memory with sub-arrays

Publications (2)

Publication Number Publication Date
JP2018513517A true JP2018513517A (ja) 2018-05-24
JP2018513517A5 JP2018513517A5 (enExample) 2019-02-28

Family

ID=55404805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017546972A Pending JP2018513517A (ja) 2015-03-11 2016-02-01 サブアレイを有するマルチビットスピントルクトランスファ磁気抵抗ランダムアクセスメモリ

Country Status (5)

Country Link
US (1) US9437272B1 (enExample)
EP (1) EP3268966A2 (enExample)
JP (1) JP2018513517A (enExample)
CN (1) CN107430883B (enExample)
WO (1) WO2016144436A2 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200066848A (ko) * 2018-12-03 2020-06-11 삼성전자주식회사 스핀-궤도 토크 라인을 갖는 반도체 소자
JP2024523986A (ja) * 2021-06-29 2024-07-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 高効率および高保持反転ワイド・ベース二重磁気トンネル接合デバイスのオンチップ集積

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150213867A1 (en) * 2014-01-28 2015-07-30 Qualcomm Incorporated Multi-level cell designs for high density low power gshe-stt mram
US9672935B2 (en) 2014-10-17 2017-06-06 Lattice Semiconductor Corporation Memory circuit having non-volatile memory cell and methods of using
USRE48570E1 (en) 2014-10-17 2021-05-25 Lattice Semiconductor Corporation Memory circuit having non-volatile memory cell and methods of using
US10306008B2 (en) * 2015-09-07 2019-05-28 International Business Machines Corporation Limiting client side data storage based upon client geo-location
DE102016112765B4 (de) * 2016-07-12 2024-04-25 Infineon Technologies Ag Magnetspeicherbauelement und Verfahren zum Betreiben desselben
JP2018147916A (ja) 2017-03-01 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 磁気記憶素子、磁気記憶装置、電子機器、および磁気記憶素子の製造方法
US10534996B2 (en) 2017-04-03 2020-01-14 Gyrfalcon Technology Inc. Memory subsystem in CNN based digital IC for artificial intelligence
US10331368B2 (en) 2017-04-03 2019-06-25 Gyrfalcon Technology Inc. MLC based magnetic random access memory used in CNN based digital IC for AI
US10546234B2 (en) 2017-04-03 2020-01-28 Gyrfalcon Technology Inc. Buffer memory architecture for a CNN based processing unit and creation methods thereof
US10296824B2 (en) 2017-04-03 2019-05-21 Gyrfalcon Technology Inc. Fabrication methods of memory subsystem used in CNN based digital IC for AI
US10331367B2 (en) 2017-04-03 2019-06-25 Gyrfalcon Technology Inc. Embedded memory subsystems for a CNN based processing unit and methods of making
US10331999B2 (en) * 2017-04-03 2019-06-25 Gyrfalcon Technology Inc. Memory subsystem in CNN based digital IC for artificial intelligence
US20190066746A1 (en) 2017-08-28 2019-02-28 Qualcomm Incorporated VARYING ENERGY BARRIERS OF MAGNETIC TUNNEL JUNCTIONS (MTJs) IN DIFFERENT MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) ARRAYS IN A SEMICONDUCTOR DIE TO FACILITATE USE OF MRAM FOR DIFFERENT MEMORY APPLICATIONS
JP6829172B2 (ja) 2017-09-20 2021-02-10 キオクシア株式会社 半導体記憶装置
US10403343B2 (en) * 2017-12-29 2019-09-03 Spin Memory, Inc. Systems and methods utilizing serial configurations of magnetic memory devices
US10803916B2 (en) 2017-12-29 2020-10-13 Spin Memory, Inc. Methods and systems for writing to magnetic memory devices utilizing alternating current
US11968843B2 (en) 2018-06-28 2024-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Processing core and MRAM memory unit integrated on a single chip
US10559338B2 (en) * 2018-07-06 2020-02-11 Spin Memory, Inc. Multi-bit cell read-out techniques
US10692569B2 (en) 2018-07-06 2020-06-23 Spin Memory, Inc. Read-out techniques for multi-bit cells
US10559357B1 (en) * 2018-08-06 2020-02-11 Lattice Semiconductor Corporation Memory circuit having non-volatile memory cell and methods of using
US10847198B2 (en) * 2018-11-01 2020-11-24 Spin Memory, Inc. Memory system utilizing heterogeneous magnetic tunnel junction types in a single chip
US10971681B2 (en) * 2018-12-05 2021-04-06 Spin Memory, Inc. Method for manufacturing a data recording system utilizing heterogeneous magnetic tunnel junction types in a single chip
US10868234B2 (en) * 2018-12-12 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Storage device having magnetic tunnel junction cells of different sizes, and method of forming storage device
JP7211273B2 (ja) * 2019-06-17 2023-01-24 株式会社アイシン 半導体記憶装置
US11514962B2 (en) * 2020-11-12 2022-11-29 International Business Machines Corporation Two-bit magnetoresistive random-access memory cell
CN116312669B (zh) * 2021-12-20 2025-08-01 长鑫存储技术有限公司 存储阵列、存储单元及其数据读写方法
US12437791B2 (en) 2023-07-11 2025-10-07 Honeywell International Inc. Magneto resistive memory for monolithic data processing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100024765A (ko) * 2008-08-26 2010-03-08 주식회사 하이닉스반도체 멀티 비트 자기 메모리 셀 및 그 제조 방법
WO2013055473A1 (en) * 2011-10-12 2013-04-18 International Business Machines Corporation Multi-bit spin-momentum-transfer magnetoresistence random access memory with single magnetic-tunnel-junction stack
JP2014041693A (ja) * 2010-04-28 2014-03-06 Hitachi Ltd 半導体記憶装置
JP2014229325A (ja) * 2013-05-20 2014-12-08 富士通株式会社 メモリ装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW578149B (en) 2002-09-09 2004-03-01 Ind Tech Res Inst High density magnetic random access memory
US7286378B2 (en) * 2003-11-04 2007-10-23 Micron Technology, Inc. Serial transistor-cell array architecture
US7102920B2 (en) * 2004-03-23 2006-09-05 Hewlett-Packard Development Company, L.P. Soft-reference three conductor magnetic memory storage device
US20060039183A1 (en) 2004-05-21 2006-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-sensing level MRAM structures
US20080246104A1 (en) * 2007-02-12 2008-10-09 Yadav Technology High Capacity Low Cost Multi-State Magnetic Memory
US8027206B2 (en) * 2009-01-30 2011-09-27 Qualcomm Incorporated Bit line voltage control in spin transfer torque magnetoresistive random access memory
US8587993B2 (en) * 2009-03-02 2013-11-19 Qualcomm Incorporated Reducing source loading effect in spin torque transfer magnetoresisitive random access memory (STT-MRAM)
WO2011087038A1 (ja) * 2010-01-13 2011-07-21 株式会社日立製作所 磁気メモリ、磁気メモリの製造方法、及び、磁気メモリの駆動方法
US8446753B2 (en) * 2010-03-25 2013-05-21 Qualcomm Incorporated Reference cell write operations at a memory
US8279662B2 (en) 2010-11-11 2012-10-02 Seagate Technology Llc Multi-bit magnetic memory with independently programmable free layer domains
KR101215951B1 (ko) 2011-03-24 2013-01-21 에스케이하이닉스 주식회사 반도체 메모리 및 그 형성방법
WO2012119449A1 (zh) * 2011-09-30 2012-09-13 华为技术有限公司 在混合存储环境下配置存储设备的方法和系统
US8804413B2 (en) 2012-02-07 2014-08-12 Qualcomm Incorporated Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing
US9196334B2 (en) 2012-04-19 2015-11-24 Qualcomm Incorporated Hierarchical memory magnetoresistive random-access memory (MRAM) architecture
CN103810118B (zh) * 2014-02-28 2016-08-17 北京航空航天大学 一种stt-mram缓存设计方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100024765A (ko) * 2008-08-26 2010-03-08 주식회사 하이닉스반도체 멀티 비트 자기 메모리 셀 및 그 제조 방법
JP2014041693A (ja) * 2010-04-28 2014-03-06 Hitachi Ltd 半導体記憶装置
WO2013055473A1 (en) * 2011-10-12 2013-04-18 International Business Machines Corporation Multi-bit spin-momentum-transfer magnetoresistence random access memory with single magnetic-tunnel-junction stack
JP2014229325A (ja) * 2013-05-20 2014-12-08 富士通株式会社 メモリ装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200066848A (ko) * 2018-12-03 2020-06-11 삼성전자주식회사 스핀-궤도 토크 라인을 갖는 반도체 소자
KR102576209B1 (ko) * 2018-12-03 2023-09-07 삼성전자주식회사 스핀-궤도 토크 라인을 갖는 반도체 소자
JP2024523986A (ja) * 2021-06-29 2024-07-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 高効率および高保持反転ワイド・ベース二重磁気トンネル接合デバイスのオンチップ集積

Also Published As

Publication number Publication date
EP3268966A2 (en) 2018-01-17
CN107430883B (zh) 2021-03-12
US20160267957A1 (en) 2016-09-15
US9437272B1 (en) 2016-09-06
WO2016144436A3 (en) 2016-11-03
WO2016144436A2 (en) 2016-09-15
CN107430883A (zh) 2017-12-01

Similar Documents

Publication Publication Date Title
US9437272B1 (en) Multi-bit spin torque transfer magnetoresistive random access memory with sub-arrays
US10198221B2 (en) Methods of operating semiconductor memory devices with selective write-back of data for error scrubbing and related devices
US11438016B2 (en) Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same
US10156995B2 (en) Semiconductor memory devices and methods of operating the same
US10671478B2 (en) Scrubbing controllers of semiconductor memory devices, semiconductor memory devices and methods of operating the same
KR101772019B1 (ko) 저항성 메모리 장치 및 저항성 메모리 장치의 리프레시 제어 방법
KR102193682B1 (ko) 선택적 ecc 기능을 갖는 반도체 메모리 장치
US9311997B2 (en) Resistive memory device with word lines coupled to multiple sink transistors
US10002045B2 (en) Semiconductor memory devices having input/output gating circuit and memory systems including the same
US10360977B2 (en) Tailoring current magnitude and duration during a programming pulse for a memory device
JP2018513517A5 (enExample)
US20170206165A1 (en) Method for accessing heterogeneous memories and memory module including heterogeneous memories
TWI684295B (zh) 電子裝置
US8873328B2 (en) Nonvolatile memory device including sudden power off detection circuit and sudden power off detection method thereof
KR20140049108A (ko) 저항성 메모리 장치 및 그것의 구동방법
KR102049258B1 (ko) 레퍼런스 셀을 포함하는 불휘발성 메모리 장치 및 그것의 데이터 관리 방법 및
US20150074489A1 (en) Semiconductor storage device and memory system
US10204700B1 (en) Memory systems and methods of operating semiconductor memory devices
US20140340959A1 (en) Nonvolatile memory device and data processing method thereof
US11669393B2 (en) Memory device for swapping data and operating method thereof
US12327046B2 (en) Data retention-specific refresh read
KR20250148211A (ko) 메모리 장치 및 이의 동작 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170912

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190115

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190115

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200106

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20200406

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200513

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20201005