JP2018506232A5 - - Google Patents
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- Publication number
- JP2018506232A5 JP2018506232A5 JP2017540862A JP2017540862A JP2018506232A5 JP 2018506232 A5 JP2018506232 A5 JP 2018506232A5 JP 2017540862 A JP2017540862 A JP 2017540862A JP 2017540862 A JP2017540862 A JP 2017540862A JP 2018506232 A5 JP2018506232 A5 JP 2018506232A5
- Authority
- JP
- Japan
- Prior art keywords
- clock
- line
- sda
- clock signal
- slave device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 13
- 230000005540 biological transmission Effects 0.000 claims 12
- 230000007704 transition Effects 0.000 claims 10
- 230000000873 masking effect Effects 0.000 claims 2
- 238000011084 recovery Methods 0.000 claims 2
- 230000011664 signaling Effects 0.000 claims 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/616,572 US9684624B2 (en) | 2014-01-14 | 2015-02-06 | Receive clock calibration for a serial bus |
| US14/616,572 | 2015-02-06 | ||
| PCT/US2016/014977 WO2016126466A1 (en) | 2015-02-06 | 2016-01-26 | Receive clock calibration for a serial bus |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018506232A JP2018506232A (ja) | 2018-03-01 |
| JP2018506232A5 true JP2018506232A5 (enExample) | 2019-02-21 |
| JP6612885B2 JP6612885B2 (ja) | 2019-11-27 |
Family
ID=55300809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017540862A Active JP6612885B2 (ja) | 2015-02-06 | 2016-01-26 | シリアルバスのための受信クロック較正 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP3254203B1 (enExample) |
| JP (1) | JP6612885B2 (enExample) |
| KR (1) | KR102445344B1 (enExample) |
| CN (1) | CN107209743B (enExample) |
| WO (1) | WO2016126466A1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10128964B2 (en) | 2016-03-10 | 2018-11-13 | Qualcomm Incorporated | Multiphase preamble data sequences for receiver calibration and mode data signaling |
| KR102495030B1 (ko) * | 2018-11-15 | 2023-02-06 | 매그나칩 반도체 유한회사 | 클록 장애를 복원하는 수신 장치 및 이를 포함하는 전송 시스템 |
| WO2020117303A1 (en) | 2018-12-03 | 2020-06-11 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3682359B1 (en) | 2018-12-03 | 2021-01-06 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| US10894423B2 (en) | 2018-12-03 | 2021-01-19 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3687820B1 (en) | 2018-12-03 | 2022-03-23 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| EP3695334A1 (en) | 2018-12-03 | 2020-08-19 | Hewlett Packard Enterprise Development Company LP | Logic circuitry |
| CA3121146C (en) | 2018-12-03 | 2024-05-28 | Hewlett-Packard Development Company, L.P. | Logic circuitry package for controlling ic2 traffic |
| US11338586B2 (en) | 2018-12-03 | 2022-05-24 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| CN113165389A (zh) | 2018-12-03 | 2021-07-23 | 惠普发展公司，有限责任合伙企业 | 逻辑电路系统封装 |
| EP3681723B1 (en) * | 2018-12-03 | 2021-07-28 | Hewlett-Packard Development Company, L.P. | Logic circuitry |
| MX2021005988A (es) | 2018-12-03 | 2021-07-06 | Hewlett Packard Development Co | Conjunto de circuitos logicos. |
| US10572438B1 (en) * | 2019-03-07 | 2020-02-25 | Qualcomm Incorporated | Dynamic optimal data sampling time on a multi-drop bus |
| JP2020167634A (ja) * | 2019-03-29 | 2020-10-08 | ソニーセミコンダクタソリューションズ株式会社 | 送信装置、受信装置、及び伝送システム |
| DE102019112447A1 (de) * | 2019-05-13 | 2020-11-19 | Jenoptik Optical Systems Gmbh | Verfahren und Auswerteeinheit zur Ermittlung eines Zeitpunkts einer Flanke in einem Signal |
| EP3844000B1 (en) | 2019-10-25 | 2023-04-12 | Hewlett-Packard Development Company, L.P. | Logic circuitry package |
| CN110928826A (zh) * | 2019-11-21 | 2020-03-27 | 中电科仪器仪表有限公司 | 一种低功耗数据传送模式的dphy总线协议解码与触发的方法 |
| US10958412B1 (en) * | 2020-01-22 | 2021-03-23 | Infineon Technologies Ag | Communication using edge timing in a signal |
| EP4031997A1 (en) | 2020-04-30 | 2022-07-27 | Hewlett-Packard Development Company, L.P. | Logic circuitry package for print apparatus |
| CN116418436A (zh) * | 2021-12-29 | 2023-07-11 | 国民技术股份有限公司 | 用于低压i2c通讯的校准装置、系统和方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6839393B1 (en) * | 1999-07-14 | 2005-01-04 | Rambus Inc. | Apparatus and method for controlling a master/slave system via master device synchronization |
| US7089338B1 (en) * | 2002-07-17 | 2006-08-08 | Cypress Semiconductor Corp. | Method and apparatus for interrupt signaling in a communication network |
| JP5287858B2 (ja) * | 2008-07-31 | 2013-09-11 | 富士通株式会社 | データ転送装置、データ送信装置、データ受信装置およびデータ転送方法 |
| CN101667167B (zh) * | 2009-10-23 | 2011-05-11 | 威盛电子股份有限公司 | 通用串行总线装置以及其校正方法 |
| US9137008B2 (en) * | 2013-07-23 | 2015-09-15 | Qualcomm Incorporated | Three phase clock recovery delay calibration |
-
2016
- 2016-01-26 JP JP2017540862A patent/JP6612885B2/ja active Active
- 2016-01-26 CN CN201680008675.8A patent/CN107209743B/zh active Active
- 2016-01-26 EP EP16703033.7A patent/EP3254203B1/en active Active
- 2016-01-26 KR KR1020177021437A patent/KR102445344B1/ko active Active
- 2016-01-26 WO PCT/US2016/014977 patent/WO2016126466A1/en not_active Ceased
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