JP2015186259A5 - - Google Patents

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Publication number
JP2015186259A5
JP2015186259A5 JP2015054426A JP2015054426A JP2015186259A5 JP 2015186259 A5 JP2015186259 A5 JP 2015186259A5 JP 2015054426 A JP2015054426 A JP 2015054426A JP 2015054426 A JP2015054426 A JP 2015054426A JP 2015186259 A5 JP2015186259 A5 JP 2015186259A5
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JP
Japan
Prior art keywords
pulse
voltage
data line
slave device
driving
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JP2015054426A
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English (en)
Japanese (ja)
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JP2015186259A (ja
JP5992565B2 (ja
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Priority claimed from US14/318,741 external-priority patent/US9210015B2/en
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Publication of JP2015186259A publication Critical patent/JP2015186259A/ja
Publication of JP2015186259A5 publication Critical patent/JP2015186259A5/ja
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Publication of JP5992565B2 publication Critical patent/JP5992565B2/ja
Expired - Fee Related legal-status Critical Current
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JP2015054426A 2014-03-20 2015-03-18 エッジに基づいた通信 Expired - Fee Related JP5992565B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201461955997P 2014-03-20 2014-03-20
US61/955,997 2014-03-20
US14/318,741 US9210015B2 (en) 2014-03-20 2014-06-30 Edge-based communication
US14/318,741 2014-06-30

Publications (3)

Publication Number Publication Date
JP2015186259A JP2015186259A (ja) 2015-10-22
JP2015186259A5 true JP2015186259A5 (enExample) 2016-03-10
JP5992565B2 JP5992565B2 (ja) 2016-09-14

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Family Applications (1)

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JP2015054426A Expired - Fee Related JP5992565B2 (ja) 2014-03-20 2015-03-18 エッジに基づいた通信

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US (2) US9210015B2 (enExample)
JP (1) JP5992565B2 (enExample)
KR (1) KR101679141B1 (enExample)

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US10887074B1 (en) * 2019-08-02 2021-01-05 Infineon Technologies Ag Full duplex communication using edge timing in a signal
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