JP2018503242A - ユニット固有パターニングの自動光学検査 - Google Patents
ユニット固有パターニングの自動光学検査 Download PDFInfo
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Abstract
Description
本開示は、2014年11月19日付けで出願された米国仮特許出願第62/081,676号の利益を主張し、この米国仮特許出願の開示の全体が参照によって本明細書に援用される。
本開示は、パネル化されたパッケージング及びウェハ・レベル・チップ・スケール・パッケージ(WLCSP)を含む半導体パッケージと、製造中の半導体パッケージの自動光学検査又は目視検査に関する。
Claims (20)
- 複数の特有の半導体パッケージのための自動光学検査(AOI)の方法であって、
再構成ウェハとして形成された複数の半導体ダイを準備することと、
前記複数の半導体ダイのうちの1つずつの上に、ユニット固有パターンのうちの1つずつがそれぞれの対応する半導体ダイに合うようにカスタマイズされているユニット固有パターンを形成することにより、複数のユニット固有パターンを形成することと、
前記複数のユニット固有パターンのうちの1つずつに対する画像を獲得することにより複数の画像を獲得することと、
前記複数のユニット固有パターンのうちの1つずつに対して特有の参照標準を作成することにより複数の特有の参照標準を作成することと、
前記複数の特有の参照標準のうちの1つずつを前記複数のユニット固有パターンのうちの1つずつに対する前記複数の画像のうちの対応する1つと比較することにより前記複数のユニット固有パターンの中の欠陥を検出することと、
前記複数の特有の半導体パッケージを形成するために前記再構成ウェハを単体化することと、
を含む、自動光学検査(AOI)の方法。 - 前記複数の画像を導電性パス及び非導電性パスを表示する複数のバイナリ画像に変換することにより、前記複数のユニット固有パターンのうちの1つずつに対する前記複数の画像を前処理することと、
XY座標の複数のネットリストとして前記複数の特有の参照標準を作成することと、
前記XY座標の複数のネットリストのうちの1つを前記複数のユニット固有パターンのうちの1つずつに対する前記複数のバイナリ画像のうちの1つにマッピングすることにより、前記XY座標の複数のネットリストのうちの1つを前記複数のユニット固有パターンのうちの1つずつに対する前記複数のバイナリ画像のうちの対応する1つと比較することと、
を更に含む、請求項1に記載のAOIの方法。 - 電気的接続性の正当性を確認するために探索アルゴリズム又は接続性アルゴリズムを使用して前記バイナリ画像の前記導電性パスの内部で前記複数のネットリストのうちの1つの中のXY座標の間のパスを見つけることを更に含む、請求項2に記載のAOIの方法。
- 画素展開アルゴリズム又は画素充填アルゴリズムを使用して、前記複数のネットリストのうちの別個のネットが接続されていないことを検証することを更に含む、請求項2に記載のAOIの方法。
- 前記複数の半導体ダイの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することと、
前記複数のユニット固有パターンのうちの1つずつに対する前記複数のCAD画像をラスタライズ又はモデリングすることによって、複数の動的参照画像を作成することにより前記複数の特有の参照標準を作成することと、
を更に含む、請求項1に記載のAOIの方法。 - 前記複数のユニット固有パターンの中の欠陥を検出するために前記複数の動的参照画像のうちの1つを前記複数のカスタマイズされたパターンのうちの1つずつに対する前記複数の画像のうちの対応する1つと比較する前に、グレースケール画像を作成するためにステップ応答を使用して前記複数のユニット固有パターンのうちの1つずつに対する前記複数のCAD画像をラスタライズすることを更に含む、請求項5に記載のAOIの方法。
- 前記複数の半導体ダイのうちの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することを更に含み、
前記複数の特有の参照標準は、抽出されたCAD幾何形状を共通空間の中に作成するために前記複数のCAD画像から抽出された幾何形状を含み、
前記複数のユニット固有パターンのうちの1つずつに対する前記複数の画像は、抽出された画像幾何形状を前記共通空間の中に作成するために前記複数の画像から抽出された幾何形状を含み、
前記複数のユニット固有パターンの中の欠陥を検出することは、前記共通空間の中の抽出されたCAD幾何形状と前記抽出された画像幾何形状とを比較することにより前記複数のユニット固有パターンの中の欠陥を検出することを含む、請求項1に記載のAOIの方法。 - 前記複数の半導体ダイのうちの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することと、
前記複数のユニット固有パターンに対する複数のバイナリ画像を形成するために、前記ユニット固有パターンの前記複数の画像をグレースケール画像からバイナリ画像に変換することと、
前記複数のCAD画像からのバイナリデータと前記複数のユニット固有パターンに対する前記複数のバイナリ画像とを比較することにより、前記複数のユニット固有パターンの中の欠陥を検出することと、
を更に含む、請求項1に記載のAOIの方法。 - 1つ以上の再分配層(RDL)、トレース、ビア、ピラー、カラム、アンダー・バンプ・メタライゼーション(UBM)、又はバンプを備える前記複数のユニット固有パターンを形成することを更に含む、請求項1に記載のAOIの方法。
- 前記複数のユニット固有パターンの中の欠陥を検出することから、前記複数の特有の半導体パッケージのうち既知の良好なユニットがどれであるかを判定することを更に含む、請求項1に記載のAOIの方法。
- 複数の特有の半導体パッケージのための自動光学検査(AOI)の方法であって、
再構成ウェハに接して形成された複数のユニット固有パターンの1つずつに対する画像を獲得することによって複数の画像を獲得することと、
前記複数のユニット固有パターンの1つずつに対する特有の参照標準を作成することにより複数の特有の参照標準を作成することと、
前記複数の特有の参照標準のうちの1つを前記複数のユニット固有パターンのうちの1つずつの前記複数の画像のうちの対応する1つと比較することにより、前記複数のユニット固有パターンの中の欠陥を検出することと、
を含む、自動光学検査(AOI)の方法。 - 前記複数の画像を導電性パス及び非導電性パスを表示する複数のバイナリ画像に変換することにより、前記複数のユニット固有パターンのうちの1つずつに対する前記複数の画像を前処理することと、
XY座標の複数のネットリストとして前記複数の特有の参照標準を作成することと、
前記XY座標の複数のネットリストのうちの1つを前記複数のユニット固有パターンのうちの1つずつに対する前記複数のバイナリ画像のうちの1つにマッピングすることにより、前記XY座標の複数のネットリストのうちの1つを前記複数のユニット固有パターンのうちの1つずつに対する前記複数のバイナリ画像のうちの対応する1つと比較することと、
を更に含む、請求項11に記載のAOIの方法。 - 電気的接続性の正当性を確認するために探索アルゴリズム又は接続性アルゴリズムを使用して前記バイナリ画像の前記導電性パスの内部で前記複数のネットリストのうちの1つのXY座標の間のパスを見つけることを更に含む、請求項12に記載のAOIの方法。
- 画素展開アルゴリズム又は画素充填アルゴリズムを使用して、前記複数のネットリストのうちの別個のネットが接続されていないことを検証することを更に含む、請求項12に記載のAOIの方法。
- 前記複数の半導体ダイの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することと、
前記複数のユニット固有パターンのうちの1つずつに対する前記複数のCAD画像をラスタライズ又はモデリングすることによって、複数の動的参照画像を作成することにより前記複数の特有の参照標準を作成することと、
を更に含む、請求項11に記載のAOIの方法。 - 前記複数のユニット固有パターンの中の欠陥を検出するために前記複数の動的参照画像のうちの1つを前記複数のカスタマイズされたパターンのうちの1つずつに対する前記複数の画像のうちの対応する1つと比較する前に、グレースケール画像を作成するためにステップ応答を使用して前記複数のユニット固有パターンのうちの1つずつに対する前記複数のCAD画像をラスタライズすることを更に含む、請求項15に記載のAOIの方法。
- 前記複数の半導体ダイのうちの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することを更に含み、
前記複数の特有の参照標準は、抽出されたCAD幾何形状を共通空間の中に作成するためにCAD画像から抽出された幾何形状を含み、
前記複数のユニット固有パターンのうちの1つずつに対する前記複数の画像は、抽出された画像幾何形状を前記共通空間の中に作成するために前記複数の画像から抽出された幾何形状を含み、
前記複数のユニット固有パターンの中の欠陥を検出することは、前記共通空間の中の抽出されたCAD幾何形状と前記抽出された画像幾何形状とを比較することにより前記複数のユニット固有パターンの中の欠陥を検出することを含む、請求項11に記載のAOIの方法。 - 前記複数の半導体ダイのうちの1つずつの上に形成された前記ユニット固有パターンのうちの1つずつに対応するCAD画像を含む複数のコンピュータ支援設計(CAD)画像を準備することと、
前記複数のユニット固有パターンに対する複数のバイナリ画像を形成するために、前記ユニット固有パターンの前記複数の画像をグレースケール画像からバイナリ画像に変換することと、
前記複数のCAD画像からのバイナリデータと前記複数のユニット固有パターンに対する前記複数のバイナリ画像とを比較することにより、前記複数のユニット固有パターンの中の欠陥を検出することと、
を更に含む、請求項11に記載のAOIの方法。 - 1つ以上の再分配層(RDL)、トレース、ビア、ピラー、カラム、アンダー・バンプ・メタライゼーション(UBM)、又はバンプを備える前記複数のユニット固有パターンを形成することを更に含む、請求項11に記載のAOIの方法。
- 前記複数のユニット固有パターンの中の欠陥を検出することから、前記複数の特有の半導体パッケージのうち既知の良好なユニットがどれであるかを判定することを更に含む、請求項11に記載のAOIの方法。
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US20160141213A1 (en) | 2016-05-19 |
KR102595447B1 (ko) | 2023-10-27 |
IL252341B (en) | 2020-11-30 |
US9401313B2 (en) | 2016-07-26 |
JP6921257B2 (ja) | 2021-08-18 |
CN107004616A (zh) | 2017-08-01 |
US20160336241A1 (en) | 2016-11-17 |
JP2020080193A (ja) | 2020-05-28 |
JP6685301B2 (ja) | 2020-04-22 |
IL252341A0 (en) | 2017-07-31 |
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CN107004616B (zh) | 2022-03-04 |
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