JP2018037649A - ドリフト空間にp層を有するnチャネルバイポーラパワー半導体素子 - Google Patents
ドリフト空間にp層を有するnチャネルバイポーラパワー半導体素子 Download PDFInfo
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- JP2018037649A JP2018037649A JP2017135446A JP2017135446A JP2018037649A JP 2018037649 A JP2018037649 A JP 2018037649A JP 2017135446 A JP2017135446 A JP 2017135446A JP 2017135446 A JP2017135446 A JP 2017135446A JP 2018037649 A JP2018037649 A JP 2018037649A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 320
- 239000002019 doping agent Substances 0.000 claims abstract description 69
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 239000012212 insulator Substances 0.000 claims abstract description 17
- 230000007704 transition Effects 0.000 claims description 29
- 230000000903 blocking effect Effects 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 11
- 230000007423 decrease Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 description 14
- 229910052733 gallium Inorganic materials 0.000 description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- 239000002800 charge carrier Substances 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 4
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910004613 CdTe Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000011163 secondary particle Substances 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
10 半導体ボディ
11 第1の負荷端子
12 第2の負荷端子
13 トレンチ
14 メサゾーン
16 アクティブセルフィールド
17 トレンチ
18 エッジターミネーションゾーン
19 エッジ
101 ソース領域
102 チャネル領域
103 障壁領域
104 第1のドリフト領域
105 第2のドリフト領域
107 バッファ領域
108 エミッタ領域
131 制御電極
132 絶縁体
171 トレンチ電極
172 トレンチ絶縁体
181 ガードリング
1012 第1の接合
1023 第2の接合
1024 トランジション
1034 第3の接合
1041 サブ領域
1042 ボーダー層部分
1047 別の接合
1057 トランジション
Claims (25)
- バイポーラパワー半導体素子(1)であって、前記パワー半導体素子(1)の第1の負荷端子(11)と第2の負荷端子(12)との間に負荷電流を通すように構成された半導体ボディ(10)を有し、
第1の導電型の、前記第1の負荷端子(11)に電気的に接続されているソース領域(101)と、
前記半導体ボディ(10)内に実装され、第2の導電型を有し、前記ソース領域(101)を前記半導体ボディ(10)のその他の部分(103)から隔てる半導体チャネル領域(102)と、
前記半導体ボディ(10)内を延び方向(Z)に延び、前記半導体チャネル領域(102)に隣接して配置された、第1のトレンチ型のトレンチ(13)であって、絶縁体(132)によって前記半導体ボディ(10)から絶縁されている制御電極(131)を含み、前記制御電極(131)は、前記半導体チャネル領域(102)内の前記負荷電流の経路を制御するように構成されている、前記トレンチ(13)と、
前記半導体ボディ(10)内に実装され、前記第2の負荷端子(12)に電気的に接続されている、前記第2の導電型の少なくとも1つのエミッタ領域(108)と、を更に含み、
前記半導体ボディ(10)は更に、
前記第1の導電型の障壁領域(103)と、
前記第2の導電型の第1のドリフト領域(104)を少なくとも有するドリフト空間であって、前記障壁領域(103)は前記第1のドリフト領域(104)を前記半導体チャネル領域(102)と結合している、前記ドリフト空間と、
一方の側の前記半導体ボディ(10)の前記ドリフト空間と、他方の側の前記エミッタ領域(108)との間に配置されている、前記第1の導電型のバッファ領域(107)と、を含み、
前記第1のドリフト領域(104)は、前記延び方向(Z)の全長(DZ4)が、前記半導体ボディ(10)の、前記延び方向(Z)の全長の少なくとも5%である、
バイポーラパワー半導体素子(1)。 - 前記ソース領域(101)と前記半導体チャネル領域(102)との間のトランジションが第1の接合(1012)を形成し、
前記障壁領域(103)と前記チャネル領域(102)との間のトランジションが第2の接合(1023)を形成し、
前記第1のトレンチ型の前記トレンチ(13)が、前記半導体ボディ(10)内を前記延び方向(Z)に、前記第1の接合(1012)及び前記第2の接合(1023)のそれぞれより遠くまで延びる、
請求項1に記載のバイポーラパワー半導体素子(1)。 - 前記第1のトレンチ型の前記トレンチ(13)に含まれる前記制御電極(131)は、前記延び方向(Z)に、前記第1の接合(1012)及び前記第2の接合(1023)のそれぞれより遠くまで延びる、請求項2に記載のバイポーラパワー半導体素子(1)。
- 前記第1のトレンチ型の前記トレンチ(13)は、前記半導体ボディ(10)の表面(10−1)から測定される、前記延び方向(Z)の全長(DZT)を有し、前記障壁領域(103)と前記第1のドリフト領域(104)との間のトランジションによって形成された第3の接合(1034)が、前記全長(DZT)の50%〜95%の範囲のレベル以内で配置されている、請求項1〜3のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記第1のトレンチ型の前記トレンチ(13)は、前記半導体ボディ(10)の表面(10−1)から測定される、前記延び方向(Z)の全長(DZT)を有し、前記延び方向の、前記第1のドリフト領域(104)から前記半導体ボディ(10)のその他の部分にかけてのトランジションが、前記全長(DZT)の200%を超えるレベル以内で配置されている、請求項1〜4のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記第1のドリフト領域(104)は、前記トレンチ(13)の少なくとも下部部分と接触し、前記下部部分は、前記延び方向(Z)に、前記第1のトレンチ型の前記トレンチ(13)の前記全長(DZT)の少なくとも10%に及ぶ、請求項1〜5のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記第1のトレンチ型の複数のトレンチ(13)を含み、前記トレンチ(13)は、第1の横方向(X)に沿って配置されている、請求項1〜6のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 第1の横方向(X)に沿って配置された第2のトレンチ型の複数のトレンチ(17)を含み、前記第2のトレンチ型の各トレンチ(17)は、前記半導体ボディ(10)内を前記延び方向(Z)に延び、トレンチ絶縁体(172)によって前記半導体ボディ(10)から絶縁されたトレンチ電極(171)を含む、請求項1〜7のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記トレンチ(13、17)のそれぞれは、前記半導体チャネル領域(102)、及び前記障壁領域(103)のそれぞれを横切り、前記第1のドリフト領域(104)内に延びる、請求項7又は8に記載のバイポーラパワー半導体素子(1)。
- 各メサゾーン(14)が、隣接するトレンチ(13、17)同士を互いに隔て、各メサゾーン(14)の幅(WM)は、10nm〜10μmの範囲にある、請求項7〜9のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 各メサゾーン(14)は、前記ソース領域(101)、前記半導体チャネル領域(102)、前記障壁領域(103)、及び前記第1のドリフト領域(104)のそれぞれの一部を含む、請求項10に記載のバイポーラパワー半導体素子(1)。
- バイポーラパワー半導体素子(1)であって、前記パワー半導体素子(1)の第1の負荷端子(11)と第2の負荷端子(12)との間に負荷電流を通すように構成された半導体ボディ(10)を有し、
前記第1の負荷端子(11)に電気的に接続されている、第1の導電型のソース領域(101)と、
前記半導体ボディ(10)内に実装され、第2の導電型を有し、前記ソース領域(101)を前記半導体ボディ(10)のその他の部分から隔てている半導体チャネル領域(102)と、
絶縁体(132)によって前記半導体ボディ(10)から絶縁された制御電極(131)であって、前記半導体チャネル領域(102)内の前記負荷電流の経路を制御するように構成されている前記制御電極(131)と、
前記半導体ボディ(10)内に実装され、前記第2の負荷端子(12)に電気的に接続されている、前記第2の導電型の少なくとも1つのエミッタ領域(108)と、を更に含み、
前記半導体ボディ(10)は更に、
前記半導体チャネル領域(102)と結合されていて前記第2の導電型を有する第1のドリフト領域(104)を少なくとも有するドリフト空間と、
一方の側の前記半導体ボディ(10)の前記ドリフト空間と、他方の側の前記エミッタ領域(108)との間に配置されている前記第1の導電型のバッファ領域(107)と、を含み、
前記第1のドリフト領域(104)は、延び方向(Z)の全長(DZ4)が、前記半導体ボディ(10)の、前記延び方向(Z)の全長の少なくとも5%である、
バイポーラパワー半導体素子(1)。 - 前記第1のドリフト領域(104)は、前記半導体チャネル領域(102)に接触して配置されている、請求項12に記載のバイポーラパワー半導体素子(1)。
- 前記半導体ボディ(10)内を前記延び方向(Z)に延び、前記半導体チャネル領域(102)に隣接して配置されている、第1のトレンチ型のトレンチ(13)を更に含み、前記トレンチ(13)は、前記制御電極(131)と前記絶縁体(132)の少なくとも一部とを含む、請求項13に記載のバイポーラパワー半導体素子(1)。
- 前記パワー半導体素子(1)は、阻止状態及び導通状態で動作可能であり、
前記半導体ボディ(10)の、前記延び方向(Z)の全長は、10個の均等な1/10部分の合計になり、
前記パワー半導体素子(1)が前記阻止状態で動作している場合には、前記第1の負荷端子(11)と前記第2の負荷端子(12)との間に印加される阻止電圧によって引き起こされる電界強度の絶対最大値が、前記半導体ボディ(10)の全長の前記1/10部分のうちの中央の6個の部分(CP)の範囲内で発生する、
請求項1〜14のいずれか一項に記載のバイポーラパワー半導体素子(1)。 - 前記ドリフト空間は更に、前記第1の導電型の第2のドリフト領域(105)を含み、前記第2のドリフト領域(105)は、前記第1のドリフト領域(104)に接触して配置され、前記延び方向(Z)に、前記第1のドリフト領域(104)より遠くまで延びる、請求項1〜15のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記バッファ領域(107)は、前記第2のドリフト領域(105)に接触して配置されている、請求項16に記載のバイポーラパワー半導体素子(1)。
- 前記バッファ領域(107)は前記延び方向(Z)に全長(DZ7)を有し、前記全長(DZ7)の少なくとも50%にわたってドーパント濃度が増加する、請求項1〜17のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記第1のドリフト領域(104)のドーパント濃度は、前記第1のドリフト領域(104)の全長(DZ4)の少なくとも50%にわたって減少する、請求項1〜18のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記第1のドリフト領域(104)のドーパント濃度は、1×1013cm−3〜2×1015cm−3の範囲にある、請求項1〜19のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- アクティブセルフィールド(16)と、前記アクティブセルフィールド(16)を囲むエッジターミネーションゾーン(18)と、を更に含み、前記第2の導電型を有する前記第1のドリフト領域(104)は、前記アクティブセルフィールド(16)内に独占的に配置されている、請求項1〜20のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記負荷電流を通す為に前記半導体チャネル領域(102)内に反転チャネルを誘導するように更に構成されている、請求項1〜21のいずれか一項に記載のバイポーラパワー半導体素子(1)。
- 前記ドリフト空間は1つ以上のサブ領域(1041)を含み、前記1つ以上のサブ領域(1041)のそれぞれは、
前記ドリフト空間の総体積への寄与分が10%未満であり、
前記ドリフト空間の前記第1のドリフト領域(104)のドーパント濃度の少なくとも100倍のドーパント濃度で、前記第1又は前記第2の導電型を有する、
請求項1〜22のいずれか一項に記載のバイポーラパワー半導体素子(1)。 - 半導体ボディ(10)を有するバイポーラパワー半導体素子(1)の加工方法であって、
第1の導電型のソース領域(101)を作成するステップと、
第2の導電型の半導体チャネル領域(102)を前記半導体ボディ(10)内に作成するステップであって、前記半導体チャネル領域(102)は前記ソース領域(101)を前記半導体ボディ(10)のその他の部分から隔てる、前記半導体チャネル領域(102)を作成するステップと、
前記半導体チャネル領域(102)内の負荷電流の経路を制御する制御電極(131)と、前記制御電極(131)を前記半導体ボディ(10)から絶縁する絶縁体(132)と、を設けるステップと、
前記第2の導電型の少なくとも1つのエミッタ領域(108)を前記半導体ボディ(10)内に作成するステップと、
前記第2の導電型の第1のドリフト領域(104)を前記半導体ボディ(10)内に少なくとも有するドリフト空間を作成するステップであって、前記第1のドリフト領域(104)が前記半導体チャネル領域(102)と結合されるように、前記ドリフト空間を作成するステップと、
前記第1の導電型のバッファ領域(107)を作成するステップであって、一方の側の前記半導体ボディ(10)の前記ドリフト空間と、他方の側の前記エミッタ領域(108)との間に配置される前記バッファ領域(107)を作成するステップと、を含み、
前記第1のドリフト領域(104)の延び方向(Z)の全長(DZ4)が、前記半導体ボディ(10)の前記延び方向(Z)の全長の少なくとも5%である、
方法。 - 前記第1のドリフト領域(104)を作成するステップは、エピタキシ処理ステップ、拡散処理ステップ、及びインプラントステップのうちの少なくとも1つを含む、請求項24に記載の方法。
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US10847617B2 (en) | 2017-12-14 | 2020-11-24 | Fuji Electric Co., Ltd. | Semiconductor device |
US11342416B2 (en) | 2017-12-14 | 2022-05-24 | Fuji Electric Co., Ltd. | Semiconductor device |
US11810952B2 (en) | 2017-12-14 | 2023-11-07 | Fuji Electric Co., Ltd. | Semiconductor device |
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DE102016112721B4 (de) | 2022-02-03 |
US20180269304A1 (en) | 2018-09-20 |
US10546939B2 (en) | 2020-01-28 |
DE102016112721A1 (de) | 2018-01-18 |
US20190288088A1 (en) | 2019-09-19 |
US10332973B2 (en) | 2019-06-25 |
JP6618960B2 (ja) | 2019-12-11 |
CN107611176A (zh) | 2018-01-19 |
JP2020021941A (ja) | 2020-02-06 |
US9978851B2 (en) | 2018-05-22 |
US20180019319A1 (en) | 2018-01-18 |
CN107611176B (zh) | 2021-03-26 |
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