JP2018006464A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
【解決手段】本発明に係る半導体装置は、第1端子と、接地のための第2端子と、を備えたリードフレームと、前記リードフレームを覆う封止樹脂と、前記第2端子の一部であって、前記封止樹脂から露出した露出部と、前記封止樹脂の表面を覆い、前記露出部において前記第2端子と接触する導電性材料と、を備える。
【選択図】図1
Description
第2の目的は、封止樹脂によって封止され、電磁波に対するシールド機能を備えた半導体装置であって、小型化が可能な半導体装置の製造方法を得ることである。
図1は、本発明の実施の形態1に係る半導体装置の断面図である。図2は、本発明の実施の形態1に係る半導体装置の平面図である。本実施の形態に係る半導体装置100は、リードフレーム20を備える。リードフレーム20は、第1端子23および第2端子22を備える。第1端子23および第2端子22は、半導体装置100の端部11に配置される。第2端子22は、第1端子23よりも背が高い。第2端子は、接地のためのグランド端子である。なお、図2に示すように、本実施の形態では第1端子23と第2端子22は交互に配置されているが、第1端子23および第2端子22は別の配置および数でも良い。
図5は、本発明の実施の形態2に係る半導体装置の断面図である。本実施の形態に係る半導体装置200は、リードフレーム220を備える。リードフレーム220は、第1端子23および第2端子222を備える。第2端子222は、第3端子228および第3端子228の表面に配置された導電性部品226を備える。第3端子228は、第1端子23と同じ高さを備える。従って、第2端子222は第1端子23よりも背が高くなる。第3端子228は、接地のためのグランド端子である。
図7は、本発明の実施の形態3に係る半導体装置の断面図である。本実施の形態に係る半導体装置300は、リードフレーム320を備える。リードフレーム320は、第1端子23および第2端子322を備える。第2端子322は、実施の形態2と同様の第3端子228および第3端子228の表面に配置された導電性部品326を備える。
図8は、本発明の実施の形態4に係る半導体装置の断面図である。本実施の形態に係る半導体装置400は、リードフレーム420を備える。リードフレーム420は、第1端子23および第2端子422を備える。第2端子422は、一端がダイパッド21と一体となったピン429で形成される。ピン429は、第1端子23よりも背が高く、ダイパッド21の表面と垂直方向に伸びる。
図10は、本発明の実施の形態5に係る半導体装置の断面図である。本実施の形態に係るリードフレーム420の構成は実施の形態4と同様である。本実施の形態では、半導体装置500の端部511において、ダイパッド21を取り囲むように封止樹脂530に薄肉部550が設けられる。薄肉部550は、高さが第1端子23の高さよりも高い。このため、第1端子23は、薄肉部550においても、封止樹脂530に覆われている。導電性材料540は、封止樹脂530の表面および露出部424の表面を覆うように形成される。露出部424において、第2端子422と導電性材料540が接触する。
図11は、本発明の実施の形態6に係る半導体装置の断面図である。本実施の形態に係る半導体装置600は、リードフレーム620を備える。リードフレーム620は、第1端子23および第2端子622を備える。第2端子622は、第1端子23よりも背が高いピン629で形成される。ピン629は、一部がダイパッド21と一体となり、導通している。
Claims (17)
- 第1端子と、接地のための第2端子と、を備えたリードフレームと、
前記リードフレームを覆う封止樹脂と、
前記第2端子の一部であって、前記封止樹脂から露出した露出部と、
前記封止樹脂の表面を覆い、前記露出部において前記第2端子と接触する導電性材料と、
を備えることを特徴とする半導体装置。 - 前記第1端子および前記第2端子は、前記半導体装置の端部に配置され、
当該端部において、前記第2端子は、前記第1端子よりも高く、
前記封止樹脂は、前記端部における高さが前記第2端子と等しい薄肉部を前記端部に備えることを特徴とする請求項1に記載の半導体装置。 - 前記第2端子は、
前記リードフレームが備える前記第1端子と同じ高さの第3端子と、
前記第3端子の表面に配置された導電性部品と、を備えることを特徴とする請求項2に記載の半導体装置。 - 前記リードフレームは、半導体チップを搭載するためのダイパッドを備え、
前記第2端子は、前記ダイパッドと導通していることを特徴とする請求項2に記載の半導体装置。 - 前記露出部と前記薄肉部は、半導体チップを取り囲むように形成され、
前記導電性材料は、前記半導体チップを取り囲む前記露出部および前記薄肉部の表面を覆うことを特徴とする請求項2〜4の何れか1項に記載の半導体装置。 - 前記第2端子は、前記第1端子よりも高く、
前記第2端子と前記封止樹脂の高さが揃っており、
前記露出部は、前記封止樹脂の表面から露出していることを特徴とする請求項1に記載の半導体装置。 - 前記リードフレームは、半導体チップを搭載するためのダイパッドと、前記第1端子よりも高く一端が前記ダイパッドと一体となったピンと、を備え、
前記第2端子は、前記ピンで形成され、
前記露出部は、前記ピンの他端が前記封止樹脂の表面から露出することで形成されていることを特徴とする請求項1に記載の半導体装置。 - 前記封止樹脂は、前記半導体チップを取り囲むように、高さが前記第1端子の高さよりも高い薄肉部を備え、
前記導電性材料は、前記薄肉部の表面を覆うことを特徴とする請求項7に記載の半導体装置。 - 第1端子と、接地のための第2端子と、を備えたリードフレームを封止樹脂で覆い、前記第2端子に前記封止樹脂から露出した露出部を形成する封止工程と、
前記露出部において導電性材料が前記第2端子と接触するように、前記封止樹脂の表面に前記導電性材料を塗布する導電性材料形成工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記第1端子および前記第2端子は、前記半導体装置の端部に配置され、
前記第2端子が前記第1端子よりも背が高くなるように、前記第1端子および前記第2端子を形成する端子形成工程を備え、
前記封止工程は、前記第1端子を被覆状態に保って、前記第2端子を露出させるハーフダイシングを、前記半導体装置の端部に実施するハーフダイシング工程を備えることを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記端子形成工程は、
前記第1端子をハーフエッチングする工程を備えることを特徴とする請求項10に記載の半導体装置の製造方法。 - 前記端子形成工程は、
前記第1端子および前記リードフレームが備える第3端子をハーフエッチングする工程と、
前記第3端子の表面に導電性部品を配置し、前記第2端子を形成する工程と、
を備えることを特徴とする請求項10に記載の半導体装置の製造方法。 - 前記リードフレームは、半導体チップを搭載するためのダイパッドを備え、
前記第2端子は、前記ダイパッドと導通していることを特徴とする請求項11に記載の半導体装置の製造方法。 - 前記ハーフダイシング工程では、前記半導体装置を取り囲むようにハーフダイシングを実施し、半導体チップを取り囲むように前記露出部と、前記封止樹脂の薄肉部と、を形成し、
前記導電性材料形成工程では、前記半導体チップを取り囲む前記薄肉部の表面および前記露出部を前記導電性材料で覆うことを特徴とする請求項10〜13の何れか1項に記載の半導体装置の製造方法。 - 前記第2端子が前記第1端子よりも高くなるように、前記第1端子および前記第2端子を形成する端子形成工程を備え、
前記封止工程では、前記第2端子と前記封止樹脂の高さが揃うように前記封止樹脂を形成することを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記リードフレームは、半導体チップを搭載するためのダイパッドと、一端が前記ダイパッドと一体となったピンと、を備え、
前記ピンの他端が前記ダイパッドの表面と垂直方向を向き、前記ピンが前記第1端子よりも高くなるように、前記ピンを折り曲げて前記第2端子を形成する端子形成工程を備え、
前記封止工程では、前記ピンの他端が前記封止樹脂の表面から露出するように前記封止樹脂を形成することを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記封止工程は、前記第1端子を被覆状態に保って、前記封止樹脂に薄肉部を形成するハーフダイシングを、前記半導体装置を取り囲むように実施するハーフダイシング工程を備え、
前記導電性材料形成工程では、前記半導体チップを取り囲む前記薄肉部の表面を前記導電性材料で覆うことを特徴とする請求項16に記載の半導体装置の製造方法。
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