JP2017535960A5 - - Google Patents

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Publication number
JP2017535960A5
JP2017535960A5 JP2017525537A JP2017525537A JP2017535960A5 JP 2017535960 A5 JP2017535960 A5 JP 2017535960A5 JP 2017525537 A JP2017525537 A JP 2017525537A JP 2017525537 A JP2017525537 A JP 2017525537A JP 2017535960 A5 JP2017535960 A5 JP 2017535960A5
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JP
Japan
Prior art keywords
terminal
chip
semiconductor
central area
wafer
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JP2017525537A
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English (en)
Japanese (ja)
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JP6709785B2 (ja
JP2017535960A (ja
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Priority claimed from US14/537,943 external-priority patent/US9305852B1/en
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Publication of JP2017535960A publication Critical patent/JP2017535960A/ja
Publication of JP2017535960A5 publication Critical patent/JP2017535960A5/ja
Application granted granted Critical
Publication of JP6709785B2 publication Critical patent/JP6709785B2/ja
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JP2017525537A 2014-11-11 2015-11-11 半導体チップを有する電子システムのためのパッケージ Active JP6709785B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/537,943 2014-11-11
US14/537,943 US9305852B1 (en) 2014-11-11 2014-11-11 Silicon package for embedded electronic system having stacked semiconductor chips
PCT/US2015/060208 WO2016077488A1 (en) 2014-11-11 2015-11-11 Package for electronic system having semiconductor chips

Publications (3)

Publication Number Publication Date
JP2017535960A JP2017535960A (ja) 2017-11-30
JP2017535960A5 true JP2017535960A5 (enExample) 2018-12-20
JP6709785B2 JP6709785B2 (ja) 2020-06-17

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ID=55589080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017525537A Active JP6709785B2 (ja) 2014-11-11 2015-11-11 半導体チップを有する電子システムのためのパッケージ

Country Status (5)

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US (2) US9305852B1 (enExample)
EP (1) EP3218930B1 (enExample)
JP (1) JP6709785B2 (enExample)
CN (1) CN107078124B (enExample)
WO (1) WO2016077488A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9893058B2 (en) * 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure
EP3279935B1 (en) * 2016-08-02 2019-01-02 ABB Schweiz AG Power semiconductor module
US20200235067A1 (en) * 2019-01-22 2020-07-23 Texas Instruments Incorporated Electronic device flip chip package with exposed clip
US11031321B2 (en) * 2019-03-15 2021-06-08 Infineon Technologies Ag Semiconductor device having a die pad with a dam-like configuration
US11024564B2 (en) 2019-06-19 2021-06-01 Texas Instruments Incorporated Packaged electronic device with film isolated power stack
EP3944304A1 (en) * 2020-07-20 2022-01-26 Nexperia B.V. A semiconductor device and a method of manufacture
CN114899171B (zh) * 2022-04-29 2025-10-03 佛山市国星光电股份有限公司 一种无焊线功率器件
CN115188853A (zh) * 2022-08-15 2022-10-14 西安西热产品认证检测有限公司 一种低温双面光伏组件

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568958A (en) * 1984-01-03 1986-02-04 General Electric Company Inversion-mode insulated-gate gallium arsenide field-effect transistors
JP4052078B2 (ja) * 2002-10-04 2008-02-27 富士通株式会社 半導体装置
EP1501126A1 (en) * 2003-11-05 2005-01-26 Infineon Technologies AG Semiconductor chip having a cavity for stacked die application
US7279786B2 (en) * 2005-02-04 2007-10-09 Stats Chippac Ltd. Nested integrated circuit package on package system
US9147649B2 (en) * 2008-01-24 2015-09-29 Infineon Technologies Ag Multi-chip module
US8358014B2 (en) * 2009-05-28 2013-01-22 Texas Instruments Incorporated Structure and method for power field effect transistor
WO2012021310A1 (en) * 2010-08-09 2012-02-16 Rambus Inc. Disaggregated semiconductor chip assembly and packaging technique
US8666505B2 (en) * 2010-10-26 2014-03-04 Medtronic, Inc. Wafer-scale package including power source
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US8994048B2 (en) * 2010-12-09 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration
CN102169872B (zh) * 2011-01-26 2013-07-03 上海腾怡半导体有限公司 集成电感的电源模块
GB2492551A (en) * 2011-07-04 2013-01-09 Accuric Ltd Current regulator
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
JP2014209091A (ja) * 2013-03-25 2014-11-06 ローム株式会社 半導体装置
TWI518844B (zh) * 2013-12-11 2016-01-21 矽品精密工業股份有限公司 封裝結構及其製法
CN105575913B (zh) * 2016-02-23 2019-02-01 华天科技(昆山)电子有限公司 埋入硅基板扇出型3d封装结构

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