CN107078124B - 用于具有半导体芯片的电子系统的封装 - Google Patents
用于具有半导体芯片的电子系统的封装 Download PDFInfo
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Abstract
在所述示例中,电子系统包括单晶半导体的第一芯片(101),其包括嵌入在单晶半导体的第二芯片(102)中的第一电子器件,该第二芯片(102)成形为具有通过脊部(103)确定边界的板坯(104)的容器,并包括第二电子器件。嵌套芯片被组装在低级硅的容器中,该容器成形为通过保持壁(131)确定边界的板坯(130)并包括导电迹线和端子。第一电子器件通过将第一芯片附接至第二芯片的板坯而连接至第二电子器件。第一电子器件和第二电子器件通过将第二芯片嵌入在容器中而连接至该容器。嵌套的第一芯片和第二芯片作为电子系统起作用,并且该容器作为该系统的封装起作用。对于作为场效应晶体管的第一器件和第二器件,该系统为功率块。
Description
本发明大体涉及半导体器件和工艺,并且更具体地涉及用于嵌入式半导体功率块和半桥器件的低级硅封装的结构和晶片级制造方法。
背景技术
在当今大部分半导体器件中,半导体芯片通常在基板(诸如,金属引线框或多层层合体)上组装,并且在坚固材料(诸如,陶瓷或硬化塑料化合物)的封装中包封。组装工艺通常包括将芯片附接至基板焊盘或引线框焊盘的工艺,以及使用键合线或焊料球将芯片端子连接至基板引线的工艺。
使用各种不同的材料(诸如,金属、陶瓷和塑料)带来部件相互粘合和长期器件稳定性的挑战。示例是相邻部件的分层。对于塑料封装的半导体器件,人们已针对识别由基于材料的热膨胀系数的失配引起的热机械应力导致的器件可靠性问题的校正措施进行了广泛的研究。由于应力效应引起的劣化可以减轻,但不会消除。而且,塑料包封器件的电特性的潮湿相关劣化已被确切记载,但仅被控制在一定程度。为防止在工作温度漂移后,器件中的金属连接开始疲劳和开裂,人们一直在进行各种尝试,但仅取得有限的成功。
受欢迎的功率电路系列包括用于将DC电压转换为另一DC电压的电力切换器件。对于紧急电力输送要求,合适的选项包括具有串联连接并通过共同的开关节点耦合在一起的两个功率MOS场效应晶体管(FET)的功率块;此组件也被称为半桥。当添加调节驱动器和控制器时,该组件被称为功率级或更常见地称为同步降压转换器。在同步降压转换器中,控制FET芯片(也称为高侧开关)被连接在电源电压VIN与LC输出滤波器之间,以及同步(sync)FET芯片(也称为低侧开关)被连接在LC输出滤波器与接地电位之间。控制FET芯片与同步FET芯片的栅极被连接至包括用于转换器和控制器的驱动器的电路系统的半导体芯片;该芯片也被连接至接地电位。
对于当今的许多功率开关器件来说,功率MOSFET芯片以及驱动器和控制器IC的芯片以水平并排的方式组装为单个部件。通常每个芯片被附接至金属引线框的矩形或方形焊盘,并且焊盘被引线包围作为输出端子。在其他功率开关器件中,功率MOSFET芯片以及驱动器-控制器IC被水平并排组装在单个引线框焊盘上,该引线框焊盘继而被引线四面包围充当器件输出端子。该引线往往以无悬臂延伸的形式成形,并且以四方扁平无引线(QFN)或小外形无引线(SON)器件的方式排列。从芯片至引线的电连接可由键合线提供,该键合线的长度和阻抗将明显的寄生电感引入功率电路中。在一些最近引进的先进组装中,夹具代替许多连接线。这些夹具是宽的并引入最小的寄生电感,但是比键合线更昂贵并且需要更复杂的组装工艺。每个组件通常被封装在塑料包封中,并且封装后的部件被用作电源系统的板组件的分立构建块。
在其他最近引入的方案中,控制FET芯片和同步FET芯片被垂直组装为一个在另一个上面的叠堆,其中(两个芯片之中的)物理面积更大的芯片被附接至引线框焊盘,并且其中芯片提供至开关节点和叠堆顶部的连接。与物理尺寸无关,由于占空比和传导损失的考虑,同步FET芯片需要比控制FET芯片的有效面积更大的有效面积。当同步芯片和控制芯片两者被组装为源极向下时,更大的(物理面积和有效面积两者)同步芯片被组装在引线框焊盘上,以及更小的(物理面积和有效面积两者)控制芯片使其源极连结至同步芯片的漏极,从而形成开关节点,并且至输入电源VIN的漏极;夹具被连接至两个芯片之间的开关节点。焊盘处于接地电位并用作可操作地生成的热量的扩散器;叠堆顶部的细长夹具被连结至输入电源VIN。
发明内容
在所述示例中,电子系统包括单晶半导体的第一芯片,其包括嵌入在单晶半导体的第二芯片中的第一电子器件,该第二芯片成形为具有通过脊部确定边界的板坯的容器,并包括第二电子器件。嵌套芯片被组装在低级硅的容器中,该容器成形为通过保持壁确定边界的板坯并包括导电迹线和端子。第一电子器件通过将第一芯片附接至第二芯片的板坯上而连接至第二电子器件。第一电子器件和第二电子器件通过将第二芯片嵌入在容器中而连接至该容器。嵌套的第一芯片和第二芯片作为电子系统起作用,并且该容器作为该系统的封装起作用。对于作为场效应晶体管的第一器件和第二器件,该系统为功率块。
附图说明
图1示出包括具有倒装附接至硅封装并嵌入在该硅封装中的堆叠硅MOS场效应晶体管(FET)的功率块的实施例的透视图。
图2示出沿线A-A的图1的组装系统的横截面。
图3描绘具有所附接和嵌入的功率块的堆叠MOSFET芯片的低级硅(L-g-Si)晶片的一部分的横截面。
图4示出蚀刻和金属化适合组装用于功率块的堆叠芯片的凹部后的l-g-Si晶片的部位的透视图。
图5A示出用于组装功率块的MOSFET芯片的金属端子的透视图。
图5B描绘在蚀刻凹部和沉积并图案化与图5A的芯片FET端子匹配的金属层之后的l-g-Si晶片的部位的透视图。
图6示出在将具有端子的FET制造到芯片中之前具有蚀刻到一个芯片侧中的凹部的单晶硅芯片的透视图。
图7示出具有倒装附接至起封装作用的l-g-Si板坯(slab)并嵌入在该板坯中的堆叠硅MOS FET的组装功率块的透视图。
图8描绘具有堆叠的MOS FET与相邻的驱动器-控制器芯片的组装功率转换器的透视图,该堆叠的MOS FET与相邻的驱动器-控制器芯片被嵌入在蚀刻到起封装作用的l-g-Si板坯中的凹部中。
图9为用于制造具有嵌入在硅封装中的堆叠部件芯片的电子系统的方法的流程图。
具体实施方式
示例实施例关于以下方面显著改善半导体晶体管器件、功率块和功率转换器:减小寄生电阻和电感、改善热性能和速度、增强在潮湿和温度变化环境中的工作可靠性并降低制造成本。在半导体芯片被组装在金属载体上并封装在塑料包封中的传统复合材料封装组合具有各种不同热膨胀系数的材料,从而导致热机械应力的倾向,并且需要漫长、耗时和昂贵的制造流程。
市场趋势(特别是针对汽车和手持应用)需要小型化的半导体产品。例如,该趋势有利于DC-DC转换器的结构,其半导体芯片彼此被堆叠在顶部上以节省宝贵的占用面积(real estate),而不是并排组装。
半导体封装的材料和成本问题通过封装的结构概念和制造流程解决,它采用常规半导体晶片制造的批量生产和受控工艺并使其并行化。新的封装基于使用从晶片切割的硅板坯,该晶片由低级硅并因此由低成本硅构成,诸如从回收、未精制和未掺杂的硅获得的低级硅。当以晶片形式处理时,板坯获得适合组装单晶器件芯片的凹部,并且它可以充当载体以及最终封装。
新的封装概念消除了引线框、键合线、金属夹具、焊料球和塑料、陶瓷以及金属壳体。相反,制造工艺使用成熟的前端技术,诸如蚀刻半导体、金属和绝缘体,沉积金属层、绝缘体层和钝化层,生长绝缘层以及通过光刻技术图案化。
而且,对于在没有夹具的情况下堆叠芯片,组装问题通过具有完成的晶体管或电路的芯片的概念和制造流程解决,该概念和制造流程包括将凹部蚀刻到完成芯片中,该完成芯片具有用于将较小的芯片嵌入到该凹部中的轮廓和深度。
所得的器件不经受不匹配的热膨胀系数,而是允许最小化的热机械应力。此外,寄生电阻和电感减小,因为线键合和夹具被去除。新器件的导热率(并因此电气性能)通过将成品器件的芯片直接附接至电路板上而增强。而且,所得的功率块和功率转换器(具有堆叠和嵌入式芯片)允许在x维、y维和z维上的同时器件小型化。
图1示出系统100作为示例实施例,其包括功率块110,该功率块110嵌入到包括板坯130和脊部或保持壁131的低级硅(l-g-Si)的容器中并附接至该容器。容器展现出系统的某些端子并还作为系统封装起作用。图2示出沿线A-A的通过功率块101的横截面。该横截面示出晶体管芯片的附接以及金属和绝缘体的层顺序。图3描绘在完成组装后但在将低级硅的晶片切割成分立封装系统之前的通过多个封装系统的横截面。
参考图1的示例,板坯130具有平坦表面135并由低级硅(l-g-Si)制成,该低级硅选自包括(但不限于)回收硅、粗硅、未掺杂硅、多晶硅、本征多晶硅、低掺杂n型多晶硅和低掺杂p型多晶硅的组。在其他实施例中,该l-g-Si材料可重掺杂以获得低电阻率。在图1的示例中,板坯130的厚度130a为~300μm,长度130b为~5.8mm,以及宽度130c为~3.7mm。厚度130a在本文中称为第一厚度。l-g-Si板坯的材料被暴露在该板坯的边缘131a。图1所示的板坯顶部适当地由第一绝缘层133构成,该第一绝缘层133确定第一平面191。绝缘层的部分被暴露在特定的位置,而其他部分被金属层覆盖,该金属层被配置为系统100的端子120(例如,功率块的开关节点)、端子121(例如,高侧FET的栅极)和端子122(例如,被连结至输入电源VIN的高侧FET的漏极)。板坯的绝缘表面在本文中被称为第一表面130d,其在第一平面191中。
如图1所示,板坯130被配置为在平面191中具有顶表面130d的一组升高脊部131,使得该脊部构造成凹部的框架。在图1中,系统具有两个平行的脊部。在其他实施例中,该系统可具有更多的脊部。凹部包括在第二平面191中具有表面134的凹陷中心区域。表面134被第二绝缘层136覆盖。中心区域适合容纳至少半导体芯片102。另一实施例如图8所示,其中,中心区域适合容纳多于一个芯片。图1示出在第二平面192中的中心区域的表面,该第二平面192与第一平面191隔开凹陷深度132a,该凹陷深度在本文中被称为第一深度。优选地,第一深度132a等于芯片厚度102a和用于将芯片102附接至凹陷中心区域的粘合材料的厚度之和。在图1的示例中,第一深度132a可为~64μm。如后面的附图所描绘,该中心区域被图案化金属层覆盖,该图案化金属层被配置为器件端子诸如晶体管端子的附接焊盘。如图2和图3所示,中心区域的焊盘分为内部组和外围组。
图1中可见的功率块110的部分为半导体芯片102,其在本文中被称为第二芯片(第一芯片101如图2和图3所示)。在图1的示例中,芯片102由重掺杂的单晶硅制成,其允许直接接触往往称为背面金属的金属层。掺杂硅由本征硅的外延层顶出,该本征硅的外延层包括用作功率块的低侧晶体管的漏极向下MOS场效应晶体管(FET),并且在本文中被称为第二半导体芯片。芯片102具有厚度102a,诸如~50μm,其在本文中被称为第三厚度。第三厚度102a小于第一厚度130a,但大于第二厚度101a(其在图2和图3中被描绘为第一半导体芯片101的厚度)。芯片102具有平坦侧102d(图1),其在本文中被称为第三侧。
图1的示例MOS FET在远离板坯130的第三侧上具有其源极端子140和栅极端子141。源极端子140被电连结至接地电位。在其他示例中,半导体芯片可由硅锗、砷化镓、氮化镓或用作半导体器件材料的其他III-V和II-VI族化合物制成。在其他FET实施例中,漏极端子可背离板坯。在其他实施例中,晶体管可为双极型晶体管,该晶体管具有背离板坯的集电极触点;或者该双极型晶体管可具有背离该板坯的发射极端子。
因为图2示出沿图1中线A-A截取的系统100的横截面,因此并不表示板坯130的脊部。相反,图2示出板坯的平坦表面135和凹陷中心区域的平坦表面134,平坦表面134处于第二平面192中。图2另外显示第一半导体芯片101和第二半导体芯片102,第二芯片102可大于第一芯片101。这两个芯片由单晶半导体材料(诸如硅)制成。对于第二芯片102,图2指示平坦侧102d,其在本文中被称为第三侧。图2另外示出芯片102具有被轮廓化的第四侧102b。第四侧102b的轮廓被配置为在第三平面193中具有表面的一组脊部103;脊部103构造成凹部的框架。在图2中,芯片102具有两个平行的脊部。在其他实施例中,芯片102可具有更多的脊部。凹部包括在平行于平面193的第四平面194中具有表面102c的凹陷平坦中心区域。该中心区域适合于容纳第一芯片101,其从而被嵌入在第二芯片102中。图1示出第四平面194与第三平面193隔开小于第一深度132a的第二深度132b,且第四平面194适合容纳第一芯片101的厚度,该第一芯片101具有其金属层和附接材料层。
图2指示包括芯片102的表面102c的第四侧102b被金属层221均匀覆盖,该金属层221有时也被称为背面金属。优选地,层221包括用于粘合至半导体晶体的难熔金属层(诸如钛或钨),接着是镍层和贵金属的最外层(诸如银、钯或金)。在一些产品中,难熔金属层被省略。芯片102的第三侧102d部分也具有类似金属选择,诸如钛、镍和银或仅是镍和金的堆叠层序列。堆叠的金属层被图案化为焊盘222和223。
在图2的示例实施例中,芯片102包括用作功率块的低侧FET的场效应晶体管(FET)。如上所述,芯片102的块状(bulk)单晶硅被重掺杂并与所谓的背面金属层221有很好的接触。在图2的这个示例中,具有金属层221的金属化第四芯片侧102b用作被电连结至开关节点的低侧FET的漏极端子,焊盘222为电连结至接地电位的源极端子,以及焊盘223为低侧FET的栅极端子。如图2所示,芯片102的第四芯片侧102b包括脊部和中心区域,该中心区域相对于脊部被凹陷。
基于其较小的尺寸和厚度,第一芯片101被嵌入在第二芯片102的凹部中。如上所述,第一芯片101由单晶半导体材料诸如硅制成。与第二芯片102相反,第一芯片101的第一侧101d和第二侧101b两者是平坦的。第一芯片101具有厚度101a,其小于第二深度132b,使得第一芯片101(连同其金属层和附接层)可以嵌入在第二芯片102的凹陷中心区域中。
在图2的示例实施例中,芯片101包括场效应晶体管(FET),其用作功率块的高侧FET,并且在第一芯片侧和第二芯片侧上具有端子。在该示例中,第一芯片侧101d的金属焊盘211用作被电连结至输入电源VIN的高侧FET的漏极端子,以及焊盘213为高侧FET的栅极端子。
如图2所示,板坯130的l-g-Si材料被绝缘层136(优选地为热生长二氧化硅)覆盖。在一些地方,绝缘层具有增加的厚度,其是下面工艺流程所论述的金属层图案化的次生效应。继而,绝缘层136被金属层覆盖。一个金属层可能是足够的,但图2示出了金属层序列的优选方法。第一层231由难熔金属诸如钛制成,接着是复合层诸如氮化钛。可替换选择包括钨、钛钨或另一种难熔金属的层。难熔金属牢固地粘附至绝缘层136。然后,将铝层232沉积到难熔金属层上;层232优选地厚于层231。对于一些应用,优选在顶部或铝层232上沉积镍层和薄金层(两层在图2中标明为233),以方便附接晶体管端子。
在板坯130的凹陷中心区域中图案化金属层231和232(以及可选的233)。图案化的结果是将多个焊盘分成内部组和外围组。内部组的焊盘与第一芯片101的晶体管端子匹配,以及外围组的焊盘与第二芯片102的脊部的端子匹配。对于图2的第一芯片101,内部组的图案化金属焊盘包括高侧FET的漏极端子241和栅极端子243。对于图2的第二芯片102,外围组的图案化金属焊盘包括功率块的开关节点端子242,其组合了高侧FET的源极端子和低侧FET的漏极端子。
图3描绘在每个板坯部位中完成组装第一FET芯片和第二FET芯片之后具有多个板坯部位的l-g-Si晶片330的一部分。如图3所示,对于每个板坯部位,该组件包括嵌入在第二芯片102的凹部中的第一芯片101,并继而包括嵌入在相应板坯的凹部中的第二芯片。第二芯片102作为容器形成,该容器包括由脊部103确定边界的板坯104。嵌入的位置意味着第二芯片102的第四侧的金属化凹陷中心区域被附接至第一芯片的第二侧上的端子,并且第二芯片的金属化脊部被附接至中心l-g-Si区域的外围组的焊盘,因此在第二芯片的第三侧上的晶体管端子与在相应l-g-Si板坯的脊部上的金属层共面。在图3中,共面平面被标明为191;它在本文中被称为第一平面。
在图3中,用于分离板坯部位的通过晶片的切割线被标记为340。在形成单独的(singulate)之后,分立系统看起来像图1中所描绘的系统100。当系统100连接至电路板时,金属层222(作为源极端子140)和金属层223(作为栅极端子141)准备附接至外部部件。
另一实施例为制造适合作为器件封装的由保持壁确定边界的半导体板坯的方法,以及制造使用硅板坯作为半导体器件封装的封装电子系统的方法。某些工艺总结在图4、图5A、图5B、图6和图7中。在图9的流程图中,介绍了用于制造具有嵌入在硅封装中的堆叠芯片的电子系统的工艺流程。制造半导体板坯的工艺流程通过提供低级硅(l-g-Si)的晶片开始,其包括多个板坯部位(工艺901)。该晶片具有两个平行的平坦表面,其中一个表面被称为第一表面。优选的晶片直径为300mm,但可使用较小的直径;第一表面的平面被称为第一平面191。优选地,最终晶片(切片之前)具有~300μm的厚度130a(称为第一厚度)。然而,前面的工艺步骤可使用较厚的晶片并通过背面研磨获得最终厚度而执行。因此,图3的标示110旨在指示大于130a的此晶片厚度。l-g-Si可选自包括回收硅、粗硅、未掺杂硅、多晶硅和本征多晶硅的组。对于具有与板坯隔离的晶体管端子的器件,l-g-Si材料也可包括低掺杂的n型多晶硅和低掺杂的p型多晶硅。相比之下,对于具有短接至板坯的晶体管端子的器件,该l-g-Si材料也可包括低电阻率的n型多晶硅和低电阻率的p型多晶硅。
在接下来的l-g-Si选择工艺中,第一绝缘层133在晶片的第一表面上形成(工艺902);该层覆盖所有板坯部位。形成绝缘表面层的优选技术是对硅进行热氧化。可替换技术包括沉积二氧化硅、氮化硅、碳化硅层或它们的组合,以及沉积与硅化合物不同的绝缘化合物。
然后,第一绝缘层从每个板坯部位的中心部分去除以暴露在下面的l-g-Si,而保留在外围部位部分上的未被去除的第一绝缘层133以形成构成每个中心部分的框架的脊部(工艺903)。脊部有时被称为确定该中心部分边界的保持壁或边沿。
在接下来的工艺(工艺904)中,对每个板坯部位的中心区域的暴露l-g-Si蚀刻,诸如使用KOH,以形成具有第二l-g-Si表面的凹部,该第二l-g-Si表面在从第一平面凹陷深度132a的第二平面192中具有平坦中心部分。图4描绘在加工状态下的单独板坯部位,其总结了上述参考制造工艺的结果;所描绘的部位为更大晶片的整体部分,如虚线所指示。
对于图4中的分立板坯部位,凹部具有通过两个平行脊部确定边界的矩形配置。对于其他器件,可使用凹部和脊部的其他配置。通过蚀刻工艺形成的凹部也形成了在第一平面191和第二平面192之间的l-g-Si的台阶(step)。优选地,该台阶倾斜小于90°。更优选地,该台阶在第一l-g-Si表面和第二l-g-Si表面之间形成缓坡401,使得可以容易在斜坡401上沉积不间断的金属层。
在产生图2的封装晶体管器件的工艺流程中,流程通过提供未掺杂或弱掺杂l-g-Si的晶片开始,其包括多个板坯部位210。每个部位被配置成具有在第一平面290中的顶部的脊部和由脊部为其构造框架的凹部。该凹部包括在与第一平面隔开深度112的第二平面291中的凹陷中心区域。第二绝缘层136在第二硅表面上形成;层136覆盖所有板坯部位(工艺905)。其他技术是可能的,但优选第二绝缘层是热生长的,使得第二层136的二氧化硅与第一层133的残留二氧化硅合并。
接下来,将至少一个金属层231沉积到第二绝缘层136上,从而覆盖所有板坯部位(工艺906)。优选地,首先选择难熔金属诸如钛的层,接着是化合物层诸如氮化钛。可替换选择包括钨、钛钨或另一种难熔金属的层。难熔金属牢固地粘附至绝缘层136。然后,将铝层232沉积到难熔金属层上。层232优选地厚于层231。对于一些应用,优选在顶部或铝层232上沉积镍层和薄金层(两层在图2中标明为233),以方便附接晶体管端子。
接下来,金属层231和232(以及233)在每个板坯部位被图案化(工艺907)。图4给出了分立板坯的图案化金属焊盘的总览。在脊部上,形成系统端子。在中心部位部分中,形成晶体管端子(或其他器件端子)的焊盘,它们被分组为内部组和外围组。
在如图4所示的示例的脊部上,金属层120被指定为功率块的开关节点的系统端子;金属层121将为高侧FET的栅极的端子;以及层122将为被连结至系统的输入电源VIN的高侧FET的漏极的系统端子。在图4的示例的中心部位部分中,图案化的结果是将多个焊盘分为匹配晶体管的端子的内部组和外围组。内部组的焊盘包括高侧FET的漏极端子211(终结为脊部上的端子122)的焊盘411和高侧FET的栅极端子213(终结为脊部上的端子121)的焊盘413。外围组的焊盘包括开关节点端子(终结为脊部上的端子120)的焊盘420。
在图案化之后,将钝化材料诸如氮化硅的层205沉积到图案化金属层上,从而覆盖所有板坯部位(工艺908)。然后在每个板坯部位从脊部上的端子和从中心部分中的焊盘去除钝化层237,从而暴露在下面的金属。相比之下,在斜坡上和焊盘之间的钝化材料保持未被去除。
在接下来的工艺909中,第一半导体芯片101具有平坦第一侧101b和相对的平坦第二侧101d,以及小于l-g-Si板坯的第一厚度130a的第二厚度101a。第一芯片可包括具有在第一芯片侧和第二芯片侧上的端子的晶体管。对于图5A的示例,芯片的形状为六面体并由单晶硅制成。该芯片可包括在第一芯片侧上具有源极端子以及在相对的第二芯片侧上的漏极端子211和栅极端子213的FET。对于其他系统,芯片101可包括双极型晶体管,或其可具有不同的端子分布,或者芯片101可由砷化镓、氮化镓或任何其他半导体单晶化合物制成。
接下来,第一芯片101的第一侧的端子被附接至l-g-Si晶片的每个板坯130的中心区域的内部组的相应焊盘(工艺910)。优选的附接材料为导电胶,其包括粘合剂高分子化合物。图5B描绘在附接之后的示例板坯部位,其形成在图5B中被标明为500的子组件。在该子组件中,第一芯片的第二侧的端子212面向第一平面191。在图5B的例子中,端子212表示第一芯片的FET的源极端子。
在接下来的工艺911中,如图6所示,第二半导体芯片102具有平坦第三侧102d和相对的轮廓化第四侧102b,以及小于第一厚度但大于第二厚度101a的第三厚度102a。第四侧102b被配置为脊部或保持壁,其在第三平面193中构造为包括在平行第四平面194中的平坦中心区域的凹部的框架,平行第四平面194从第三平面凹陷第二深度132b。第二深度132b被配置为小于板坯的第一深度132a,并适合容纳第一芯片101。
第二芯片102由单晶半导体制成,该单晶半导体往往是重掺杂的硅,并且与覆盖第四侧102b的均匀金属层接触良好。而且,芯片102包括适合形成有源器件,诸如FET或双极型晶体管的外延层。在图6的示例中,晶体管为具有在第三侧102d上的源极端子222和栅极端子223以及在第四侧102b上的漏极端子的FET。
图7示出具有图5B的子组件500的第二芯片102的组装(工艺912)。在此工艺中,第二芯片102的第四侧102b的金属化凹陷中心区域被附接至相应第一芯片101的第二侧101b上的端子,以及第二芯片102的金属化脊部被附接至中心l-g-Si区域的相应外围组的焊盘。在此组装工艺中,在第二芯片的第三侧102d上的晶体管端子222和223变成与相应l-g-Si板坯130的脊部上的端子120、121和122共面。所有附接工艺优选地使用粘合剂聚合物化合物的导电胶执行;可替换地,它们可使用无铅焊料执行。所有系统端子的共面性便于将系统组装到外板上。
在芯片已被组装在晶片的部位的凹部中之后,l-g-Si晶片被锯切或激光切割为形成单独的系统,如图1所示(工艺913)。
具有嵌入在硅封装中的堆叠半导体芯片的电子系统提供了众多的技术优势。与传统系统相比,多个部件被去除,所有这些部件是昂贵的、在制造中劳动密集型的,以及在电气参数中为寄生的,诸如:键合线、连接夹具、金属引线框、塑料成型化合物和具有铅的焊料。通过至壳体、至顶部、至环境和散热器的低θ参数,大大改善了热性能。活性硅对封装的比率为高,并且整个系统的厚度可以保持非常薄(~0.3mm至~0.5mm)。芯片和封装的热膨胀系数之间的差异被最小化或消除;从而最小化热机械应力。
其他实施例为电子系统,诸如DC-DC功率转换器,其往往被称为同步降压转换器。图8中描绘的示例转换器包括两个FET芯片的垂直叠堆(其彼此嵌入),以及被组装在形成为具有保持壁的板坯的l-g-Si容器上的相邻驱动器和控制器芯片。该示例系统具有5.0mm的长度801,3.0mm的宽度802,和0.45mm的高度803。驱动器和控制器芯片810的所有金属端子和硅背面810a是共面的;共用平面被标明为191。通过采用和扩展在图1和图7中的标示,图8示出具有嵌入式FET和附接至板坯130的倒装驱动器和控制器芯片810的功率块110。在图8的示例中,金属层222为低侧FET(同步FET)的源极端子,层223为低侧FET(同步FET)的栅极端子,金属层122为电连结至输入电源VIN的高侧FET的漏极端子,层121为高侧FET的栅极端子,层120为开关节点的端子,以及金属层811、812、813、814、815和816为倒装芯片810的集成驱动器和控制器电路的输出引脚。暴露的硅表面810a可被金属化以方便附接至外部板。
在权利要求的范围内,所述实施例的修改是可能的,并且其他实施例也是可能的。例如,示例实施例适用于场效应晶体管,并且也适用于其他合适的功率晶体管、双极型晶体管、绝缘栅晶体管、晶闸管等。
作为另一示例,功率转换器的结构和制造方法的上述考虑适用于调节器、多输出功率转换器、具有感测端子的应用以及具有开尔文端子的应用等。
作为另一示例,通过在器件附接至板之后使用l-g-Si的空白背面,使该背面可以优选地连接到散热器,封装晶体管和转换器的高电流能力可以进一步扩展,并且效率进一步增强。在此配置中,该器件可以将其热量散发到板和散热器中。
Claims (23)
1.一种电子系统,其包括:
单晶半导体的第一芯片,所述第一芯片成形为六面体并包括第一电子器件;
单晶半导体的第二芯片,所述第二芯片成形为具有由保持壁确定边界的板坯的容器,并且包括第二电子器件;
低级硅的容器,所述容器成形为由保持壁确定边界的板坯并包括导电迹线和端子,所述板坯被配置为在第一平面中的脊部,所述脊部构造为包括在第二平面中的凹陷中心区域的凹部的框架,所述第二平面与所述第一平面间隔第一深度,所述脊部和所述中心区域由被图案化为用于接触晶体管端子的焊盘的金属层覆盖;
所述第一芯片附接至第二芯片的所述板坯,从而形成嵌套芯片;以及
所述第一芯片和第二芯片被嵌入在所述容器中,其中,所嵌套的第一芯片和第二芯片可操作为电子系统,并且所述容器可操作为所述系统的封装。
2.根据权利要求1所述的系统,其中,所述单晶半导体为硅,所述第一电子器件和第二电子器件为MOS场效应晶体管,以及所述电子系统为功率块。
3.根据权利要求1所述的系统,其中,所述单晶半导体为硅,所述第一电子器件和第二电子器件为双极型晶体管,以及所述电子系统为调节器。
4.一种电子系统,其包括:
单晶半导体的第一芯片,所述第一芯片成形为六面体并包括第一电子器件;
单晶半导体的第二芯片,所述第二芯片成形为具有通过保持壁确定边界的板坯的容器,并且包括第二电子器件;
单晶半导体的第三芯片,所述第三芯片成形为六面体并包括第三电子器件;
低级硅的容器,所述容器成形为由保持壁确定边界的板坯并包括导电迹线和端子,所述板坯被配置为在第一平面中的脊部,所述脊部构造为包括在第二平面中的凹陷中心区域的凹部的框架,所述第二平面与所述第一平面间隔第一深度,所述脊部和所述中心区域由被图案化为用于接触晶体管端子的焊盘的金属层覆盖;
所述第一芯片附接至所述第二芯片的所述板坯,从而形成嵌套芯片的叠堆;以及
所嵌套的第一芯片和第二芯片与相邻的第三芯片被嵌入在所述容器中,其中,所嵌套的第一芯片和第二芯片与所述相邻的第三芯片可操作为电子系统,并且所述容器可操作为所述系统的封装。
5.根据权利要求4所述的系统,其中,所述单晶半导体为硅,所述第一电子器件和第二电子器件为MOS场效应晶体管,所述第三电子器件为集成电路,并且所述电子系统为功率转换器。
6.一种封装的电子系统,其包括:
具有第一厚度和在第一平面中的表面的低级硅板坯即l-g-Si板坯,所述l-g-Si板坯被构造为在所述第一平面中的脊部,所述脊部构造为包括在第二平面中的凹陷中心区域的凹部的框架,所述第二平面与所述第一平面间隔第一深度,所述脊部和所述中心区域由被图案化为用于接触晶体管端子的焊盘的金属层覆盖,所述中心区域的所述焊盘被分为内部组和外围组;
第一半导体芯片,其具有平坦的第一侧和相对的平坦的第二侧,以及小于所述第一厚度的第二厚度,所述第一半导体芯片包括在所述第一侧和第二侧上具有端子的晶体管,所述第一侧的所述端子附接至所述l-g-Si板坯的所述中心区域的所述内部组的相应焊盘,从而形成子组件,其中,所述第二侧的所述端子面向所述第一平面;
第二半导体芯片,其具有平坦的第三侧和相对的轮廓化的第四侧,以及小于所述第一厚度但大于所述第二厚度的第三厚度,所述第四侧被配置为在第三平面中的脊部,所述脊部构造为包括在平行第四平面中的平坦中心区域的凹部的框架,所述平行第四平面从所述第三平面凹陷小于所述第一深度的第二深度并适合容纳所述第一半导体芯片,所述第四侧被均匀金属化,所述第二半导体芯片包括在所述第三侧和所述第四侧上具有端子的晶体管;以及
所述第四侧的所述金属化凹陷中心区域附接至所述第一半导体芯片的所述第二侧上的所述端子,并且所述第二半导体芯片的所述金属化脊部附接至所述中心l-g-Si区域的所述外围组的所述焊盘,因此在所述第二半导体芯片的所述第三侧上的所述晶体管端子与在相应l-g-Si板坯的所述脊部上的所述金属层共面。
7.根据权利要求6所述的封装的电子系统,其中,所述第一半导体芯片和所述第二半导体芯片的晶体管为MOS场效应晶体管,以及所述电子系统为功率块。
8.根据权利要求6所述的封装的电子系统,其中,所述第一半导体芯片和所述第二半导体芯片的晶体管为双极型晶体管,以及所述电子系统为调节器。
9.一种用于制造封装的电子系统的方法,其包括:
提供包括多个板坯部位的低级硅即l-g-Si的晶片,所述晶片具有第一厚度和在第一平面中的第一表面,每个部位被配置为在所述第一平面中的脊部,所述脊部构造为包括在第二平面中的凹陷中心区域的凹部的框架,所述第二平面与所述第一平面间隔第一深度,所述脊部和所述中心区域由被图案化为用于接触晶体管端子的焊盘的金属层覆盖,所述中心区域的所述焊盘被分为内部组和外围组;
提供多个第一半导体芯片,其具有平坦的第一侧和相对的平坦的第二侧,以及小于所述第一厚度的第二厚度,所述第一半导体芯片包括在所述第一侧和第二侧上具有端子的晶体管;
将所述第一侧的所述端子附接至每个l-g-Si板坯的所述中心区域的所述内部组的相应焊盘,从而形成子组件,其中,所述第二侧的所述端子面向所述第一平面;
提供多个第二半导体芯片,其具有平坦的第三侧和相对的轮廓化的第四侧,以及小于所述第一厚度但大于所述第二厚度的第三厚度,所述第四侧被配置为在第三平面中的脊部,所述脊部构造为包括在平行的第四平面中的平坦中心区域的凹部的框架,所述平行的第四平面从所述第三平面凹陷小于所述第一深度的第二深度并适合容纳所述第一半导体芯片,所述第四侧被均匀金属化,所述第二半导体芯片包括在所述第三侧和所述第四侧上具有端子的晶体管;以及
对于每个子组件,将第二半导体芯片的所述第四侧的所述金属化凹陷中心区域附接至相应第一半导体芯片的所述第二侧上的所述端子,并且将所述第二半导体芯片的所述金属化脊部附接至所述中心l-g-Si区域的相应外围组的所述焊盘,因此在所述第二半导体芯片的所述第三侧上的所述晶体管端子与在相应l-g-Si板坯的所述脊部上的所述金属层共面。
10.根据权利要求9所述的方法,其中,所述附接的工艺采用导电粘合剂。
11.根据权利要求9所述的方法,其进一步包括切割所述l-g-Si晶片以形成单独的具有嵌入在作为封装的l-g-Si板坯中的晶体管芯片的分立多输出器件的工艺。
12.根据权利要求11所述的方法,其中,所述第一半导体芯片和所述第二半导体芯片的晶体管为MOS场效应晶体管,以及所述电子系统为功率块。
13.根据权利要求11所述的方法,其中,所述第一半导体芯片和所述第二半导体芯片的晶体管为双极型晶体管,以及所述电子系统为调节器。
14.根据权利要求9所述的方法,其中,所述提供低级硅即l-g-Si的晶片的工艺包括以下工艺:
提供包括多个板坯部位的l-g-Si的晶片,所述晶片具有第一厚度和在第一平面中的第一表面;
在所述第一表面上形成第一绝缘层,所述第一绝缘层覆盖所有板坯部位;
从每个板坯部位的所述中心部分去除所述绝缘层以暴露在下面的l-g-Si,保留在所述外围部位部分上的未被去除的所述绝缘层以形成构造为每个中心部分的框架的脊部;
蚀刻每个器件部位的所述中心区域的所暴露的l-g-Si,以形成具有第二l-g-Si表面的凹部,所述第二l-g-Si表面具有在从所述第一平面凹陷第一深度的第二平面中的中心平坦部分,以及在所述第一表面和第二表面之间的斜坡;
在所述第二l-g-Si表面上形成第二绝缘层,所述第二绝缘层覆盖每个器件部位的所述中心区域;
将至少一个金属层沉积到整个晶片上;
在每个器件部位图案化所述金属层以在所述脊部上形成器件端子和在所述中心部分中的匹配晶体管端子的多个焊盘,所述焊盘被分为内部组和外围组;
将钝化层沉积到所述晶片表面上,从而覆盖所有器件部位;以及
在每个器件部位从所述框架上的所述端子和在所述中心部分中的所述焊盘去除所述钝化层,以暴露在下面的金属,同时保留在所述斜坡上和在所述焊盘之间的未被去除的钝化材料。
15.根据权利要求14所述的方法,其中,形成所述凹部的所述蚀刻工艺在所述第一平面和第二平面之间形成l-g-Si的台阶,所述台阶以<90°的角度倾斜。
16.根据权利要求14所述的方法,其中,所述晶片的所述低级硅即l-g-Si包括回收硅。
17.根据权利要求14所述的方法,其中,所述晶片的所述低级硅即l-g-Si包括粗硅。
18.根据权利要求14所述的方法,其中,所述晶片的所述低级硅即l-g-Si包括未掺杂硅。
19.根据权利要求14所述的方法,其中,所述晶片的所述低级硅即l-g-Si包括多晶硅。
20.根据权利要求19所述的方法,其中,所述多晶硅包括本征多晶硅、低掺杂n型多晶硅和/或低掺杂p型多晶硅。
21.根据权利要求14所述的方法,其中,所述金属层包括钛层、氮化钛层和铝层中的每一者。
22.根据权利要求14所述的方法,其进一步包括在铝层上沉积镍层,然后沉积最外金层的工艺。
23.根据权利要求9所述的方法,其中,所述提供多个第二半导体芯片的工艺包括以下工艺:
提供包括低电阻率块状半导体和本征半导体的外延层的半导体晶片,所述晶片具有第三厚度并且包括多个器件部位;
在每个部位中形成晶体管,所述晶体管在所述外延层的表面和所述块状半导体的表面上具有端子;
蚀刻每个部位的所述块状半导体以形成具有由块状半导体的脊部构造框架的平坦中心区域的空腔,所述中心区域具有适合容纳第一半导体芯片的尺寸和深度,但保留第三厚度的所述块状半导体框架未被蚀刻;
将至少一个金属层沉积到整个晶片的所述外延层的所述表面和所述蚀刻的块状半导体的所述表面上;
通过在每个部位的所述外延半导体的所述表面上图案化所述金属层形成金属化晶体管端子,但保留在每个部位的所述中心区域和所述空腔的所述脊部上的所述金属层未被图案化;以及
切割所述晶片以形成单独的具有金属化脊部的第三厚度的分立第二半导体芯片。
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