JP2017531995A5 - - Google Patents

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Publication number
JP2017531995A5
JP2017531995A5 JP2017522131A JP2017522131A JP2017531995A5 JP 2017531995 A5 JP2017531995 A5 JP 2017531995A5 JP 2017522131 A JP2017522131 A JP 2017522131A JP 2017522131 A JP2017522131 A JP 2017522131A JP 2017531995 A5 JP2017531995 A5 JP 2017531995A5
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JP
Japan
Prior art keywords
signal
pulse width
width modulation
clock
ramp
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Pending
Application number
JP2017522131A
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English (en)
Japanese (ja)
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JP2017531995A (ja
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Publication date
Priority claimed from US14/630,362 external-priority patent/US9793804B2/en
Application filed filed Critical
Publication of JP2017531995A publication Critical patent/JP2017531995A/ja
Publication of JP2017531995A5 publication Critical patent/JP2017531995A5/ja
Pending legal-status Critical Current

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JP2017522131A 2014-10-23 2015-09-24 ３レベル降圧コンバータを制御するための回路及び方法 Pending JP2017531995A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462067883P 2014-10-23 2014-10-23
US62/067,883 2014-10-23
US14/630,362 2015-02-24
US14/630,362 US9793804B2 (en) 2014-10-23 2015-02-24 Circuits and methods for controlling a three-level buck converter
PCT/US2015/052025 WO2016064527A1 (en) 2014-10-23 2015-09-24 Circuits and methods for controlling a three-level buck converter

Publications (2)

Publication Number Publication Date
JP2017531995A JP2017531995A (ja) 2017-10-26
JP2017531995A5 true JP2017531995A5 (enExample) 2018-01-18

Family

ID=54291640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017522131A Pending JP2017531995A (ja) 2014-10-23 2015-09-24 ３レベル降圧コンバータを制御するための回路及び方法

Country Status (5)

Country Link
US (1) US9793804B2 (enExample)
EP (1) EP3210292A1 (enExample)
JP (1) JP2017531995A (enExample)
CN (1) CN107636947A (enExample)
WO (1) WO2016064527A1 (enExample)

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