WO2012074967A1

WO2012074967A1 - Fully integrated 3-level dc/dc converter for nanosecond-scale dynamic voltage scaling with fast shunt regulation

Info

Publication number: WO2012074967A1
Application number: PCT/US2011/062319
Authority: WO
Inventors: Wonyoung Kim; David Brooks; Gu-Yeon Wei
Original assignee: President And Fellows Of Harvard College
Priority date: 2010-11-29
Filing date: 2011-11-29
Publication date: 2012-06-07

Abstract

A fully integrated 3-level DC/DC converter merges characteristics of both inductor-based buck converters and switched-capacitor converters. The 3-level converter uses both a flying capacitor and an output inductor and operates with a four step cycle. During two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage. The combination of the capacitor and inductor allows the 3-level converter to efficiently regulate the output voltage across a wide range of levels and load currents. A power supply and an integrated power distribution system using the DC/DC converter are also disclosed.

Description

FULLY INTEGRATED 3-LEVEL DC/DC CONVERTER FOR NANOSECOND- SCALE DYNAMIC VOLTAGE SCALING WITH FAST SHUNT REGULATION

GOVERNMENT RIGHTS

[0001 ] The present invention was made with government support under 0720566 awarded by the National Science Foundation. The government has certa rights in the invention.

TECHNICAL FIELD

[0002] The present invention relates to multi-level DC to DC converters.

BACKGROUND ART

[0003] In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates per-core/block dynamic voltage and frequency scaling (DVFS) with fast voltage transition. Given the high cost and bulk of off-chip DC/DC converters to implement multiple on-chip power domains, there has been a surge of interest in on-chip converters. See, for example, articles entitled "A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors," J. Wibben and R. Harjani, IEEE Journal of Solid State Circuits, v. 43, n. 4, pp. 844-854 (April 2008); "A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter," M. Alimadadi, et al., IEEE Solid State Circuits Conference, pp. 532 - 620, San Francisco, CA (2007); "A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18μηη SiGe Process," S. Abedinpour, et al., IEEE Transaction on Power Electronics, v. 22, n. 6, pp. 2164-2175 (2006); and "A 32nm Fully Integrated Reconfigurable Switched- Capacitor DC-DC Converter Delivering 0.55W/mm2 at 81 % Efficiency," H.-P. Le, et al., IEEE Solid State Circuits Conference, pp. 210-21 1 , San Francisco, CA (2010).

[0004] Other authors have disclosed inductor-based buck and switched- capacitor (SC) converters. See J. Wibben and R. Harjani, "A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors," IEEE JSSC, Apr. 2008; M. Alimadadi, et al., "A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter," ISSCC, 2007; S. Abedinpour, et al., "A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18μηη SiGe Process," ISSCC, 2006; and H. Le, et al., "A 32nm Fully Integrated Reconfigurable Switched- Capacitor DC-DC Converter Delivering 0.55W/mnn2 at 81 % Efficiency," ISSCC, 2010.

[0005] However, conventional inductor-based buck and switched-capacitor converters have drawbacks. While off-chip inductor-based buck converters show high conversion efficiency, on-chip buck converters suffer from significant losses due to the low quality inductors which can be produced on-chip. Switched capacitor converters need complex structures to provide regulated outputs with values higher than half the input voltage. DISCLOSURE OF INVENTION

[0006] In accordance with the principles of the present invention, a fully integrated 3-level DC/DC converter merges characteristics of both inductor-based buck converters and switched-capacitor converters. The 3-level converter uses both a flying capacitor and an output inductor and operates with a four step cycle. During two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage. The combination of the capacitor and inductor allows the 3-level converter to efficiently regulate the output voltage across a wide range of levels and load currents.

[0007] In one embodiment, the time durations of the four steps during each cycle are determined by a duty cycle factor. In this configuration, the output voltage is determined by the input voltage and the duty cycle factor.

[0008] In another embodiment, the duty cycle factor is regulated by a feedback loop from the output voltage in order to stabilize the output.

[0009] In still another embodiment, both an integrated capacitor and an integrated inductor are used allowing the entire circuit to be fabricated on a single die.

[0010] In yet another embodiment, the capacitor is located under the inductor using ground patterning in order to reduce the area of the circuit.

[001 1 ] In yet another embodiment, integrated capacitors are used and discrete inductor devices are mounted directly on the die.

[0012] In another embodiment, the converter comprises a stack of thin-oxide power FET devices with small parasitic capacitances whose source-drain breakdown voltage is considerably smaller than the breakdown voltages of devices in

conventional DC-DC converters. [0013] In another embodiment, a plurality of converters are connected together and driven with phased clock signals to construct a multi-phased converter with increased efficiency.

[0014] In another embodiment, a high-speed shunt regulator may be connected between the converter output and ground.

[0015] In still another embodiment, the input voltage is divided down into an intermediate voltage by a simple voltage divider that does not use inductors. This intermediate voltage is provided to each chip that requires power and an on-chip voltage regulator generates the voltages required by that chip from the intermediate voltage. In this manner multiple off-chip inductors and capacitors are avoided.

BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is an electrical schematic diagram of a 3-level power converter in accordance with the principles of the present invention.

[0017] Figures 2A-2E are electrical signal timing diagrams illustrating drive voltages applied to the converter during the four steps of a single cycle and the corresponding output voltage and current waveforms when the duty cycle factor is less than or equal to 0.5.

[0018] Figures 3A-3E are electrical signal timing diagrams illustrating drive voltages applied to the converter during the four steps of a single cycle and the corresponding output voltage and current waveforms when the duty cycle factor is greater than or equal to 0.5.

[0019] Figure 4 is a schematic block diagram of a two-phase voltage regulator with a digital feedback control and a shunt regulator.

[0020] Figure 5 is a block schematic diagram of the duty cycle calculator shown in Figure 4.

[0021 ] Figure 6A is a block schematic diagram of a digital pulse width modulation as shown in Figure 4.

[0022] Figure 6B is a block schematic diagram of level shifters and buffers used in the digital pulse width driver shown in Figure 4.

[0023] Figure 6C are waveform diagrams which occur during the operation of the circuit shown in Figure 6B.

[0024] Figure 7 is an oscillograph of the output voltage of the circuit shown in Figure 4 versus time for various voltage levels and constant load current. The inset expands the time axis showing that the output voltage level can change between 0.4 volts to 1 .4 volts in 15-20 nanoseconds.

[0025] Figure 8 is a graph of a simulation comparing peak-to-peak inductor current ripple across duty cycles of buck and 3-level converters using same switching frequencies and inductors. Thanks to much smaller inductor current ripple, the 3-level converter shows less loss due to inductor current ripple, and is able to use a small inductor and low switching frequency.

[0026] Figures 9A-9D are graphs of measured conversion efficiency across output voltage and load current ranges, and different switching frequency and phase configurations in accordance with a preferred embodiment of the present invention.

[0027] Figure 10 is a block schematic diagram of a shunt regulator which can be used with the converter of the present invention.

[0028] Figure 1 1 is a block schematic diagram of an alternative shunt regulator which can be used with the converter of the present invention

[0029] Figure shows a snapshot of voltage droops due to two consecutive

80ns wide current pulses of 100mA and 150mA that are illustrated in Figure 12B.

[0030] Figures 13A and 13B are histograms of measured voltage noise with and without shunt regulator for 4-phase and 2-phase voltage converters in

accordance with a preferred embodiment of the present invention.

[0031] Figure 14 is a graph of voltage noise with predictive shunt turned on at different times. While predicting the exact timing of the voltage droop could be difficult, voltage noise stays at the same level when the shunt turn-on time is within +-20ns of the actual droop.

[0032] Figure 15 is a plan view of a die with an inductor mounted over a flying capacitor with an intervening ground pattern.

[0033] Figure 16 shows a die fabricated for a DC to DC converter with a surface mount inductor mounted thereon.

[0034] Figure 17 is a schematic diagram of a package on package

configuration incorporating the DC to DC converters of the present invention.

[0035] Figure 18 is a schematic diagram of a configuration with a silicon interposer incorporating the DC to DC converters of the present invention.

[0036] Figure 19 is a schematic diagram of a conventional power distribution circuit. [0037] Figure 20 is a schematic diagram of a power distribution circuit incorporating the principles of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0038] As shown in Figure 1 , a 3-level voltage converter 100 constructed in accordance with the present invention comprises a set of four power FET devices connected in a series string between V_in and ground. These include P-type FET devices P_top 1 10 and P_mid 122 and N-type FET devices N_mid 124 and N_bottom 130. FETs 1 10, 122, 124 and 130 are preferably thin-oxide devices with small parasitic resistances in order to reduce conversion loss. The stacked FET structure allows the converter to support input voltages (V_in) up to twice the maximum gate-source voltage allowed for each FET device. Typical values of W/L_min for the N-type devices are 5mm/40nm to 50mm/40nm per one ampere of load current (W/L_min increases proportionately with load current). For the P-type devices W/L_min is 10mm/40 nm to 100mm/40nm per one ampere of load current.

[0039] The converter also includes a flying capacitor (Cfi_y) 140 and an output capacitor 160. Capacitors 140 and 160 may be MOSFET capacitors or high density capacitors such as deep trench capacitors or metal-insulator-metal (MiM) capacitors. High density capacitors are 20 to 30 times more area-efficient than MOSFET capacitors and can reduce the 3-level DC-DC converter area by 80-90%.

Approximately 1 nF to 50nF of capacitance is needed per one ampere of load current (capacitance increases proportionately with load current). An output inductor 150 is also part of the converter 100. Thick metal may be used to implement this inductor. Such metals are usually approximately 5um thick, compared to approximately 2um thick metals used in normal process technologies. Using these thick metal layers can help reduce 3-level DC-DC converter loss by approximately 10 percent.

Alternatively, thin-film materials may be used to implement the inductor in the 3-level DC-DC converter. Using such thin film materials can help reduce 3-level DC-DC converter loss by as much as -10%. Approximately 100pH to 20nH of inductance is needed per converter phase.

[0040] The converter is controlled by gate signals applied to the P_top, PN_mid and N_bottom FETs in a repeating switching period of time duration T. During each switching period, the gate signals iterate through four distinct steps. The time duration of each step is dependent on the switching period time duration T and a duty cycle factor D which ranges from zero to one. The gate signals fall into two distinct patterns - one pattern for D equal to or greater than 0.5 and another pattern for D less than or equal to 0.5. The gate signals for D equal to or greater than 0.5 along with the resulting output voltages and currents are shown in Figures 2A-2E. Figure 2A shows the gate signal applied to FET P_top versus time during a single switching cycle. Similarly, Figures 2B and 2C show the gate signals applied to FETs PNmici and N_bottom- Finally, Figures 2D and 2E show the resulting output voltage and output current respectively.

[0041 ] Steps 1 and 3 have equal time durations of 1 -D whereas steps 2 and 4 have equal time durations of D-0.5. During step 1 FETs 122 and 130 are conducting and FETs 1 10 and 124 are non-conducting. In this configuration, the capacitor 140 discharges through the load. During step 2 FETs 1 10 and 122 conduct and FETs 124 and 130 are non-conducting so that the output voltage is driven to V_in and the load current is regulated by inductor 150. During step 3, FETs 1 10 and 124 conduct and FETs 122 and 130 are non-conducting so that capacitor 140 charges through the load. Finally, in step 4, FETs 1 10 and 122 conduct and FETs 124 and 130 are non-conducting so that the output voltage is driven to V_in and the load current is regulated by inductor 150. Therefore, the output voltage varies between V_in and V_in/2 depending on the value of the duty cycle D.

[0042] The gate signals for D less than or equal to 0.5 along with the resulting output voltages and currents are shown in Figures 3A-3E. Figure 3A shows the gate signal applied to FET P_top versus time during a single switching cycle.

Similarly, Figures 3B and 3C show the gate signals applied to FETs PN_mid and

Nbottom- Finally, Figures 3D and 3E show the resulting output voltage and output current respectively.

[0043] Steps 1 and 3 have equal time durations of D whereas steps 2 and 4 have equal time durations of 0.5 -D. During step 1 FETs 122 and 130 are

conducting and FETs 1 10 and 124 are non-conducting. In this configuration, the capacitor 140 discharges through the load. During step 2 FETs 124 and 130 conduct and FETs 1 10 and 122 are non-conducting so that the output voltage is driven to 0 and the load current is regulated by inductor 150. During step 3, FETs 1 10 and 124 conduct and FETs 122 and 130 are non-conducting so that capacitor 140 charges through the load. Finally, in step 4, FETs 124 and 130 conduct and FETs 1 10 and 122 are non-conducting so that the output voltage is driven to 0 and the load current is again regulated by inductor 150. Therefore, the output voltage varies between 0 and V_in/2 depending on the value of the duty cycle D.

[0044] When D equals 0.5 (50%), steps 2 and 4 essentially disappear and the converter operates like a switched capacitor converter, regulating the output to approximately V_in/2. As D deviates away from 0.5, the voltage on node V_L swings between V_in/2 and V_in, or 0 and V_in/2. The square wave signal on node V_L causes inductor current (l_L) ripple to vary with D, and the output inductor 150 and capacitor 160 filter the voltage on V_L. The inventive 3-level converter 100 offers advantages over conventional inductor-based on-chip converters that either use large inductors or high switching frequencies to prevent large li_ ripple, which otherwise causes large V_L ripple and resistive loss. The frequency of voltage swing on V_L is twice the converter's switching frequency, which allows the converter to use lower switching frequencies and/or smaller inductors. Furthermore, the voltage swing on V_L reduces to Vin 2, reducing l_L ripple and parasitic switching losses.

[0045] In order to further reduce ripple on the load voltage, two or more converters, constructed as shown in Figure 1 , can be connected in parallel and driven by phased gate signals. A two-phase embodiment 400 using converters 402 and 404 is shown in Figure 4. The converters 402 and 404 are both connected to V_in 406 as indicated by lines 408 and 410 and ground as indicated by lines 412 and 414. The power FETs for each converter 402 and 404 are controlled by gate signals that are out of phase by 180 degrees. The outputs 416 and 418 of converters 402 and 404 are connected in parallel to the output line V_out (420). The output line 420 is, in turn, connected to a common output capacitor 422 and the load 424.

[0046] Because the output voltage V_out is proportional to the duty cycle factor D, a simple feedback loop can be used to stabilize the output voltage. This feedback loop includes threshold comparators 428 and 430. The output voltage V_out is provided to comparators 428 and 430 as indicated by line 426. Comparator 428 is provided with a low reference voltage. This reference voltage is typically the output voltage V_out less a reference voltage delta amount. Similarly, comparator 430 is provided with a high reference voltage, which is typically the output voltage V_out plus the reference voltage delta amount. The input polarity of comparator 428 is selected so that if the output voltage falls below the low reference voltage, the comparator 428 generates an "up" correction signal. The input polarity of comparator 430 is selected so that if the output voltage rises above the high reference voltage, the comparator 428 generates a "down" correction signal.

[0047] The Up and Down correction signals are provided to duty-cycle calculator 432 which generates a digital word representing the duty cycle. Calculator 432 responds to the Up signal by increasing the duty cycle and to the Down signal by reducing the duty cycle. A block schematic diagram of the duty-cycle calculator is shown in Figure 5. Time-to-digital converters (TDCs) 502 and 504 sample the Down and Up signals respectively to determine how long these signals stay at "1 ". This information is represented by twenty-bit digital numbers N_dOwn^< 9:0> (506) and N_up<19:0> (508). An accumulator formed by digital adders 510, 512 and 514, constantly forms a sum by adding the up number N_up<19:0> and subtracting the down number N_dOwn^< 9:0> to determine whether to increase or decrease the duty cycle to maintain the output voltage within a desired range. An 8-bit reference number N_dutyref^<7:0> is added to the output of the accumulator by adder 518. By changing N_dutyref^<7:0> together with the LO REF and HIGH REF reference signals in Figure 4, the duty cycle of the converter can be changed instantaneously for nanosecond-scale voltage scaling. The output of the duty cycle calculator block 518 is an 8-bit number N_duty<7:0> which is an 8-bit representation of the duty cycle factor.

[0048] The digital word representing the duty cycle is provided, as indicated schematically by arrow 434, to pulse width modulator driver 436. Driver 436 generates the phased sets of gate control signals 438 and 440 which control the FET switching in converters 402 and 404, respectively. Driver 438 comprises two parts, a digital pulse width modulator 600 and a three-level driver 620 which are shown in Figures 6A, 6B and 6C. Figure 6A shows the digital pulse width modulator 600 which determines the pulse-widths of the signals. This comprises a 20-phase voltage controlled oscillator (VCO) with an 8-phase interpolator 602, which together generate 160 output phases (V_phase^<159:0>). Given the duty cycle number

N_duty^<7:0>, the rising/falling edge selector 606 selects the timing of the rising and falling edges from the 160 phases and generates three square waves DPWM_top 608, DPWM_mid 610 and DPWM_bottom 612 as output signals.

[0049] The output signals 608, 610 and 612 are provided to the three level- driver circuit 620 shown in Figure 6B which shows the circuitry for one converter phase 402 of the two phase circuit 400. The driver circuitry for the other phase 402 is the same and has been omitted for clarity. The driver circuits generate the gate control waveforms for the FETs in the converter by processing the DPWM outputs DPWMtop 608, DPWMmid 610 and DPWM_bottom 612. Figure 6C illustrates the various circuit waveforms when the duty-cycle factor D is greater than or equal to 0.5. The waveforms when the duty-cycle factor D is less than or equal to 0.5 are similar.

[0050] As shown in Figure 6B, the signal DPWM_top 608 which varies between zero and V_in/2 is level-shifted by level shifter 614 so that it varies between V_in and V_in/2 and applied, via inverter/drivers 618 to the upper PFET as the gate control signal P_t0p. The DPWMbottom signal 612 is applied directly to inverter drivers 624 and applied to the bottom NFET as gate control signal N_bottom- [0051 ] Because the gate control signal PN_mid for the middle FETs spans three different levels, V_in, V_in/2, and 0, the inverter (INV_fly 626) which produces the signal uses two source voltages, V_cto_P and V_Cbottom, that are not fixed in value but instead change over different voltage levels. Because the inverter uses changing supply voltages, it is called a "flying inverter". The input signal to inverter 626 must also be shifted depending on the voltage range over which the inverter operates. In order to accomplish this shift, a second inverter INV_mid 622 is used to level shift the input signal. Inverter 622 has its input and supply voltages controlled by three-pole double throw switch 628 whose position depends on whether duty cycle D is less than or greater than 0.5. Switch 628 is shown in position when D is greater than 0.5. In this position, signal DPWM_mid 610 from digital pulse width modulation circuit 600 is level shifted to vary between V_in and V_in/2 by level shifter 616. In addition, the supply voltages for inverter 622 are V_in and V_in/2. When duty cycle factor D is less then 0.5, switch 628 is shifted so that signal DPWM_mid 610 from digital pulse width modulation circuit 600 which varies between zero and V_in/2 is directly applied to inverter 622 and the supply voltages for inverter 622 are zero and V_in/2.

[0052] Two identical converters can be connected in parallel with low- impedance switches (not shown) to create a single 4-phase converter with each phase offset by 90 degrees. Since power FETs can be disabled, multiple 3-level converter configurations comprising one to four phases are also possible.

[0053] To facilitate experimental measurements of the converter 400 shown in Figure 4, the load 424 was constructed as a programmable load that can sink up to 0.5A of current in 25mA steps as either steady current or pseudorandom current patterns. Figure 7 shows voltage data 700 from a two-phase converter constructed in accordance with the principles of the invention and captured from a real-time oscilloscope with a constant load current of 450 ma, an input voltage (V_in) of 2.4 volts and a switching frequency (1/T) of 1 15 MHz. . Figure 7 demonstrates that the converter 400 can regulate the output voltage across a wide voltage range - from 0.4 to 1 .4V as indicated by voltage steps 702-712. The inset 720 shows that voltages can be scaled by 1V within 15-20ns. Such high-speed voltage transitions at nanosecond timescales enable temporally fine-grained DVFS to improve energy efficiency of complex digital systems. See, for example, an article entitled "System level analysis of fast, per-core DVFS using on-chip switching regulators," W. Kim, et al., IEEE 14th International Symposium on High Performance Computer Architecture (HPCA-14), Salt Lake City, UT 2008.

[0054] Figure 8 is a graph produced by a simulation comparing peak-to-peak inductor current ripple across duty cycles of a conventional buck converter and an inventive 3-level converter using same switching frequencies and inductors. Thanks to much smaller inductor current ripple, the 3-level converter shows less loss due to inductor current ripple, and is able to use a small inductor and low switching frequency.

[0055] Figures 9A-9D present multiple views of conversion efficiency measurements. To facilitate efficiency measurements, the duty cycle feedback shown in Figure 4 is removed and the converter is operated with fixed duty cycle factors ranging from 0.40 to 0.65 in .05 steps. Since the duty cycle is fixed, IR drop due to parasitic resistance causes a spread in output voltages with respect to load currents for the same duty cycle. Figure 9A is a plot of all data collected across a wide range of conditions with different switching frequencies (50 to 160MHz) and differing number of phases (1 to 4), spreading out measured efficiencies.

[0056] Figure 9B focuses on measured data for 0.5 duty cycle factor operating with two and four phases. Efficiency peaks at 77% for low load current conditions. Using two phases degrades efficiency due to higher IR losses. To more easily view the results, Figure 9C represents the upper range of efficiency

measurements shown in Figure 9A by selecting the best efficiency data for each setting, and only for a 4-phase configuration. Trend line overlays again demonstrate the spread in output voltages due to IR drop. Since the 3-level converter merges characteristics of both switched capacitor and buck converters, efficiency peaks for 0.5 duty cycle factor, but gradually decreases as duty cycle factor deviates from 0.5. This trend is due to the inductor current ripple growing as duty cycle deviates from 0.5 and causing increasing resistive loss. Figure 9D adds results for 2-phase configuration (symbols with outlines) and shows that fewer phases can increase efficiency at low load currents.

[0057] In one embodiment, the converter 400 relies on a supplemental shunt regulator 442 to compensate for sudden changes in load conditions. A regulator 442 suitable for use with the converter 400 is described in detail in an article entitled "Integrated Regulation for Energy-Efficient Digital Circuits," E. Alon and M. Horowitz, IEEE Journal of Solid State Circuits, v. 43, n. 8, pp. 1795 - 1807 (Aug. 2008) which article is incorporated herein by reference in its entirety. Figure 10 is a schematic diagram of such a regulator. It comprises two comparators 1000 and 1002 and two adjustable current sources 1008 and 1010. When the voltage on the output 420 falls below a reference voltage V_ref, comparator 1000 controls current source 1008, as indicated schematically by arrow 1004, to inject current from V_in (406) into the load 424. Alternatively, when the voltage on the output 420 rises above the reference voltage V_ref, comparator 1002 controls current source 1010, as indicated

schematically by arrow 1006, to extract current from the load 424 to ground.

[0058] While a shunt regulator that reacts to threshold crossings reduces voltage fluctuations, it has two drawbacks. First, there is a limit to how quickly the reactive shunt regulator internal feedback loop can sense and react to these crossings due to internal circuit delays. Second, simply relying on thresholds provides limited information as to the magnitude of voltage noise and the appropriate response needed to suppress it. Accordingly, another embodiment uses a

prediction-based shunt regulator, which leverages prior studies that show

microarchitecture-level information can reliably predict upcoming voltage droops. A predictor for use in such a regulator is described in detail in an article entitled

"Voltage Emergency Prediction: Using Signatures To Reduce Operating Margins", V. J. Reddi, et al., IEEE 15th International Symposium on High Performance Computer Architecture (HPCA-15), Raleigh, NC 2009, which article is incorporated herein by reference in its entirety.

[0059] Figure 1 1 is a block schematic diagram of such as regulator. As with the regulator shown in Figure 10, this regulator comprises two adjustable current sources 1 108 and 1 1 10. However, the comparators 1000 and 1002 have been replaced by actuator 1 102 which is controlled by predictor 1 1 12. Predictor 1 1 12 monitors microarchitecture-level information from the load 424. When a condition is sensed that will lead to a voltage or current fluctuation, the predictor 1 1 12 controls the actuator 1 102, which, in turn, controls the current sources 1 108 and 1 1 10 to inject or extract current as necessary to reduce the fluctuation.

[0060] Figure 12A shows a snapshot of voltage droops due to two

consecutive 80ns wide current pulses of 100mA and 150mA that are illustrated in Figure 12B. Predictive current shunting reduces the maximum voltage droop by over 40% compared to simply reacting to threshold crossings.

[0061] Figures 13A and 13B are histogram plots of measured voltage noise with and without the shunt regulator turned on while pseudorandom current patterns are produced by the programmable load. Figure 13A shows the output when two converters are connected together to produce a 4-phase system and Figure 13B shows the results for a single 2-phase converter. These results verify the shunt regulator can appreciably squeeze the noise distribution together and reduce peak- to-peak voltage excursions.

[0062] Predicting the exact time of a voltage droop occurring in the future could be difficult for a predictive voltage regulator, however significant improvement can be obtained even when the prediction is approximate. Figure 14 is a graph of voltage noise where the predictive shunt is actuated at different times relative to the actual time at which a voltage droop occurs. As shown in the figure, the voltage noise stays at the same level when the shunt turn-on time is within +-20ns of the actual droop time.

[0063] In one embodiment, in order to save area on the chip, the flying capacitor used in the converter is placed under the output inductor. To avoid noise from the flying capacitor coupling to the inductor, a ground pattern is placed between the flying capacitor and the inductor. The ground pattern comprises wires connected to ground with a predetermined pattern. This arrangement is shown in Figure 15 which shows the face of the chip looking down at the output inductor. The figure illustrates an inductor spiral wire pattern 1502 under laid by a ground pattern 1504. The exact pattern used could be any of several well-known patterns. Such ground patterns are described in detail for example, in an article entitled "On-Chip Spiral

Inductors with Patterned Ground Shields for Si-Based RF IC's", C. P. Yue et al, IEEE Journal of Solid State Circuits, May 1998. This article is incorporated in its entirety by reference herein. [0064] However, instead of using spiral inductors with on-chip wires, high- quality surface-mount inductors can also be on the die as shown in Figure 16.

Figure 16 shows a cross-sectional diagram 1600 of a silicon die 1602 in which the inventive converter is fabricated. The die has a passivation layer 1604 covering its upper surface. A surface mount inductor 1606 with conductive pads 1608 and 1610 is electrically connected to the die 1602 via solder balls 1612, 1614 which extend through holes in the passivation layer 1604.

[0065] Because the inventive converter can be constructed without any large external components, it can easily be integrated into conventional die packages. Figure 17 shows the converter mounted in a conventional package-on-package configuration. The package-on-package (PoP) configuration is widely used in wireless handset circuit board in order to save circuit board area by vertically stacking processor and DRAM packages. Figure 17 is a cross sectional diagram 1700 of such a package. The components are mounted on the main printed circuit board 1702. A first printed wiring board 1706 is electrically connected to the printed circuit board 1702 at selected points by means a plurality of solder balls 1704. The application processor 1708 is mounted on the printed wiring board 1706 by a plurality of small solder balls 1710. Two DC-DC converters 1714 and 1716 can be mounted to the printer wiring board 1706 by solder balls 1718 and 1720 in order to provide power to the processor 1708.

[0066] A second printed wiring board 1722 is mounted on top of the application processor 1708. This second printed wiring board 1722 may be connected to the first printed wiring board 1706 by means of solder balls, such as solder ball 1712. On the opposite side of printed wiring board 1722, DRAM chips 1724 are mounted and can be connected to printed wiring board 1722 by leads 1726 and 1728. DC-DC converters 1730 and 1732 are mounted on top of circuit board 1722 in order to provide power to DRAM chips 1724. Converters 1730 and 1732 can also be connected to circuit board 1722 by means of leads, such as leads 1734 and 1736. A cover 1738 completes the assembly.

[0067] Figure 18 shows the inventive DC-DC converter in use with a silicon interposer. Silicon interposers are used to connect multiple dies with fine-pitch balls. The assembly mounts on a printed circuit board 1802. A printed wiring board 1804 is mounted on the printed circuit boards 1802 by means of solder balls, such as solder ball 1806, at selected locations. A silicon interposer 1808 is mounted on the printed wiring board 1804 by means of solder balls, such as solder ball 1810. Chip dies 1812 and 1814 can be mounted on the silicon interposer 1808 by fine-grained solder balls, such as solder balls 1816 and 1818. DC-DC converter dies 1820 and 1824 can also be mounted on the silicon interposer 1808 by means of fine-grained solder balls, such as solder balls 1822 and 1826 next to the chip dies 1812 and 1814.

[0068] To maintain long battery life, the battery size, which contributes to the bulk of portable electronics, cannot be reduced further. Therefore, it is crucial to minimize printed circuit board area and thickness, which is another limiting factor to making thinner and lighter electronics. Printed circuit boards contain multiple chips that are necessary for various functions of a device. These chips can be divided into two categories: chips that actually perform computation and chips that deliver power to computation chips. The chips for power delivery are called power management chips. In a high-end electronic device, such as a smartphone, the power

management chips and associated passive elements required for power

management can occupy close to half of the entire printed circuit board area.

[0069] Figure 19 illustrates the reason that the power management devices require such as large areas. Figure 19 shows a conventional way of delivering power from the battery to different chips, such as the chips typically used in a telecommunications device. The battery 1900 produces 3.7 volts. A power management chip PMIC steps the 3.7V battery voltage down to the voltage ranges that various chips can use. In the configuration shown, two separate power management chips 1902 and 1904 are used: one for chips used with the application processor (AP) 1906, including the memory chip 1908 and the other for those used with the baseband processor (BB) 1910 and its DRAM memory 1912 that handle processing of the RF signals. A conventional power management chip requires an inductor and a capacitor for each voltage that is delivered. For example inductor 1914 and capacitor 1916 are required for the 1 volt voltage delivered to the application processor 1906. Thus, five inductors and five capacitors are required for the five voltages used to power the computing chips. The bulk of high-quality passive elements required for efficient power delivery increases the printed circuit board form-factor.

[0070] In accordance with the principles of the present invention, the voltage regulators used to generate different required voltages are integrated with the chips that they supply in the manner illustrated above. This arrangement is shown in Figure 20. In Figure 20, power management chip 2002 divides the 3.7 volt voltage produced by battery 2000 voltage in half to produce an intermediate voltage (V_int) of 1 .8 volts using a simple switched-capacitor voltage divider that uses a flying capacitor 2004, but does not require an inductor.

Then, multiple integrated voltage regulators (IVRs shown as dark boxes 2014) integrated in different chip packages step down the intermediate voltage (VINT) to different voltage levels that each chip needs. Figure 20 illustrates the same chips and required voltages shown in Figure 19 (the application processor 2006 and its DRAM memory 2008 and the baseband processor 2010 and its DRAM memory

2012), but the multiple inductors and capacitors have been eliminated. This reduces the size and number of passive elements and enables a simpler PMIC chip compared to the conventional configuration. As a result, the new power delivery configuration using IVRs leads to smaller PCB form-factor and reduction in

component cost.

[0071 ] While the invention has been shown and described with reference to a number of embodiments thereof, it will be recognized by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

[0072] What is claimed is:

Claims

CLAIMS 1 . A multi-level DC to DC converter for converting an input voltage on an input terminal to an output voltage on an output terminal and comprising:

an even plurality of FET transistors connected in a series string between the input terminal and a ground terminal;

a capacitor connected in parallel across at least two of the FET transistors located at a center of the series string;

an inductor connected between the center of the series string and the output terminal; and

a driver circuit that generates gate control signals for each of the plurality of FET transistors in a repetitive four step cycle, the gate control signals being timed so that during two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage.

2. The DC to DC converter of claim 1 wherein a time duration of each four step cycle is fixed and time durations of the four steps during each four step cycle are determined by a duty cycle factor and wherein the output voltage is determined by the input voltage and the duty cycle factor.

3. The DC to DC converter of claim 2 wherein the driver circuit comprises a

plurality of level shifters, each of which receives a control signal from a driver circuit that is responsive to the duty cycle factor.

4. The DC to DC converter of claim 2 further comprising a feedback loop which responds to the output voltage by calculating the duty cycle factor in order to stabilize the output voltage.

5. The DC to DC converter of claim 1 wherein the capacitor and the inductor are fabricated as integrated devices on the same die on which the FET transistors are fabricated.

6. The DC to DC converter of claim 5 wherein the capacitor is located under the inductor with a ground pattern between the capacitor and the inductor.

7. The DC to DC converter of claim 1 wherein the capacitor is integrated in a die and the inductor is a discrete surface mount inductor mounted directly on the die.

8. The DC to DC converter of claim 1 wherein each of the plurality of FET

transistors is a thin-oxide power FET device with small parasitic capacitance having a source-drain breakdown voltage less than the input voltage.

9. The DC to DC converter of claim 1 further comprising a shunt regulator

connected between the input terminal and ground and being configured to inject current into the output terminal or extract current from the output terminal in response to changes in the output voltage.

10. An integrated power supply for converting an input voltage on an input

terminal to an output voltage on an output terminal and comprising:

a plurality of DC to DC converters, each DC to DC converter having an even plurality of FET transistors connected in a series string between the input terminal and a ground terminal,

a capacitor connected in parallel across at least two of the FET transistors located at a center of the series string, and

an inductor connected between the center of the series string and the output terminal;

a driver circuit that generates gate control signals for each of the plurality of FET transistors in each DC to DC converter in a repetitive four step cycle, the gate control signals being timed so that during two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage; and

a control circuit which controls the driver circuits to apply gate control signals to each DC to DC converter so that gate control signals for the DC to DC converters differ in phase.

1 1 . The power supply of claim 10 wherein a time duration of each four step cycle is fixed and time durations of the four steps during each four step cycle are determined by a duty cycle factor.

12. The power supply of claim 10 further comprising a feedback loop which

responds to the output voltage by calculating the duty cycle factor in order to stabilize the output voltage.

13. The power supply of claim 12 wherein the feedback loop comprises a

comparator device that generates correction signals when the output voltage departs from a predetermined value and a duty cycle calculator that responds to the correction signals by calculating a duty cycle factor.

14. The power supply of claim 1 1 further comprising a pulse width modulation circuit which is responsive to the duty cycle factor for generating control signals that define the four step cycle.

15. The power supply of claim 14 further comprising a level shifter circuit that is responsive to the control signals for generating the gate control signals.

16. The power supply of claim 10 further comprising a shunt regulator connected between the input terminal and ground and being configured to inject current into the output terminal or extract current from the output terminal in response to changes in the output voltage.

17. The power supply of claim 16 wherein the shunt regulator is one of a reactive shunt regulator and a predictive shunt regulator.

18. A distribution system for receiving an input voltage and distributing therefrom a plurality of different voltage values to a plurality of integrated semiconductor device chips comprising: a voltage divider that divides the input voltage down to an intermediate voltage;

a distribution bus that provides the intermediate voltage to each device chip that requires power; and

at least one integrated voltage regulator that requires power that receives the intermediate voltage and generates voltage values required by the chips from the intermediate voltage, the integrated voltage regulator having a plurality of FET transistors connected in a series string between the intermediate voltage and a ground, a capacitor, an inductor and a driver circuit that generates gate control signals for each of the plurality of FET transistors in a repetitive four step cycle, the gate control signals being timed so that during two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage.

19. The distribution system of claim 18 wherein the capacitor and the inductor are fabricated as integrated devices on the semiconductor device chip.

20. The distribution system of claim 18 wherein each voltage regulator comprises a driver circuit that generates gate control signals for each of the plurality of FET transistors in a repetitive four step cycle, the gate control signals being timed so that during two steps of the four step cycle the capacitor regulates the output voltage and during the remaining two steps, the inductor regulates the output voltage.

21 . The distribution system of claim 18 wherein at least one of the semiconductor device chips is a package on package chip having multiple levels above a base printed circuit board and the at least one integrated voltage regulator is located on at least one of the multiple levels.

22. The distribution system of claim 18 wherein at least one of the semiconductor device chips has a silicon interposer mounted thereon and the at least one integrated voltage regulator is located on the silicon interposer.