JP2020501488A - Battery charging system - Google Patents

Abstract

A switching charging circuit connected to the four series-connected MOSFET transistors; a flying capacitor connected across two of the four series-connected MOSFET transistors; an output inductor between two of the four series-connected transistors; And a node connected to and forming a buck and a regulator. Embodiments of the charging system can increase efficiency, reduce the size and inductance of the output inductor, and provide a low voltage process. [Selection diagram] FIG.

Description

<Related application>
This application is related to US patent application Ser. No. 15 / 828,158 filed on Nov. 30, 2017 and US Provisional Applications Nos. , 058 claims priority. The contents of these documents are hereby incorporated by reference in their entirety for all purposes.

  Embodiments of the present invention relate to a charging system, specifically to a battery charging system.

  There is an increasing demand for using mobile devices that include battery charging. In particular, battery charging of mobile devices is desirably fast and efficient. Many battery charges have two series connected transistors that are configured to form a Buck regulator and are driven by a control circuit to function as a switching charger. However, in order to keep the size of the inductor in the Buck regulator small and to keep the DC resistance (DCR) of the inductor small, the super-column connection transistor may be switched at a high frequency (2-4 MHz).

  To meet fast charging requirements (eg, battery charging current of 3A or more), the bus voltage is raised to 9V, 12V or more, thereby meeting the VBUS pin current requirements of the Universal Serial Bus (USB) microconnector. I have. However, high VBUS voltages cause even greater switching losses at high switching frequencies, which switching losses are proportional to the voltage between the two series connected transistors. Also, using a high VBUS voltage increases the ripple current in the output inductor, and high voltage processing requires large components, thereby increasing die size and increasing cost. Further, as the transistor size increases, conduction loss decreases, but switching loss increases.

  Therefore, there is a need for better and more efficient battery charging systems.

  In an aspect of the invention, a charging system includes: a first transistor connected to receive a bus voltage; a second transistor connected in series with the first transistor; A third transistor connected in series; a fourth transistor connected between ground and the third transistor; controlling a gate of each of the first transistor, the second transistor, the third transistor, and the fourth transistor A flying capacitor connected across the second transistor and the fourth transistor, wherein a node between the second transistor and the fourth transistor is an output inductor. And the switching control circuit is connected to Serial first transistor, the second transistor is configured to provide a system voltage accompanied to switch the third transistor, and the fourth transistor.

  A charging method according to an embodiment includes: receiving a bus voltage across four serially connected transistors; driving two gates of the four serially connected transistors to drive the four serially connected transistors. Charging a flying capacitor connected across two of the transistors; two of the four series connected transistors having a node that can be connected to an output inductor to provide a system voltage. Driving the gate of the transistor.

  These and other embodiments are described below with reference to the following drawings.

1 shows a conventional battery charging system.

1 shows a battery charging system according to an embodiment of the present invention.

  In the following description, details describing the embodiments of the present invention will be described. However, it will be apparent to one skilled in the art that the embodiments may be practiced without some or all of these details. The specific embodiments disclosed herein are illustrative and not restrictive. One of ordinary skill in the art would be able to realize other embodiments within the scope and spirit of the present disclosure, even if not explicitly described herein.

  The present specification and accompanying drawings, which illustrate aspects and embodiments of the invention, are not to be considered as limiting. The claims define the protection scope of the present invention. Various changes may be made without departing from the spirit and scope of the specification and claims. In other instances, well-known structures and techniques have not been shown or described in detail in order not to obscure the present invention.

  Elements and related aspects described in detail with reference to certain embodiments may, where practicable, be included in other embodiments not explicitly shown or described. For example, if an element is described in detail with reference to one embodiment and not described with reference to another embodiment, the element may be claimed as being included in another embodiment.

FIG. 1 shows a conventional charging system 100. The charging system 100 includes a switching charge control circuit 110 that is connected to and driven by the gates of the transistors 130 (Q1), 132 (Q2), and 134 (Q3). Transistor 130 (Q1) is a battery backflow blocking transistor, closed by controller 110 when external voltage _VBUS is present, and opened when it is not.

  The transistors 132 (Q2) and 134 (Q3) are connected in series between the block transistor 130 and the ground. The node between transistors 132 and 134 is connected to inductor 120, which is connected in series with output capacitor 136. Transistors 132 and 134 and inductor 120 form a buck regulator that functions as a switching charger. The system voltage is provided by inductor 120 and can be used to power an external system. In addition, the system voltage connects to switch transistor 122 to supply or receive power from battery pack 150. Transistor 122 (Q 4) is a battery switch that has a gate connected to supply power to power path control circuit 140 and controls a power path to battery pack 150. The transistors 130, 132, 134, 122 are, for example, MOSFET transistors.

The control circuit 110 receives inputs V _BUS , I _Batt , V _Batt , and T _Batt . Voltage V _BUS is an input DC voltage from an external power source. The voltage V _BUS is connected to the high voltage side of the series-connected transistors 132 and 134 via the block transistor 131. Input I _Batt indicates the current to or from battery pack 150 and is measured by current sensor 126. The current sensor 126 is connected to measure the current from the battery 152 of the battery pack 150 via the transistor 122. Voltage V _Batt is determined by voltage sensor 128. Voltage sensor 128 is connected across battery pack 150 and indicates battery voltage. Temperature signal T _Batt is received from temperature monitor 154 in battery pack 150.

Control circuit 110 drives the gates of switching transistors 132 and 134 to provide power to function with the inductor 120 and capacitor 136 as a Buck regulator. The voltage from inductor 120 is connected to battery pack 150 via transistor 122, thereby charging battery 152 of battery pack 150. The gate of the transistor 122 is connected to the power path control circuit 124. The power path control circuit 124 controls the power path according to the battery temperature T _Batt , the current I _{Batt, and the} battery voltage V _Batt , and if necessary, To charge or discharge.

  System 100 has a number of operational challenges. In embodiments, transistors 132 (Q2) and 133 (Q3) need to switch at a high frequency (2-4 MHz). High frequency switching keeps the inductance of inductor 120 low (e.g., 0.47 [mu] H in some applications), reduces the DC resistance (DCR) value of inductor 120, physically miniaturizes inductor 120, and reduces inductor 120 The efficient operation of the capacitor 136 is enabled. However, the high switching frequency increases switching losses and offsets at least a portion of the efficient gain obtained from the low DCR of inductor 120.

  Further, in order to satisfy the current demand for high-speed charging, it is necessary to increase the bus voltage VBUS. These increased bus voltages also meet the VBUS pin current requirements of USB micro connectors. For example, a battery charging current of 3 A or more requires a VBUS voltage of 9 V to 12 V to satisfy these requirements. However, a high VBUS voltage causes more switching losses at high switching frequencies. Switching loss is proportional to the voltage crossing transistors 132 (Q2) and 134 (Q3) because this is the VBUS voltage. The high VBUS voltage also increases the ripple current in inductor 120, which causes more ripple voltage in system voltage VSYS. In order to reduce the ripple voltage of VSYS, the switching frequency should be increased while keeping the inductance of inductor 120 the same, which further increases switching losses and reduces the efficiency of system 100.

  Also, the high VBUS voltage requirement requires a high voltage process, which requires larger circuit elements. This increases die size and increases manufacturing costs to meet efficiency requirements. As MOSFET size increases (resistance Rdson value decreases), conduction losses decrease, but as size increases, switching losses increase. Therefore, reducing MOSFET conduction losses to achieve high efficiency of system 100 is limited.

Embodiments of the present invention provide a method for improving the switching charging system 100 shown in FIG. Specifically, there is a need to switch at low frequencies while providing output inductors with low inductance and small physical size. This further reduces DCR, increases system efficiency, and reduces ripple current to meet the ripple voltage requirement of system voltage _VSYS .

Embodiments in accordance with the present invention provide a new switching charging arrangement to enable lower switching frequencies without penalty for increasing inductor size. This switching arrangement also reduces switching losses, thereby increasing system efficiency. In addition, the new switching arrangement allows high input voltages to be handled using a low voltage process, further reducing the die size and manufacturing cost of the charger. Also by the new arrangement, fast charge current (eg over 3A) together is _possible, it is possible to maintain the _{V BUS} current below the current limit of the USB (1.8A) or TypeC connector (2.5A). Furthermore, by increasing the transistor size (reducing the Rdson value), the transistor conduction loss can be further reduced without increasing the switching loss.

FIG. 2 shows a switching charging system 200 according to an embodiment of the present invention. As shown in FIG. 2, the switching charge control circuit 210 is connected to the gates of the series-connected transistors 230 (Q2), 232 (Q3), 234 (Q4), and 236 (Q5). Further, a capacitor 240 (C _FLY ) is provided across a series connected pair of transistors 232 (Q3) and 234 (Q4). Output inductor 230 is connected to the node between transistors 232 and 234 and is smaller (both physical size and inductance) than output inductor 120 shown in FIG. The series connected transistors 230, 232, 234, 236 can be driven independently to allow the system 200 to operate seamlessly at any duty cycle (eg, 1% to 99%).

The voltage crossing the series connected transistors 232 (Q3) and 234 (Q4) during normal operation may be half the input voltage on VBUS due to the introduction of the capacitor 240 (C _FLY ) crossing them. As a result, the switching loss of each of the transistors 230, 232, 234, 236 is one fourth that of the system 100 shown in FIG. There are four series connected MOSFETs 230, 232, 234, 236, but when switching at the same frequency, the total switching loss is half that of system 100. The system 200 further allows for using a low voltage process with a high VBUS voltage (VBUS / 2). This is because transistors 232 and 234 are switched at half the bus voltage.

  Further, the voltage across inductor 220 during normal operation is less than half that of inductor 120 of FIG. Thus, the inductor value of inductor 220 may be less than half of inductor 120 of FIG. 1 at the same switching frequency and the same VBUS voltage. As shown in FIG. 2, the efficiency of the system 200 can be improved over the system 100 by making the inductor 220 smaller with small inductance and small DCR. If the VBUS voltage can be adjusted based on the VSYS value to maintain VBUS at twice VSYS (eg, using a USB PD), the inductance of inductor 220 can be further reduced. Further, the inductance of the inductor 220 can be made the same as that of the inductor 120, and the switching frequency can be reduced. This further increases system efficiency.

As a result, embodiments of the present invention include series connected switching transistors 230 (Q2), 232 (Q3), 234 (Q4), 236 (Q5), and between the transistors 232 (Q3) and 234 (Q4). Connected to a flying capacitor 240C _FLY . This arrangement is combined with the output inductor 220 to reduce the size and inductance of the output inductor 220 by adjusting the VBUS voltage according to VSYS to maintain VBUS near twice VSYS, reduce the switching frequency, and reduce the system efficiency. And a low voltage process can be used to meet the high VBUS voltage. Furthermore, low voltage reduces die size and cost.

As shown in FIG. 2, transistors 230 and 236 operate to charge flying capacitor 240 when transistors 232 and 234 operate as switching capacitors to drive the buck regulator formed by inductor 220. In an embodiment, each MOSFET is individually driven using an efficient driving scheme for the four transistors 230, 232, 234, 236 (Q2-Q5), allowing the system 200 to be seamless with a 1% -99% duty cycle. Can work. The system 200 also has a minimum external bootstrap capacitor (C _BYP on bypass circuit and bus voltage capacitor C _IN , shown only in system 200 of FIG. 2). Also, the system 200 can control the VBUS voltage to twice the VSYS voltage to achieve optimal efficiency. In addition, the voltage across the flying capacitors can be varied to meet optimal line and load transient requirements.

  The above detailed description is provided to explain the specific embodiments of the present invention and is not intended to be limiting. Various modifications and changes are possible within the scope of the present invention. The invention is set forth in the following claims.

Claims (14)

A charging system,
A first transistor connected to receive a bus voltage;
A second transistor connected in series with the first transistor;
A third transistor connected in series to the first transistor and the second transistor,
A fourth transistor connected between ground and the third transistor;
A switching control circuit connected to control a gate of each of the first transistor, the second transistor, the third transistor, and the fourth transistor;
A flying capacitor connected across the second transistor and the fourth transistor,
With
A node between the second transistor and the fourth transistor is connected to an output inductor, and the switching control circuit connects the first transistor, the second transistor, the third transistor, and the fourth transistor. A system configured to provide a system voltage upon switching. The charging circuit according to claim 1, wherein a bus switching transistor is connected between the first transistor and the bus voltage. The system of claim 1, wherein the system voltage is connected to a battery pack via a power path switching transistor. The system of claim 1, wherein a power path switching transistor is connected to the power path controller. The system according to claim 4, wherein the output inductor is arranged such that the bus voltage is twice the system voltage. The system of claim 1, wherein the first transistor and the fourth transistor are operated by the control circuit such that a voltage across the flying capacitor changes according to line and load transients. The system of claim 1, wherein the second transistor and the third transistor operate at a duty cycle between 1% and 99%. A charging method,
Receiving a bus voltage across four series connected transistors;
Driving two gates of the four serially connected transistors to charge a flying capacitor connected across two of the four serially connected transistors;
Driving the gates of two of the four series connected transistors having a node that can be connected to an output inductor to provide a system voltage;
A method comprising: The method of claim 8, wherein the method further comprises activating a transistor connected between the bus voltage and the four serially connected transistors. The method of claim 8, wherein the system voltage is connected to charge a battery pack. The method of claim 10, further comprising activating a switching transistor connected between the system voltage and the battery pack. The method of claim 8, wherein the bus voltage is twice the system voltage. The method of claim 8, wherein the flying capacitor is charged according to line and load transients. 9. The method of claim 8, wherein driving two gates of the four series-connected transistors having nodes comprises driving the gate with a duty cycle of 1% to 99%. .