JP6898447B2 - Battery charging system - Google Patents

Description

<Related application>
This application applies to US patent applications 15 / 828, 158 filed November 30, 2017, and US provisional applications 62 / 428,737, 62 / 429,056, 62/429 filed December 1, 2016. , 058 claim priority. The contents of these documents are all incorporated herein by reference for all purposes.

Embodiments of the present invention relate to a charging system, specifically a battery charging system.

There is an increasing demand for the use of mobile devices, including battery charging. In particular, battery charging of mobile devices is desirable to be fast and efficient. Many battery charges have two transistors connected in series, which are configured to form a Buck regulator and are driven by a control circuit to act as a switching charger. However, in order to keep the size of the inductor in the Buck regulator small and the DC resistance (DCR) of the inductor small, the super column connection transistor may be switched at a high frequency (2 to 4 MHz).

To meet fast charging requirements (eg battery charging current above 3A), the bus voltage can be raised to 9V, 12V or higher, thereby satisfying the VBUS pin current requirement for universal serial bus (USB) microconnectors. There is. However, high VBUS voltage causes even greater switching loss at high switching frequencies, which is proportional to the voltage between the two series-connected transistors. Further, when a high VBUS voltage is used, the ripple current of the output inductor increases, and the high voltage processing requires a large component, which increases the die size and the cost. Further, as the transistor size increases, the conductive loss decreases, but the switching loss increases. Therefore, there is a need for a better and more efficient battery charging system. Patent Documents 1 to 5 are techniques related to the present application.

US 2009/0033293 A1 US 9,431,845 B2 US 2015/0188362 A1 US 2016/0329809 A1 US 2016/0261190 A1

In aspects of the invention, the charging system is: a first transistor connected to receive a bus voltage; a second transistor connected in series with the first transistor; with respect to the first transistor and the second transistor. A third transistor connected in series; a fourth transistor connected between the ground and the third transistor; controls the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor. A switching control circuit connected so as to; a flying capacitor connected by crossing the second transistor and the third transistor; the node between the second transistor and the third transistor is an output inductor. The switching control circuit is configured to provide system voltage as it switches between the first transistor, the second transistor, the third transistor, and the fourth transistor.

The charging method according to the embodiment is: a step of crossing four series-connected transistors to receive a bus voltage; driving two gates of the four series-connected transistors and connecting the four series. The step of charging a flying capacitor connected so as to intersect two of the transistors; two of the four series connected transistors having a node capable of connecting to an output inductor to provide system voltage. It has a step of driving the gate of the transistor;

These and other embodiments will be described later with reference to the drawings below.

Shown is a conventional battery charging system.

The battery charging system according to the embodiment of the present invention is shown.

In the following description, the details for explaining the embodiment of the present invention will be described. However, it is clear to those skilled in the art that embodiments can be implemented without some or all of these details. The specific embodiments disclosed herein are for illustration purposes only and not for limitation purposes. One of ordinary skill in the art will be able to realize other embodiments included in the scope and intent of the present disclosure, even if not expressly provided herein.

The present specification and accompanying drawings showing aspects and embodiments of the invention should not be considered limiting. The claims define the scope of protection of the present invention. Various changes can be made without departing from the spirit and scope of this specification and the claims. In order not to obscure the present invention, the known structures and techniques are not shown or described in detail in the examples.

Elements described in detail with reference to one embodiment and related aspects can also be included in other embodiments not explicitly illustrated or described, if feasible. For example, if an element is described in detail with reference to one embodiment and not described with reference to another embodiment, the element can be claimed as being included in another embodiment.

FIG. 1 shows a conventional charging system 100. The charging system 100 includes a switching charge control circuit 110 that is connected to and driven by the gates of transistors 130 (Q1), 132 (Q2), and 134 (Q3). The transistor 130 (Q1) is a battery backflow block transistor, which is closed by the controller 110 when the external voltage VBUS is present and opened when it is not present.

The transistors 132 (Q2) and 134 (Q3) are connected in series between the block transistor 130 and the ground. The node between the transistors 132 and 134 is connected to the inductor 120, which is connected in series with the output capacitor 136. The transistors 132, 134 and the inductor 120 form a back regulator that functions as a switching charger. The system voltage is provided by the inductor 120 and can be used to power the external system. Further, the system voltage is connected to the switch transistor 122 to supply or receive power from the battery pack 150. The transistor 122 (Q4) is a battery switch having a gate connected to supply power to the power path control circuit 140 and controlling the power path to the battery pack 150. Transistors 130, 132, 134, 122 are, for example, MOSFET transistors.

The control circuit 110 receives the inputs VBUS, IBatt, VBatt, and TBatt. The voltage VBUS is an input DC voltage from an external power source. The voltage VBUS is connected to the high voltage side of the series connection transistors 132 and 134 via the block transistor 131. The input IBatt indicates the current to or from the battery pack 150 and is measured by the current sensor 126. The current sensor 126 is connected via a transistor 122 to measure the current from the battery 152 of the battery pack 150. The voltage VBatt is determined by the voltage sensor 128. The voltage sensor 128 is connected across the battery pack 150 to indicate the battery voltage. The temperature signal TBatt is received from the temperature monitor 154 in the battery pack 150.

The control circuit 110 drives the gates of the switching transistors 132 and 134 to provide power to function as a Buck regulator along with the inductor 120 and the capacitor 136. The voltage from the inductor 120 is connected to the battery pack 150 via the transistor 122, thereby charging the battery 152 of the battery pack 150. The gate of the transistor 122 is connected to the power path control circuit 124, which controls the power path according to the battery temperature TBatt, the current IBatt, and the battery voltage VBatt to charge or charge the battery pack 150 as needed. Discharge.

The system 100 has a plurality of problems in operation. In the embodiment, the transistors 132 (Q2) and 133 (Q3) need to be switched at a high frequency (2-4 MHz). High frequency switching keeps the inductance of the inductor 120 low (eg 0.47 μH in some applications), reduces the DC resistance (DCR) value of the inductor 120, physically miniaturizes the inductor 120, and makes it with the inductor 120. It enables efficient operation of the capacitor 136. However, the high switching frequency increases the switching loss and offsets at least a portion of the efficient gain obtained from the low DCR of the inductor 120.

Further, in order to meet the current high-speed charging requirement, it is necessary to increase the bus voltage VBUS. These increased bus voltages also meet the VBUS pin current requirements for USB microconnectors. For example, a battery charging current of 3A or more requires a VBUS voltage of 9V to 12V to meet these requirements. However, high VBUS voltage causes more switching loss at high switching frequencies. This is because the switching loss is proportional to the voltage at which the transistors 132 (Q2) and 134 (Q3) intersect, which is the VBUS voltage. The high VBUS voltage also increases the ripple current in the inductor 120, which results in more ripple voltage at the system voltage VSYS. In order to reduce the ripple voltage of VSYS, the switching frequency should be increased while maintaining the same inductance of the inductor 120, which further increases the switching loss and reduces the efficiency of the system 100.

Also, the high VBUS voltage requirement requires a high voltage process, which requires larger circuit elements. This increases the die size and increases the manufacturing cost to meet the efficiency requirements. As the MOSFET size increases (the resistance Rdson value decreases), the conductive loss decreases, but as the size increases, the switching loss increases. Therefore, there is a limit to reducing MOSFET conductivity loss in order to achieve high efficiency of the system 100.

Embodiments of the present invention provide a method of improving the switching charging system 100 shown in FIG. Specifically, there is a need for switching at low frequencies while providing an output inductor with low inductance and physical size. This further reduces DCR, increases system efficiency, and reduces ripple current to meet the ripple voltage requirements of the system voltage VSYS.

Embodiments of the present invention provide a new switching charge arrangement to allow low switching frequencies without incurring a penalty of increased inductor size. This switching arrangement also reduces switching loss, thereby increasing system efficiency. In addition, the new switching arrangement allows high input voltages to be handled using low voltage processes, further reducing the die size and manufacturing costs of the charger. In addition, the new arrangement enables high-speed charging current (eg, 3A or more) and keeps VBUS current below the current limit of USB (1.8A) or Type C connector (2.5A). Further, the transistor size can be increased (the Rdson value becomes smaller) to further reduce the transistor conductive loss without increasing the switching loss.

FIG. 2 shows a switching charging system 200 according to an embodiment of the present invention. As shown in FIG. 2, the switching charge control circuit 210 is connected to the gates of the series connection transistors 230 (Q2), 232 (Q3), 234 (Q4), and 236 (Q5), respectively. Further, the capacitor 240 (CFLY) is provided by crossing a series connection pair of transistors 232 (Q3) and 234 (Q4). The output inductor 230 is connected to the node between the transistors 232 and 234 and is smaller than the output inductor 120 shown in FIG. 2 (both physical size and inductance). The series connection transistors 230, 232, 234, and 236 can be driven independently to allow the system 200 to operate seamlessly in any duty cycle (eg: 1% to 99%).

The voltage that intersects the series connection transistors 232 (Q3) and 234 (Q4) during normal operation may be half the input voltage on the VBUS by introducing the capacitor 240 (CFLY) that intersects them. As a result, the switching loss of each of the transistors 230, 232, 234, and 236 is one-fourth that of the system 100 shown in FIG. 1 at the same switching frequency. There are four series-connected MOSFETs 230, 232, 234, 236, but when switching at the same frequency, the total switching loss is half that of system 100. System 200 also allows the use of low voltage processes at high VBUS voltages (VBUS / 2). This is because the transistors 232 and 234 are switched at half the bus voltage.

Further, the voltage crossing the inductor 220 during normal operation is less than half that of the inductor 120 of FIG. Therefore, the inductor value of the inductor 220 may be less than half that of the inductor 120 of FIG. 1 at the same switching frequency and the same VBUS voltage. As shown in FIG. 2, the efficiency of the system 200 can be improved as compared with the system 100 by making the inductor 220 smaller by the small inductance and the small DCR. If the VBUS voltage can be adjusted based on the VSYS value to maintain VBUS twice as high as VSYS (eg, using a USB PD), the inductance of the inductor 220 can be further reduced. Further, the inductance of the inductor 220 can be made the same as that of the inductor 120, and the switching frequency can be reduced. This further increases system efficiency.

As a result, embodiments of the present invention include series-connected switching transistors 230 (Q2), 232 (Q3), 234 (Q4), 236 (Q5) and between the transistors 232 (Q3) and 234 (Q4). The flying capacitor 240CFLY connected to is provided. This arrangement is combined with the output inductor 220 to reduce the size and inductance of the output inductor 220 and reduce the switching frequency by adjusting the VBUS voltage according to VSYS to keep the VBUS nearly twice the VSYS and system efficiency. A low voltage process can be used to improve and satisfy the high VBUS voltage. In addition, the low voltage reduces die size and cost.

As shown in FIG. 2, the transistors 230 and 236 operate to charge the flying capacitor 240 when the transistors 232 and 234 operate as switching capacitors to drive a back regulator formed by the inductor 220. In an embodiment, each MOSFET is individually driven using an efficient drive scheme of four transistors 230, 232, 234, 236 (Q2-Q5) to seamlessly drive the system 200 with a duty cycle of 1% to 99%. Can be operated. The system 200 also includes a minimum external bootstrap capacitor (CBYP and bus voltage capacitor CIN on the bypass circuit, shown only in system 200 of FIG. 2). Further, the system 200 can control the VBUS voltage to twice the VSYS voltage to realize the optimum efficiency. In addition, the voltage across the flying capacitors can be varied to meet optimum line and load transient requirements.

The above detailed description is provided for explaining a specific embodiment of the present invention, and is not intended to be limited. Various modifications and changes are possible within the scope of the present invention. The present invention is presented by claims.

Claims (14)

It ’s a charging system,
First transistor connected to receive bus voltage,
A second transistor connected in series with the first transistor,
A third transistor connected in series to the first transistor and the second transistor,
A fourth transistor connected between the ground and the third transistor,
A switching control circuit connected to control the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor.
A flying capacitor, in which the second transistor and the third transistor are crossed and connected.
With
The node between the second transistor and the third transistor is connected to the output inductor, and the switching control circuit connects the first transistor, the second transistor, the third transistor, and the fourth transistor. It is configured to provide the system voltage as it switches.
The first transistor and the fourth transistor operate to charge the flying capacitor, and the second transistor and the third transistor operate as switching transistors separately from the first and fourth transistors. A system characterized by driving the output transistor. Wherein between the first transistor and the bus voltage, the system of claim 1, wherein the bus switching transistor is connected. The system according to claim 1, wherein the system voltage is connected to the battery pack via a power path switching transistor. The system according to claim 3 , wherein a power path switching transistor is connected to the power path controller. The system according to claim 4, wherein the second transistor and the third transistor are arranged so that the bus voltage is twice the system voltage. The first transistor and the fourth transistor are characterized in that they are operated by the control circuit so that the voltage crossing the flying capacitor changes according to the line connected to the system voltage and the load transient state. The system according to claim 1. The system according to claim 1, wherein the second transistor and the third transistor operate in a duty cycle of 1% to 99%. It ’s a charging method,
Comprising: receiving the bus voltage crosses the transistors series connected, said series connected transistors, the first transistor connected to the bus voltage, a second coupled to the first transistor A step, comprising a transistor, a third transistor connected to the second transistor, and a fourth transistor connected to the third transistor and ground .
Drives the gate of the fourth transistor and the first transistor of the series connected transistors, connected flying to intersect the third transistor and the second transistor of the series connected transistors Steps to charge the transistor,
The gate of the third transistor and the second transistor of the series connected transistors, a node between said second transistor capable of providing a system voltage connected to the output inductor and the third transistor A step of driving the first transistor and the gate of the fourth transistor separately.
A method characterized by having. The method further method of claim 8, characterized in that it comprises a step of activating a transistor connected between said bus voltage and the series-connected separate transistors. 8. The method of claim 8, wherein the system voltage is connected to charge the battery pack. 10. The method of claim 10, further comprising activating a switching transistor connected between the system voltage and the battery pack. The method according to claim 8, wherein the bus voltage is twice the system voltage. 8. The method of claim 8, wherein the flying capacitor is charged according to a line connected to the system voltage and a load transient state. The step of driving the gate of said series connected second transistor and the third transistor having a node connected to said output inductor, it comprises the step of driving the gate 1% to 99% duty cycle 8. The method according to claim 8.

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