JP2006149125A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce undershoot that occurs when a through switch is turned off, in a step-down DC-DC converter provided with a through switch that connects between input and output terminals. <P>SOLUTION: This DC-DC converter is provided with voltage-dropping portion comprising a first switching element, a rectifier, an inductor, and a smoothing means. An input voltage from the input terminal is dropped to a voltage lower than the input voltage and outputted by controlling the switching of the first switching element and the rectifier alternately. This DC-DC converter includes a current control portion connected in parallel to the voltage-dropping portion between the input and output terminals and a drive portions that controls the conduction state and interruption state of the current control portion according to a control signal inputted from a control terminal and that, when the current control portion is put into the interruption state, controls a current flowing in the current control portion in such a way that it decreases taking a predetermined period of time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a DC-DC converter. In particular, the present invention relates to a switching step-down DC-DC converter including a current control element that connects an input terminal and an output terminal.

  In portable devices and the like, a step-down DC-DC converter is used to step down an input voltage to a lower desired output voltage and supply it to a load circuit. For portable devices and the like, low power consumption is required in order to enable long-term use with a single charge of the battery, and accordingly, a highly efficient DC-DC converter is required. Has been. When a battery is used as the input power supply voltage of the DC-DC converter, in order to make the driving time of the DC-DC converter as long as possible, the lower the operation input voltage of the DC-DC converter itself is better. A step-down DC-DC converter that operates with an input voltage as close as possible to the output voltage is desirable.

  The step-down DC-DC converter has a switching element and a rectifier connected in series between a power supply voltage and a ground voltage, and has an inductor connected to a connection point between the switching element and the rectifier. By controlling the switching element and the rectifier alternately on / off, an output voltage lower than the power supply voltage is output via the inductor. The output voltage can be controlled by adjusting the ratio (duty ratio) δ of the on-time occupying one switching cycle of the switching element. Assuming that the on-time of the switching element is Ton, the off-time of the switching element is Toff, the power supply voltage (input voltage) is Vin, and the output voltage is Vout, the output voltage of the step-down DC-DC converter is ideally It is represented by (1) and (2).

δ = Ton / (Ton + Toff) (1)
Vout = δ × Vin (2)

  As can be seen from the above equations (1) and (2), in the step-down DC-DC converter, the duty ratio δ is controlled to increase as the input voltage Vin decreases and approaches the desired output voltage Vout, When the input voltage Vin = the output voltage Vout, the duty ratio δ reaches 100%. However, in reality, a voltage drop due to the on-resistance of the switching element and the parasitic resistance of the inductor occurs. Therefore, when the duty ratio δ is controlled to 100%, the input voltage Vin> the output voltage Vout, and the efficiency of the DC-DC converter. Is low.

  Therefore, as a method for reducing a voltage drop due to circuit elements and obtaining a desired output voltage Vout using a lower input voltage Vin, an input terminal and an output terminal are arranged in parallel with a step-down DC-DC converter. A configuration including a through switch (current control element) to be connected is known. With this configuration, a desired output voltage Vout can be secured with a lower input voltage Vin by turning on the through switch when the input voltage Vin becomes low. Patent Document 1 discloses a conventional step-down DC-DC converter that includes a circuit that detects that the duty ratio δ of the on-time of the switching element has reached 100% and turns on the through switch.

  A conventional step-down DC-DC converter will be described with reference to FIG. As shown in FIG. 7, the conventional DC-DC converter has a switching element 1 and a rectifier 2 connected in series between an input terminal IN and a ground potential, and one end connected to a connection point between the switching element 1 and the rectifier 2. The other end of the inductor 3 is connected to the output terminal OUT, the capacitor 4 is connected between the other end of the inductor 3 and the ground potential, and the input voltage Vin and the output voltage Vout are input to the switching element 1 and the rectifier. A voltage step-down unit 6 having a control circuit 5 for controlling 2, a through switch 7 connected between the input terminal IN and the output terminal OUT so as to be in parallel with the voltage step-down unit 6, and a control signal Vs from the control terminal CTL And an inverter 50 that inverts and outputs to the gate of the through switch 7.

  The switching element 1 is a P-channel FET, and is switched on / off by a signal from the control circuit 5. The rectifier 2 is a synchronous rectifier made of an N channel FET. The switching element 1 and the rectifier 2 supply a switching current to the inductor 3 by performing a switching operation alternately. The inductor 3 and the capacitor 4 are used to smooth the switching voltage corresponding to the switching current and supply a stable output voltage Vout.

  The control circuit 5 detects the input voltage Vin and the output voltage Vout, respectively, determines the on-duty duty ratio δ of the switching element 1 so as to stabilize the output voltage Vout by the above equations (1) and (2), and performs switching. Switching control of the element 1 and the rectifier 2 is performed alternately.

  The inverter 50 inverts the control signal Vs input from the control terminal CTL and outputs it as the drive signal Vgt. The through switch 7 is a P-channel FET, and is turned off when a high level drive signal Vgt is input from the inverter 50 to the gate, and opens between the input terminal IN and the output terminal OUT. Further, it is turned on when a low-level drive signal Vgt is input, and the input terminal IN and the output terminal OUT are short-circuited.

  In FIG. 7, an external control device (not shown) detects that the input voltage Vin has decreased and the on-duty duty ratio δ of the switching element 1 has reached 100%, and when the duty ratio δ is 100%, the high level. The control signal is input from the control terminal CTL. At this time, the drive signal Vgt output from the inverter 50 is at a low level, and the through switch 7 is turned on. The input terminal IN and the output terminal OUT are short-circuited.

When the on-resistance of the switching element 1 is R ₁ , the parasitic resistance of the inductor 3 is R ₃ , and the on-resistance of the through switch 7 is R ₇ , the input terminal IN and the output terminal OUT when the through switch 7 is turned on The combined resistance R can be expressed by the following formula (3). The combined resistance R is smaller than the combined resistance (R ₁ + R ₃ ) when the through switch 7 is not provided.

R = {(R ₁ + R ₃ ) · R ₇ } / (R ₁ + R ₃ + R ₇ ) (3)

  As described above, the step-down DC-DC converter of the conventional example is provided with the through switch 7 connected in parallel with the step-down DC-DC converter, so that input due to the parasitic resistance of the inductor 3 or the on-resistance of the switching element 1 is performed. The voltage drop of the voltage Vin is reduced, and a desired output voltage Vout is obtained even at a lower input voltage Vin.

JP 2001-298945

  However, the step-down DC-DC converter of the conventional example shown in FIG. 7 has a problem that an undershoot occurs in the output voltage Vout when the through switch 7 is turned off. FIG. 8 shows operation waveforms of the conventional step-down DC-DC converter.

  For example, when the battery that is the input power supply voltage of the DC-DC converter is charged, the input voltage Vin increases, and the duty ratio δ of the on-time of the switching element 1 changes from 100% to less than 100%. In this case, the control signal Vs is switched from High to Low, the drive signal Vgt is switched from Low to High, and the through switch 7 is switched from ON to OFF. Since the input terminal IN and the output terminal OUT are opened, the current flowing through the through switch 7 (referred to as Iq) is almost zero.

  In the conventional step-down DC-DC converter, even if the duty ratio δ is 100%, the current Iq flowing through the through switch 7 is larger than the current flowing through the inductor 3 (referred to as Id). . Immediately before the through switch 7 is turned off, the input voltage Vin has already become sufficiently high, so the control circuit 5 may reduce the duty ratio δ of the ON time of the switching element 1. The switching control of the control circuit 5, that is, the increase in the current Id flowing through the inductor 3 cannot catch up with the decrease in the current Iq due to the through switch 7 being turned off, and the current output from the output terminal OUT is temporarily To decrease.

  This decrease in current appears as an undershoot of the output voltage Vout shown in FIG. The undershoot of the output voltage Vout causes a malfunction of various load circuits connected to the output terminal OUT.

  The present invention has been made to solve the above-described problem, and occurs in a step-down DC-DC converter including a current control element that connects between an input terminal IN and an output terminal OUT, when the current control element is turned off. The purpose is to reduce undershoot.

In order to solve the above problems, the present invention has the following configuration.
The DC-DC converter according to claim 1 is a series circuit of a first switching element and a rectifier connected between an input terminal and a ground potential, and a connection point and an output of the first switching element and the rectifier. A voltage step-down unit having an inductor connected between the terminal and a smoothing means connected between a connection point between the inductor and the output terminal and a ground potential; and the first switching element, In the DC-DC converter that steps down the input voltage input from the input terminal to an output voltage lower than the input voltage and outputs the output voltage from the output terminal by alternately performing switching control with the rectifier, the input terminal And a current control unit connected in parallel with the voltage step-down unit between the output terminals, and the current control unit according to a control signal input from the control terminal. Controls passing state and a blocking state, when the current control unit to the disconnected state, a driving unit, a current flowing through the current control unit controls so as to reduce over a predetermined decreasing time.
The decrease in current flowing through the current controller may be continuous or stepwise.

  According to the present invention, in a step-down DC-DC converter having a current control element that connects between an input terminal and an output terminal, the undershoot of the output voltage that occurs when the current control unit is turned off is reduced. can do.

The DC-DC converter according to claim 2, wherein in the DC-DC converter according to claim 1, the predetermined reduction time is the voltage step-down unit when the driving unit sets the current control unit in a cut-off state. Is set longer than the time until the current level of the current flowing through the voltage step-down unit increases from a current level to a predetermined output current level when the current control unit is in a conductive state.
Generally, when the current control unit is in a conductive state, the current flowing through the voltage step-down unit is smaller than the current flowing through the current control unit. Therefore, when the current control unit is switched from the conduction state to the cutoff state, the switching control of the first switching element and the rectifier is performed, the current flowing through the inductor is increased, and the current flowing through the voltage step-down unit is a predetermined value. It takes time to increase to the output current level.

  According to the present invention, the predetermined decrease time during which the current flowing through the current control unit decreases is set longer than the time until the current flowing through the voltage step-down unit increases to the predetermined output current level. Undershoot can be more reliably reduced.

In the DC-DC converter according to claim 3, in the DC-DC converter according to claim 1 or 2, the current control unit has an impedance that changes according to a drive signal from the drive unit. The current control unit is configured to change the level of the drive signal over a predetermined time to change the current flowing through the current control unit for a predetermined decrease time. Configured to decrease over time.
The level of the drive signal may change continuously or stepwise.

  According to the present invention, it is possible to realize a DC-DC converter that reduces undershoot of output voltage at a low cost by a single current control element.

5. The DC-DC converter according to claim 4, wherein the drive unit is controlled by the control signal and connected between a gate of the current control element and a ground potential. A second switching element, a resistor connected between the input terminal and the gate of the current control element, and a connection point between the resistor and the gate of the current control element and a ground potential. A capacitor.
The predetermined decrease time during which the current flowing through the current control unit decreases is determined by the time constant determined by the resistance value of the resistor and the capacitance of the capacitor, and the threshold voltage of the current control element.

  According to the present invention, it is possible to realize a DC-DC converter that reduces the undershoot of the output voltage at a low cost with a simple configuration including a single current control element, a second switching element, a resistor, and a capacitor. .

In the DC-DC converter according to claim 5, in the DC-DC converter according to claim 1 or 2, the current control unit includes a plurality of current control elements, and the drive unit includes the current. When the control unit is put into a cut-off state, the plurality of current control elements are sequentially turned off.
“Sequentially off” refers to an operation in which one current control element is switched off (cut-off state) and then the next current control element is switched off while the current control element remains off. Indicates that all current control elements are repeated until they are turned off.

  According to the present invention, by sequentially turning off a plurality of current control elements, the current flowing through the current control unit can be gradually reduced as compared with the case of turning off a single current control element, and output can be performed more reliably. Voltage undershoot can be reduced. By increasing the number of current control elements, it is possible to more gently reduce the current flowing through the current control unit.

  In the DC-DC converter according to claim 6, in the DC-DC converter according to claim 5, the driving unit includes one or more delay circuits that output an input signal after a predetermined delay time, In the case where the current control unit is turned off, the plurality of current control elements are sequentially turned off every predetermined delay time of the delay circuit.

  According to the present invention, it is possible to realize a DC-DC converter that can more reliably reduce the undershoot of the output voltage by sequentially turning off the plurality of current control elements using one or more delay circuits.

In the DC-DC converter according to claim 7, in the DC-DC converter according to claim 5, each of the plurality of current control elements has an impedance that changes in accordance with a drive signal from the drive unit, The driving unit includes: a second switching element connected between a gate of any one of the plurality of current control elements and a ground potential; the input terminal; and any one of the current control elements. And a capacitor connected between a connection point between the resistor and the gate of any one of the current control elements and a ground potential.
The predetermined decrease time is determined by the time constant due to the resistance and capacitor of each drive block and the threshold voltage of each current control element.

  According to the present invention, a plurality of current control elements and a plurality of drive blocks each including a second switching element, a resistor, and a capacitor for controlling any one of the plurality of current control elements are provided. With the configuration, it is possible to realize a DC-DC converter that more reliably reduces undershoot of the output voltage.

  Advantageous Effects of Invention According to the present invention, in a switching step-down DC-DC converter including a current control element that connects between an input terminal and an output terminal, it is possible to reduce an undershoot that occurs when a through switch is turned off. Play.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that specifically show the best mode for carrying out the present invention will be described below with reference to the drawings.

Embodiment 1
Hereinafter, the DC-DC converter according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram illustrating a circuit configuration of a DC-DC converter according to the present embodiment.

  1, the DC-DC converter of the present embodiment includes a switching device 1, a rectifier 2, an inductor 3, a capacitor 4 (smoothing means), a voltage step-down unit 6 having a control circuit 5, and a through switch (current control). Element) 7 and a drive unit 8.

The switching element 1 is a P-channel FET, for example, and the rectifier 2 is a synchronous rectifier made of an N-channel FET, for example. The switching element 1 and the rectifier 2 are connected in series between the input terminal IN and the ground potential. The switching element 1 and the rectifier 2 are connected to the control circuit 5 at their gates, and are switched on (conductive state) / off (cut-off state) according to a signal from the control circuit 5.
The switching element 1 and the rectifier 2 supply a switching current to the inductor 3 by performing a switching operation alternately under the control of the control circuit 5.

The inductor 3 has one end connected to a connection point between the switching element 1 and the rectifier 2 and the other end connected to the output terminal OUT. One end of the capacitor 4 is connected to the connection point between the inductor 3 and the output terminal OUT, and the other end is connected to the ground potential.
The inductor 3 and the capacitor 4 smooth the switching voltage corresponding to the switching current. A stable output voltage Vout is supplied to a load circuit (not shown) connected to the output terminal OUT.

  The control circuit 5 is connected to the input terminal IN, the output terminal OUT, the gate of the switching element 1, and the gate of the rectifier 2. The control circuit 5 detects the input voltage Vin and the output voltage Vout, respectively, determines the duty ratio δ of the switching element 1 so as to stabilize the output voltage Vout by the above formulas (1) and (2), and the switching element 1 And rectifier 2 are alternately switched.

  The through switch 7 is, for example, a P-channel FET, and has a source connected to the input terminal IN and a drain connected to the output terminal OUT so as to be in parallel with the voltage step-down unit 6. The through switch 7 is turned off (shut off) when a high level drive signal Vgt is input to the gate, and opens the input terminal IN and the output terminal OUT. Further, when a low-level drive signal Vgt is input, it is turned on (conductive state), and the input terminal IN and the output terminal OUT are short-circuited. The through switch 7 has a predetermined impedance with respect to the drive signal Vgt.

The drive unit 8 includes a switching element 11 made of an N-channel FET, a resistor 12, and a capacitor 13, for example.
The switching element 11 has a source connected to the ground potential, a drain connected to the gate of the through switch 7, and a gate connected to the control terminal CTL. The switching element 11 is turned on (conductive state) when the control signal Vs from the control terminal CTL is High, and is turned off (cut off state) when the control signal Vs is Low.
The resistor 12 and the capacitor 13 are connected in series between the input terminal IN and the ground potential. The connection point between the resistor 12 and the capacitor 13 is connected to the drain of the switching element 11.

  An external control device (not shown) is connected to the control terminal CTL. When the input voltage Vin decreases and the on-duty duty ratio δ of the switching element 1 becomes 100%, the external control device (not shown) generates the high-level control signal Vs and the duty ratio δ becomes less than 100%. In this case, a low level control signal Vs is output to the control terminal CTL.

  The drive unit 8 receives a control signal Vs from an external control device (not shown) via the control terminal CTL. When the control signal Vs changes from Low to High, the drive unit 8 outputs a signal Vgt that changes discretely from High to Low. When the control signal Vs changes from High to Low, the drive unit 8 outputs a signal Vgt that gradually changes from Low to High due to the action of the time constant by the resistor 12 and the capacitor 13. ON / OFF of the through switch 7 is controlled by a control signal Vs input from the drive unit 8.

  Next, the operation of the DC-DC converter of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing operation waveforms of the DC-DC converter in the present embodiment.

First, a case where the through switch 7 is turned on will be described.
At time T1 in FIG. 2, when the input voltage Vin decreases and the on-duty duty ratio δ of the switching element 1 becomes 100%, the external device outputs a high level control signal Vs to the control terminal CTL. The switching element 11 is turned on. Since the gate of the through switch 7 is short-circuited to the ground potential, the drive signal Vgt becomes Low. The capacitor 13 is discharged.

Since the gate voltage of the through switch 7 becomes the ground potential and the voltage between the source and the gate becomes equal to or higher than the threshold voltage of the through switch 7, the through switch 7 is turned on, and the input terminal IN and the output terminal OUT are short-circuited. At this time, the current flowing between the source and drain of the through switch 7 is Iq. When the on-resistance of the switching element 1 is R ₁ , the parasitic resistance of the inductor 3 is R ₃ , and the on-resistance of the through switch 7 is R ₇ , the combined resistance R between the input terminal IN and the output terminal OUT is expressed by the above equation (3). The combined resistance R at this time is smaller than the combined resistance (R ₁ + R ₃ ) when the through switch 7 is not provided. For this reason, the DC-DC converter of the present embodiment reduces the voltage drop due to the on-resistance of the switching element 1 and the parasitic resistance of the inductor 3 as in the conventional DC-DC converter, and even with a lower input voltage Vin. A desired output voltage Vout can be obtained.

Next, a case where the through switch 7 is turned off will be described.
At time T2 in FIG. 2, when the input voltage Vin rises due to the battery being charged or the like and the duty ratio δ of the on-time of the switching element 1 becomes less than 100%, the external device (not shown) has a low level at the control terminal CTL. The control signal Vs is input. The switching element 11 is turned off, and the capacitor 13 is charged by the input voltage Vin through the resistor 12. At this time, since the voltage between the source and gate of the through switch 7 is equal to or higher than the threshold voltage of the through switch 7, the through switch 7 is not immediately turned off.

  As the charging of the capacitor 13 progresses, the drive signal Vgt rises, and when the charged charge approaches the capacity of the capacitor 13, the rising speed becomes slow. Assuming that the capacitance of the capacitor 13 is Cr and the elapsed time from the start of charging is t, the voltage Vg applied between the source and gate of the through switch 7 is gradually increased as represented by the following equation (4). To drop.

Vg = Vin × e ^{−t / Cr} (4)

  When the voltage Vg falls below the threshold voltage of the through switch 7 at time T3 in FIG. 2, the current Iq starts to decrease as the voltage Vg decreases and eventually becomes zero (the through switch 7 is turned off). By setting the decrease time of the current Iq to a time in which the increase of the current Id from the inductor 3 is in time for the decrease of the current Iq due to the through switch 7 being turned off, the output Vout generated when the through switch is turned off. Undershoot can be reduced. The decrease time of the current Iq can be arbitrarily adjusted by changing the time constant determined by the resistance value of the resistor 12 and the capacitance of the capacitor 13.

  As described above, according to the DC-DC converter of the present embodiment, in the step-down DC-DC converter including the through switch that connects the input terminal IN and the output terminal OUT, the drive unit having the above-described configuration is provided. By providing, it is possible to reduce undershoot that occurs when the through switch is off.

<< Embodiment 2 >>
FIG. 3 is a diagram illustrating a circuit configuration of the DC-DC converter according to the second embodiment of the present invention. 3 is different from the first embodiment in that a through switch group (current control unit) 37 is provided instead of the through switch 7 and a drive unit 38 is provided instead of the drive unit 8. The other points are the same as those in the first embodiment, and detailed description of elements having the same reference numerals is omitted.

  The through switch group 37 includes, for example, through switches (current control elements) 20, 23, 26, and 29 each made of a P-channel FET. Each through switch has a source connected to the input terminal IN and a drain connected to the output terminal OUT so as to be in parallel with the voltage step-down unit 6. The gate of each through switch is connected to the drive unit 38. Each through switch is turned off (blocked state) when a high level signal is inputted to the gate, and turned on (conducted state) when a low level signal is inputted.

  The drive unit 38 includes delay circuits 21, 24, 27, AND gates 22, 25, 28, and an inverter 30. The drive unit 38 receives the control signal Vs from the control terminal CTL and outputs drive signals Vgt1, Vgt2, Vgt3, and Vgt4 for controlling on / off of each through switch.

  The inverter 30 has an input terminal connected to the control terminal CTL and an output terminal connected to the gate of the through switch 20. The inverter 30 receives the control signal Vs from the control terminal CTL and outputs its inverted signal. The output of the inverter 30 becomes the drive signal Vgt1 for the through switch 20, and is input to the delay circuit 21 and the AND gates 22, 25, and 28.

  The delay circuit 21 has an input terminal connected to the output terminal of the inverter 30 and an output terminal connected to one input terminal of the AND gate 22. The delay circuit 21 receives the output signal of the inverter 30 and outputs it to the AND gate 22 after a predetermined delay time DT. The AND gate 22 has one input terminal connected to the output terminal of the delay circuit 21, the other input terminal connected to the output terminal of the inverter 30, and the output terminal connected to the gate of the through switch 23. The AND gate 22 inputs the output signal of the inverter 30 and the output signal of the delay circuit 21 and outputs the logical sum of the two as the drive signal Vgt2 for the through switch 23.

  The delay circuit 24 has an input terminal connected to the output terminal of the AND gate 22 and an output terminal connected to one input terminal of the AND gate 25. The delay circuit 24 receives the output signal of the AND gate 22 and outputs it to the AND gate 25 after a predetermined delay time DT. The AND gate 25 has one input terminal connected to the output terminal of the delay circuit 24, the other input terminal connected to the output terminal of the inverter 30, and the output terminal connected to the gate of the through switch 26. The AND gate 25 inputs the output signal of the inverter 30 and the output signal of the delay circuit 24, and outputs the logical sum of both as the drive signal Vgt3 for the through switch 26.

  The delay circuit 27 has an input terminal connected to the output terminal of the AND gate 25 and an output terminal connected to one input terminal of the AND gate 28. The delay circuit 27 receives the output signal of the AND gate 25 and outputs it to the AND gate 28 after a predetermined delay time DT. The AND gate 28 has one input terminal connected to the output terminal of the delay circuit 27, the other input terminal connected to the output terminal of the inverter 30, and the output terminal connected to the gate of the through switch 29. The AND gate 28 inputs the output signal of the inverter 30 and the output signal of the delay circuit 27 and outputs the logical sum of both as the drive signal Vgt4 for the through switch 29.

  Next, the operation of the DC-DC converter according to the present embodiment will be described with reference to FIG. FIG. 4 is a diagram showing operation waveforms of the DC-DC converter in the present embodiment.

First, a case where the through switch group 37 is in a conductive state and the through switches 20, 23, 26, and 29 are turned on will be described.
At time T1 in FIG. 4, when the input voltage Vin decreases and the on-duty duty ratio δ of the switching element 1 reaches 100%, the external device (not shown) outputs a high-level control signal Vs to the control terminal CTL. The inverter 30 inverts the control signal Vs and outputs a low level drive signal. The through switch 20 is turned on. Further, since a low level signal is input to the other input terminals of the AND gates 22, 25, 28, the outputs of the AND gates 22, 25, 28 are Low. Therefore, since the low level drive signals Vgt1, Vgt2, Vgt3, and Vgt4 are applied to the gates of the through switches 20, 23, 26, and 29, the through switches are turned on almost simultaneously. At this time, the input terminal IN and the output terminal OUT are short-circuited. An output voltage Vout that is substantially equal to the input voltage Vin is output from the output terminal OUT. The current Iq flowing through the through switch group 37 rises to a predetermined value.

Next, a case where the through switch group 37 is cut off and the through switches 20, 23, 26, and 29 are turned off will be described.
At time T2 in FIG. 4, when the input voltage Vin rises due to charging of the battery or the like and the duty ratio δ of the on-time of the switching element 1 becomes less than 100%, an external device (not shown) has a low level at the control terminal CTL. The control signal Vs is input. The inverter 30 inverts the control signal Vs and outputs a high level drive signal Vgt1. The through switch 20 is turned off, and the current Iq1 flowing through the through switch 20 is almost zero. However, the outputs Vgt2, Vgt3, and Vgt4 of the AND gates 22, 25, and 28 do not immediately become High because the predetermined delay time DT by the delay circuits 21, 24, and 27 is set.

The output (drive signal Vgt2) of the AND gate 22 becomes High at time T3 after a predetermined delay time DT by the delay circuit 21 after the output of the inverter 30 becomes High. The through switch 23 is turned off, and the current Iq2 flowing through the through switch 23 is almost zero.
The output of the AND gate 25 (drive signal Vgt3) becomes High at a time T4 after a predetermined delay time DT by the delay circuit 24 after the output of the AND gate 22 becomes High. The through switch 26 is turned off, and the current Iq3 flowing through the through switch 26 is almost zero.
The output of the AND gate 28 (drive signal Vgt4) becomes High at a time T5 after a predetermined delay time DT by the delay circuit 27 after the output of the AND gate 25 becomes High. The through switch 29 is turned off, and the current Iq4 flowing through the through switch 29 becomes almost zero.

  The current Iq flowing through the through switch group 37 is the sum of the current Iq1 flowing through the through switch 20, the current Iq2 flowing through the through switch 23, the current Iq3 flowing through the through switch 26, and the current Iq4 flowing through the through switch 29. As the switches 20, 23, 26, and 29 are sequentially turned off, the current Iq decreases stepwise. By setting the decrease time of the current Iq to a time when the current supply from the inductor 3 is in time, undershoot of the output Vout can be reduced. The decrease time of the current Iq can be arbitrarily and easily adjusted by changing the delay time DT in each delay circuit.

  As described above, according to the DC-DC converter in the present embodiment, in the step-down DC-DC converter including the through switch that connects between the input terminal IN and the output terminal OUT, the through switch group is brought into a conductive state. In this case, the through switches are turned on at the same time. However, when the through switch group is put into a cutoff state, the through switches are sequentially turned off. Thereby, the current Iq flowing through the through switch group 37 can be gradually reduced.

  In the present embodiment, the through switch group 37 is configured by four through switches. However, the present invention is not limited to this configuration, and any number of two or more through switches can be used in the present embodiment. This embodiment is effective and the present embodiment is not limited to this number. In addition, by changing the number of through switches and the delay time of each delay circuit, the reduction time of the current Iq flowing through the through switch and the linearity of the current change are adjusted, and the reduction of the current Iq is moderately and substantially linear. Can be changed.

<< Embodiment 3 >>
FIG. 5 is a diagram showing a circuit configuration of the DC-DC converter according to Embodiment 3 of the present invention. 5 differs from the second embodiment in that a through switch group (current control unit) 57 is provided in place of the through switch group 37 and a drive unit 58 is provided in place of the drive unit 38. The other points are the same as those of the second embodiment, and detailed description of elements having the same reference numerals is omitted.

  The through switch group 57 includes, for example, through switches (current control elements) 40, 43, and 46 each made of a P-channel FET. Each through switch has a source connected to the input terminal IN and a drain connected to the output terminal OUT so as to be in parallel with the voltage step-down unit 6. The gate of each through switch is connected to the drive unit 58. Each through switch is turned off (blocked state) when a high level signal is inputted to the gate, and turned on (conducted state) when a low level signal is inputted. Each through switch has a predetermined impedance with respect to the drive signal from the drive unit 58.

  The drive unit 58 includes switching elements 61, 64, 67, resistors 62, 65, 68, capacitors 63, 66, 69, and inverters 70, 71, which are all N-channel FETs. The drive unit 58 receives the control signal Vs from the control terminal CTL and outputs drive signals Vgt1, Vgt2, and Vgt3 for controlling on / off of each through switch.

  The switching element 61 has a source connected to the ground potential, a drain connected to the gate of the through switch 40, and a gate connected to the control terminal CTL. The switching element 64 has a source connected to the ground potential, a drain connected to the gate of the through switch 43, and a gate connected to the gate of the through switch 40. The switching element 67 has a source connected to the ground potential, a drain connected to the gate of the through switch 46, and a gate connected to the gate of the through switch 43. The switching elements 61, 64, and 67 are turned on (conducting state) when the signal input to the gate is high, and turned off (cut off state) when the signal is low.

  The resistor 62 and the capacitor 63, the resistor 65 and the capacitor 66, the resistor 68 and the capacitor 69 are respectively connected in series between the input terminal IN and the ground potential. The connection point between the resistor 62 and the capacitor 63, the connection point between the resistor 65 and the capacitor 66, and the connection point between the resistor 68 and the capacitor 69 are the drain of the switching element 61, the drain of the switching element 64, and the switching element 67, respectively. Connected to the drain.

  The inverter 70 has an input terminal connected to the drain of the switching element 61 and an output terminal connected to the gate of the switching element 64. The inverter 71 has an input terminal connected to the drain of the switching element 64 and an output terminal connected to the gate of the switching element 67. The inverters 70 and 71 invert the input signal and output it.

  A first driving block including a switching element 61, a resistor 62, and a capacitor 63; a second driving block including a switching element 64, a resistor 65, and a capacitor 66; and a switching element 67, a resistor 68, and The third drive block including the capacitor 69 is configured similarly to the drive unit 8 in the first embodiment and operates in the same manner. Detailed description of each drive block is omitted.

  Next, the operation of the DC-DC converter of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing operation waveforms of the DC-DC converter in the present embodiment.

First, the case where the through switch group 57 is turned on and the through switches 40, 43, and 46 are turned on will be described.
At time T1 in FIG. 6, when the input voltage Vin decreases and the duty ratio δ of the on-time of the switching element 1 reaches 100%, the external device (not shown) outputs a high level control signal Vs to the control terminal CTL. The switching element 61 is turned on. Since the gate of the through switch 40 is short-circuited to the ground potential, the drive signal Vgt1 becomes Low. The capacitor 63 is discharged.

Further, the switching element 64 that inputs the inverted signal of the drive signal Vgt1 to the gate via the inverter 70 is turned on. Since the gate of the through switch 43 is short-circuited to the ground potential, the drive signal Vgt2 becomes Low. The capacitor 66 is discharged.
The switching element 67 that inputs the inverted signal of the drive signal Vgt2 to the gate via the inverter 71 is turned on. Since the gate of the through switch 46 is short-circuited to the ground potential, the drive signal Vgt3 becomes Low. The capacitor 69 is discharged.

  Accordingly, since the low level drive signals Vgt1, Vgt2, and Vgt3 are applied to the gates of the through switches 40, 43, and 46, respectively, the gate voltages of the through switches 40, 43, and 46 become the ground potential, and the source − The voltage between the gates is equal to or higher than the threshold voltage of each through switch 40, 43, 46. Each through switch 40, 43, 46 is turned on almost simultaneously. At this time, the input terminal IN and the output terminal OUT are short-circuited. An input voltage Vin is output from the output terminal OUT. The current Iq flowing through the through switch group 57 rises to a predetermined value.

Next, a case where the through switch group 57 is cut off and the through switches 40, 43, and 46 are turned off will be described.
At time T2 in FIG. 6, when the input voltage Vin rises due to charging of the battery or the like and the duty ratio δ of the ON time of the switching element 1 becomes less than 100%, the external device (not shown) has a low level at the control terminal CTL. The control signal Vs is input. The switching element 61 is turned off, and the capacitor 63 is charged by the input voltage Vin through the resistor 62. At this time, since the voltage between the source and gate of the through switch 40 is equal to or higher than the threshold voltage of the through switch 40, the through switch 40 does not turn off immediately.

  As the charging of the capacitor 63 proceeds, the drive signal Vgt1 increases, and as the capacity of the capacitor 63 approaches, the increasing speed becomes slow. The voltage Vg1 applied between the source and gate of the through switch 40 gradually decreases. When the voltage Vg1 falls below the threshold voltage of the through switch 40 at time T3, the current Iq1 flowing through the through switch 40 starts to decrease and eventually becomes zero (the through switch 40 is turned off).

  At substantially the same time as the through switch 40 is turned off, the drive signal Vgt1 exceeds the threshold voltage of the inverter 70 (the high-level drive signal Vgt1 is input to the inverter 70). An inverted signal (Low level) of the drive signal Vgt1 is input to the gate of the switching element 64 via the inverter 70. The switching element 64 is turned off, and the capacitor 66 is charged by the input voltage Vin through the resistor 65. At this time, since the voltage between the source and gate of the through switch 43 is equal to or higher than the threshold voltage of the through switch 43, the through switch 43 is not immediately turned off.

  As the charging of the capacitor 66 proceeds, the drive signal Vgt2 increases. As the capacity of the capacitor 66 is approached, the rate of increase increases. The voltage Vg2 applied between the source and gate of the through switch 43 gradually decreases. When the voltage Vg2 falls below the threshold voltage of the through switch 43 at time T4, the current Iq2 flowing through the through switch 43 starts to decrease and eventually becomes zero (the through switch 43 is turned off).

  At substantially the same time as the through switch 43 is turned off, the drive signal Vgt2 exceeds the threshold voltage of the inverter 71 (the high-level drive signal Vgt2 is input to the inverter 71). An inverted signal (Low level) of the drive signal Vgt2 is input to the gate of the switching element 67 through the inverter 71. The switching element 67 is turned off, and the capacitor 69 is charged by the input voltage Vin through the resistor 68. At this time, since the voltage between the source and gate of the through switch 46 is equal to or higher than the threshold voltage of the through switch 46, the through switch 46 is not immediately turned off.

  As the charging of the capacitor 69 progresses, the drive signal Vgt3 increases. As the capacity of the capacitor 69 is approached, the increasing speed becomes slower. The voltage Vg3 applied between the source and gate of the through switch 46 gradually decreases. When the voltage Vg3 falls below the threshold voltage of the through switch 46 at time T5, the current Iq3 flowing through the through switch 46 also starts to decrease and eventually becomes zero (the through switch 46 is turned off).

  Since the current Iq flowing through the through switch group 57 is the sum of the current Iq1 flowing through the through switch 40, the current Iq2 flowing through the through switch 43, and the current Iq3 flowing through the through switch 46, each of the through switches is sequentially turned off. Thus, the current Iq decreases gradually. By setting the decrease time of the current Iq so that the increase in the current Id from the inductor 3 is in time for the decrease in the current Iq due to the through switch 7 being turned off, the output Vout generated when the through switch is turned off is set. Undershoot can be reduced. The decrease time of the current Iq can be arbitrarily adjusted by changing the time constant determined by the resistor 62 and the capacitor 63, the resistor 65 and the capacitor 66, the resistor 68 and the capacitor 69.

  As described above, according to the DC-DC converter in the present embodiment, in the step-down DC-DC converter including the through switch that connects between the input terminal IN and the output terminal OUT, the through switch group is brought into a conductive state. In this case, the through switches are turned on at the same time. However, when the through switch group is put into a cutoff state, the through switches are sequentially turned off. Thereby, the current Iq flowing between the input terminal IN and the output terminal OUT can be more gently reduced.

  In the present embodiment, the through switch group 57 is configured by three through switches. However, the present invention is not limited to this configuration, and any number of through switches of two or more may be used. This embodiment is effective and the present embodiment is not limited to this number. In addition, by changing the number of through switches and the time constant of each resistor and capacitor, the reduction time of the current Iq flowing through the through switch and the linearity of the current change are adjusted, and the reduction of the current Iq is gradually and substantially reduced. It can be changed linearly. In the present embodiment, the time constant due to each resistor and capacitor for realizing the same current Iq reduction time is smaller than that of the first embodiment, and the number of through switches may be smaller than that of the second embodiment. Therefore, the undershoot of the output voltage Vout can be accurately reduced at a low cost.

  The present invention can be used for a step-down power supply circuit including a through switch that connects between an input terminal and an output terminal.

The figure which shows the circuit structure of the DC-DC converter in Embodiment 1 of this invention. The figure which shows the operation | movement waveform of the DC-DC converter in Embodiment 1 of this invention. The figure which shows the circuit structure of the DC-DC converter in Embodiment 2 of this invention. The figure which shows the operation | movement waveform of the DC-DC converter in Embodiment 2 of this invention. The figure which shows the circuit structure of the DC-DC converter in Embodiment 3 of this invention. The figure which shows the circuit structure of the DC-DC converter in Embodiment 3 of this invention. The figure which shows the circuit structure of the DC-DC converter in a prior art example. The figure which shows the operation | movement waveform of the DC-DC converter in a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 61, 64, 67 Switching element 2 Rectifier 3 Inductor 4, 13, 63, 66, 69 Capacitor 5 Control circuit 6 Voltage step-down part 7, 20, 23, 26, 29, 40, 43, 46 Through switch (current control) element)
8, 38, 58 Drive unit 12, 62, 65, 68 Resistor 21, 24, 27 Delay circuit 22, 25, 28 AND gate 30, 50 Inverter 37, 57 Through switch group (current control unit)

Claims (7)

A series circuit of a first switching element and a rectifier connected between an input terminal and a ground potential; an inductor connected between a connection point of the first switching element and the rectifier and an output terminal; Smoothing means connected between the connection point of the inductor and the output terminal and the ground potential, and a voltage step-down unit having
The DC− that outputs the voltage from the output terminal by stepping down the input voltage input from the input terminal to an output voltage lower than the input voltage by alternately controlling the switching of the first switching element and the rectifier. In the DC converter,
A current control unit connected in parallel with the voltage step-down unit between the input terminal and the output terminal, and controlling a conduction state and a cutoff state of the current control unit according to a control signal input from the control terminal; A DC-DC converter, comprising: a drive unit that controls the current flowing through the current control unit to decrease over a predetermined decrease time when the current control unit is in a cut-off state. The predetermined decrease time is the current flowing through the voltage step-down unit when the driving unit turns off the current control unit, and the current flowing through the voltage step-down unit when the current control unit is conductive. 2. The DC-DC converter according to claim 1, wherein the DC-DC converter is set longer than a time until the current level increases to a predetermined output current level. The current control unit is one current control element having an impedance that changes according to a drive signal from the drive unit,
The drive unit is configured to reduce the current flowing through the current control unit over a predetermined decrease time by changing the level of the drive signal over a predetermined time when the current control unit is in a cut-off state. The DC-DC converter according to claim 1 or 2, wherein the DC-DC converter is provided. A second switching element controlled by the control signal and connected between a gate of the current control element and a ground potential;
A resistor connected between the input terminal and the gate of the current control element; and a capacitor connected between a connection point of the resistor and the gate of the current control element and a ground potential. The DC-DC converter according to claim 3. The current control unit has a plurality of current control elements,
3. The DC-DC converter according to claim 1, wherein the drive unit is configured to sequentially turn off the plurality of current control elements when the current control unit is in a cut-off state. 4. The driving unit includes one or more delay circuits that output an input signal after a predetermined delay time;
6. The DC-DC converter according to claim 5, wherein when the current control unit is in a cut-off state, the plurality of current control elements are sequentially turned off for each predetermined delay time of the delay circuit. . The plurality of current control elements each have an impedance that changes in accordance with a drive signal from the drive unit,
The driving unit includes a second switching element connected between a gate of any one of the plurality of current control elements and a ground potential;
A resistor connected between the input terminal and the gate of any one of the current control elements; and a connection point between the resistor and the gate of any one of the current control elements and a ground potential. The DC-DC converter according to claim 5, comprising a plurality of drive blocks each having a capacitor.

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