TWI796052B - A dc-dc converter, an electronic device, and a soft-start method for the dc-dc converter - Google Patents

Abstract

A DC-DC converter, an electronic device, and a soft-start method for the DC-DC converter are provided, where a sampled voltage is used to adjust a duty cycle of a pulse width modulation signal, thereby adjusting an on-period of a PMOS power transistor and an on-period of a NMOS power transistor, so that an inductor current is switched between decreasing and increasing. In addition, by setting an appropriate preset voltage and preset duration, the inductor current is increased from a low initial point, and a duration in which the inductor current increase within a period is limited to prevent a large inductor current to an external load which causes damage to the external load.

Description

DCDC converter, electronic equipment and soft start method for DCDC converter

The present application relates to the technical field of current converters, in particular to a DCDC converter, electronic equipment and a soft start method for the DCDC converter.

DCDC refers to DC switching power supply (also known as DC-DC), which can be used for step-up and step-down. Using the energy storage characteristics of capacitors and inductors, high-frequency switching actions are performed through controllable switches such as MOSFETs, and the input The electrical energy is stored in the capacitor or inductor, and when the switch is turned off, the electrical energy is released to the load to provide energy. The power or voltage capability of the DCDC output is related to the duty cycle, and the duty cycle is related to the ratio of the switch conduction time to the entire switch cycle.

In the initial startup stage of the DCDC converter, a transient inrush current may be generated, causing damage to the DCDC converter itself and the load, and even damage in severe cases. Therefore, it is necessary to set a soft-start process to limit the startup When the current intensity is constant, the output voltage rises slowly and smoothly to the set value, avoiding voltage and current overshoot.

In view of this, the present application provides a DCDC converter, electronic equipment and a soft start method for the DCDC converter, so as to solve the problem of current overshoot in the initial start-up stage of the DCDC converter.

A DCDC converter provided by this application includes: The oscillation module is used to output a pulse width modulation signal according to the sampling voltage; the output module includes a PMOS power transistor, an NMOS power transistor and an LC filter circuit, wherein: the source of the PMOS power transistor is used to receive the input voltage, and the gate connected to the output terminal of the oscillation module; the source of the NMOS power transistor is grounded, the gate is connected to the output terminal of the oscillation module, and the drain is connected to the drain of the PMOS power transistor; the LC The first end of the filter circuit is connected to the drain of the PMOS power transistor, the first end is connected to the oscillation module to provide the sampling voltage to the oscillation module, and the second end of the LC filter circuit for outputting the output voltage; the oscillating module is used for adjusting the duty cycle of the pulse width modulation signal according to the change of the sampling voltage, so as to control the sequential turn-on time of the PMOS power transistor and the NMOS power transistor, The method includes: when the NMOS power transistor is turned on, when the sampling voltage is greater than a preset voltage, controlling the PMOS power transistor to be turned on, and limiting the turn-on duration of the PMOS power transistor to be below a preset duration.

Optionally, when the oscillation module controls the duty ratio of the pulse width modulation signal according to the magnitude of the sampling voltage, compare the sampling voltage with a preset voltage, and when the NMOS power transistor is turned on, if the If the sampling voltage is greater than the preset voltage, the PMOS power transistor is controlled to be turned on through the pulse width modulation signal, and the conduction time of the PMOS power transistor is controlled to be less than or equal to the preset time length.

Optionally, the oscillation module includes: a conduction control unit connected to the first end of the LC filter circuit and connected to receiving the pulse width modulation signal, the conduction control unit is used to compare the sampling voltage and the preset voltage, and output a first control signal according to the comparison result and the pulse width modulation signal; the shutdown control unit is connected to to the conduction control unit, configured to output a second control signal according to the first control signal; a pulse width modulation signal unit, connected to the conduction control unit and the shutdown control unit, for outputting a second control signal according to the first control signal and The second control signal forms the pulse width modulation signal; a driving unit, connected to the pulse width modulation signal unit, is used to output a driving signal according to the pulse width modulation signal to drive the PMOS power transistor and the NMOS power transistor.

Optionally, the conduction control unit includes: a comparison unit having two input terminals, one of which is connected to the output terminal of the sampling voltage, and the other input terminal is used to receive the preset voltage and output the The above comparison result; a current mirror load, used to provide a bias current for the comparison unit; an NOR gate circuit, including a first NOR gate and an inverter, the first NOR gate has two input terminals, wherein One input terminal is connected to the output terminal of the comparison unit, the other input terminal is connected to the output terminal of the pulse width modulation signal unit through the inverter, and the output terminal of the first inverting-or gate outputs the first a control signal.

Optionally, the comparison unit includes: a first NMOS transistor and a second NMOS transistor whose gates are connected to each other, the gate and drain of the first NMOS transistor are connected, and the source of the first NMOS transistor is connected to to the place The first end of the LC filter circuit, the source of the second NMOS transistor receives the preset voltage; the current mirror load includes: a first PMOS transistor, the source receives the input voltage, and the drain is connected to the The drain of the first NMOS transistor; the second PMOS transistor, the source of which receives the input voltage, and the drain is connected to the drain of the second NMOS transistor; the gates of the first PMOS transistor and the second PMOS transistor It is also connected to a bias voltage source, and the bias voltage source provides bias voltages for the first PMOS transistor and the second PMOS transistor.

Optionally, the preset voltage is 0V.

Optionally, the shutdown control unit includes: a mirror current source for providing charging current, including a third PMOS transistor and a fourth PMOS transistor whose gates are connected to each other, and the third PMOS transistor and the fourth PMOS transistor The source of the source receives the input voltage; the resistor is connected to the output terminal of the mirror current source to control the magnitude of the charging current; the charging capacitor is connected to the third PMOS transistor through the resistor The drain of the switch unit, connected to the output terminal of the conduction control unit, and connected to the mirror current source and the charging capacitor, for controlling the charging capacitor to accept the mirror image according to the first control signal current source for charging, or to control the charging capacitor discharge electricity.

Optionally, the shutdown control unit further includes: a buffer unit, connected to the charging capacitor, for shaping the terminal voltage of the charging capacitor, and the buffer unit has a flipping threshold, at which the terminal voltage When it is greater than or equal to the inversion threshold, the terminal voltage is inverted and output.

Optionally, the pulse width modulation signal unit includes: an RS latch, including a second NOR gate and a third NOR gate, wherein: an input terminal of the second NOR gate is used as an R input terminal, connected to To the output terminal of the shutdown control unit, the other input terminal is connected to the output terminal of the third NOR gate, and the output terminal of the second NOR gate is used as the Q output terminal; one of the third NOR gate The input end is used as the S input end and is connected to the output end of the conduction control unit, and the other input end is connected to the output end of the second NOR gate.

The present application provides a soft start method for a DCDC converter, the DCDC converter includes an output module, the output module includes an NMOS power transistor, a PMOS power transistor, and an LC filter circuit, and the first end of the LC filter circuit is connected to To the connection point of the NMOS power transistor and the PMOS power transistor, the second end is grounded; the method includes the following steps: obtaining a sampling voltage from the first end of the LC filter circuit; providing a pulse width modulation signal to drive the NMOS power tube and PMOS power tube, and adjust the duty cycle of the pulse width modulation signal according to the change of the sampling voltage, so as to control the conduction time of the PMOS power tube and the NMOS power tube.

Optionally, when adjusting the duty ratio of the pulse width modulation signal according to the change of the sampling voltage to control the conduction time of the PMOS power transistor and the NMOS power transistor, The method includes the following steps: comparing the sampling voltage with a preset voltage, when the NMOS power transistor is turned on, if the sampling voltage is greater than the preset voltage, controlling the PMOS power transistor to turn on through the pulse width modulation signal, and and controlling the conduction duration of the PMOS power transistor to be less than or equal to a preset duration.

Optionally, when adjusting the duty ratio of the pulse width modulation signal according to the change of the sampling voltage, the following steps are included: acquiring a first control signal and a second control signal according to the magnitude of the sampling voltage; A control signal and a second control signal form the pulse width modulated signal.

Optionally, when acquiring the first control signal according to the magnitude of the sampling voltage, the following steps are included: acquiring the pulse width modulation signal; when the sampling voltage is greater than the preset voltage, if the pulse width modulation signal is a high level, then output the first control signal that is set high, and if the pulse width modulation signal is low level, then output the first control signal that is set low; and/or, at the sampling voltage When the voltage is lower than the preset voltage, the comparing unit outputs a high level, and outputs the first control signal which is set low.

Optionally, when acquiring the second control signal according to the change of the sampling voltage, the method includes the following steps: providing a charging capacitor, and providing a charging current to charge the charging capacitor; When the first control signal is set high, cut off the connection between the charging current and the charging capacitor, and control the charging capacitor to discharge; obtain the terminal voltage of the charging capacitor, when the terminal voltage is higher than a When the threshold value is reversed, output the second control signal that is set high, otherwise output the second control signal that is set low.

Optionally, when acquiring the second control signal according to the change of the sampling voltage, the following step is further included: adjusting the set-high duration of the second control signal by changing the charging capacitance, charging current and the flipping threshold.

Optionally, an RS latch is used to process the first control signal and the second control signal to obtain the pulse width modulation signal.

The present application also provides an electronic device, including the DCDC converter.

The DCDC converter, the electronic equipment and the soft start method of the DCDC converter of the present application use the sampling voltage to adjust the duty ratio of the pulse width modulation signal, thereby adjusting the conduction duration of the PMOS power transistor and the NMOS power transistor. Since the PMOS power transistor and the NMOS power transistor can increase or decrease the inductor current, by controlling the duty cycle of the pulse width modulation signal, the inductor current can be reduced to a certain extent Then start to increase, so that the inductor current can increase from a lower initial point, and can limit the increase of the inductor current in one cycle, preventing the output of a large inductor current to the external load, Cause damage to external loads.

101:Oscillation module

102: Output module

103: Drive unit

104: Turn on the control unit

1041: comparison unit

1042: current mirror load

105:Shutdown control unit

106: Pulse Width Modulation Signal Unit

201: RS latch

S401: step

S402: step

S501: step

S502: step

S601: step

S602: step

S603: step

Fig. 1 is a schematic structural diagram of a DCDC converter in the prior art; Fig. 2 is a timing diagram of various signals in a DCDC converter in the prior art; Fig. 3 is a schematic structural diagram of a DCDC converter described in an embodiment; Fig. 4 is A schematic diagram of the structure of the DCDC converter in one embodiment; FIG. 5 is a schematic diagram of the circuit structure of the DCDC converter in one embodiment; FIG. 6 is a schematic diagram of the timing of each signal of the DCDC converter in one embodiment; FIG. 7 It is a schematic flow diagram of the steps of the soft start method described in an embodiment; FIG. 8 is a schematic flow diagram of the steps after step S402 in FIG. 7 is expanded in an embodiment; FIG. 9 is a step after the expansion of step S502 in FIG. 8 in an embodiment Schematic diagram of the process.

Research has found that an error amplifier and a comparison unit can be used to construct a soft-start circuit for a DCDC converter. The DCDC converter is shown in Figure 1, including an error amplifier EA, a comparison unit COMP, a driver, and an output section. The error The amplifier EA compares the rising reference voltage VC with the sampling voltage FB based on the output voltage of the DCDC converter, and outputs an adjusted voltage VEA. The rising reference voltage VC is generated by charging the capacitor C and rises linearly with time.

The comparison unit COMP compares the adjustment voltage VEA with a sawtooth wave signal to generate a square wave signal PWM, as shown in FIG. 2 . Since the reference voltage VC rises linearly with time, the adjusted voltage VEA is obtained after chopping the sawtooth signal SAW The duty cycle of the square wave signal PWM will also increase linearly, causing the output voltage VOUT to increase slowly with the increase of the reference voltage VC, thereby realizing a soft start process.

However, when using the soft-start circuit, when the load is heavy or the output filter capacitor is large, the output voltage VOUT is low, the sampling voltage FB is almost zero, and the difference between the sampling voltage FB and the reference voltage VC will reach the maximum. The regulated voltage VEA output by the error amplifier EA reaches the maximum, and the DCDC converter will work at the maximum duty ratio, and the conduction time Ton of the PMOS power transistor is very large at this time. Since the current peak value of the inductor L in the output module is related to the conduction time Ton of the PMOS power transistor, the current peak value of the inductor is also very high at this time, and the inductor saturation is prone to occur, seriously causing damage to the DCDC converter.

In order to overcome the above problems, the present application proposes a DCDC converter, electronic equipment and a soft start method for the DCDC converter. The DCDC converter and the soft start of the DCDC converter in this application will be further described below with reference to the accompanying drawings.

An embodiment of the present application provides a DCDC converter.

Please refer to FIG. 3 , which is a schematic structural diagram of the DCDC converter in an embodiment.

A DCDC converter provided in this application includes an oscillation module 101 and an output module 102 .

The oscillating module 101 is used to output a pulse width modulation signal, and control the duty cycle of the pulse width modulation signal PWM according to the magnitude of the sampling voltage SW, that is, the high-low level inversion timing of the pulse width modulation signal PWM. The sampling voltage SW is sampled from the output module 102, and when the pulse width modulation signal PWM is at a high level, if the sampling voltage SW is greater than a preset voltage, the pulse width modulation signal PWM is reversed to a low level. level, and the low level of the The duration is less than or equal to the preset duration.

The output module 102 includes a PMOS power transistor, an NMOS power transistor and an LC filter circuit, wherein: the source of the PMOS power transistor is used to receive the input voltage Vin, and the gate is connected to the output terminal of the oscillation module 101; The source of the NMOS power transistor is grounded, the gate is connected to the output terminal of the oscillation module 101 , and the drain is connected to the drain of the PMOS power transistor.

The LC filter circuit includes an inductor L and a capacitor C connected to each other, the first end of the inductor L is connected to the drain of the PMOS power transistor as the first end of the LC filter circuit, and is also connected to the oscillator module 101, to provide the sampling voltage SW to the oscillation module 101. The second end of the inductor L is used as the second end of the LC filter circuit to output an output voltage VOUT, and the second end of the inductor L is connected to the upper plate of the capacitor C, and the capacitor C The lower plate is grounded.

The PMOS power transistor and the NMOS power transistor are alternately turned on according to the change of the high and low levels of the pulse width modulation signal PWM, so that the LC filter circuit is switched between two states, one state is that the PMOS power transistor is turned on, and the NMOS power transistor is turned on. When it is turned off, the LC filter circuit is connected to the input voltage Vin through the PMOS power transistor, and the input voltage Vin charges the capacitor in the LC filter circuit. In this state, the inductance of the inductor L The current is constantly increasing, and the greater the on-time Ton of the PMOS transistor is, the greater the peak value of the inductor current is; in another state, when the NMOS power transistor is turned on and the PMOS power transistor is turned off, the LC filter circuit has a greater effect on the The discharge state of the NMOS tube discharge, in this state, the inductance current of the inductor L decreases continuously, and the longer the on-time Toff of the NMOS tube is, the smaller the minimum value of the inductance current is.

Therefore, by controlling the conduction time of the PMOS power transistor and the NMOS power transistor, the inductor current can be controlled to prevent the peak value of the inductor current from being too large, thereby preventing the DCDC converter from being damaged under the excessive peak value of the inductor current .

In this embodiment, in the discharge state, the electrode plate of the capacitor C in the LC filter circuit discharges to the ground, and the current direction is from the ground to the first end of the LC filter circuit. Since the potential of the ground is 0V, Therefore, the potential of the first end of the LC filter circuit is a negative value, therefore, the sampling voltage SW is inversely proportional to the magnitude of the inductor current, the larger the inductor current is, the smaller the sampling voltage SW is, therefore , only after the inductor current decreases to a certain value, so that the sampling voltage SW increases to the preset voltage, the pulse width modulation signal PWM that is set high is output to start a new round of charging, which ensures that the The inductor current has a lower initial value at the beginning of charging in one cycle of the pulse width modulation signal PWM.

In this embodiment, the duration of the low level of the pulse width modulation signal PWM is also limited, and the duration of the low level corresponds to the charging duration of one cycle of the pulse width modulation signal PWM. The increase of the inductor current during the charging process in the PWM cycle of the signal is positively correlated. Therefore, by limiting the duration of the low level, the increase of the inductor current during the charging process of a pulse width modulation signal PWM cycle can be limited.

In this embodiment, the initial value of the inductor current and the increase of the inductor current during the charging process of a pulse width modulation signal PWM cycle are limited, which can effectively prevent the peak value of the inductor current from being too large, thereby preventing The DCDC converter is destroyed by excessive inductor current peaks.

Please refer to FIG. 4 , which is a schematic structural diagram of the DCDC converter in an embodiment.

In this embodiment, the oscillation module 101 includes a turn-on control unit 104 , a turn-off control unit 105 , a PWM signal unit 106 and a drive unit 103 .

The conduction control unit 104 is connected to the first end of the LC filter circuit to obtain the sampling voltage SW and receive the pulse width modulation signal PWM, and the conduction control unit 104 is used to compare the sampling voltage SW and a preset voltage, and output the first control signal according to the comparison result and the pulse width modulation signal PWM.

The turn-off control unit 105 is connected to the turn-on control unit 104 for outputting a second control signal according to the first control signal.

The pulse width modulation signal unit 106 is connected to the on control unit 104 and the off control unit 105 for forming the pulse width modulation signal PWM according to the first control signal and the second control signal.

The driving unit 103 is connected to the output terminal of the pulse width modulation signal unit 106, and is used for shaping and amplifying the pulse width modulation signal PWM output from the pulse width modulation signal unit 106, so as to drive the output module 102 The PMOS power tube and the NMOS power tube in it.

Please refer to FIG. 5 , which is a schematic diagram of the circuit structure of the DCDC converter in an embodiment.

In this embodiment, the conduction control unit 104 includes a comparison unit 1041 , a current mirror load 1042 and an inverting OR gate circuit.

The comparison unit 1041 includes a first NMOS transistor MN1 and a second NMOS transistor MN2 whose gates are connected to each other, the gate and drain of the first NMOS transistor MN1 are connected, and the source of the first NMOS transistor MN1 serves as The positive input, connected to the LC The first terminal of the filter circuit is used to obtain the sampling voltage SW, and the source of the second NMOS transistor MN2 is used as the negative input terminal to be grounded to obtain a preset voltage of 0V.

In fact, the preset voltage can also be set to other values. The larger the preset voltage, the larger the duty cycle of the high level of the pulse width modulation signal PWM, and the longer the conduction time of the NMOS power transistor is. The larger the , the greater the reduction range of the inductor current of the LC filter circuit in one cycle. Therefore, setting the preset voltage reasonably can prevent excessive accumulation of inductor current.

In this embodiment, the current mirror load 1042 is used to provide a bias current to the comparison unit 1041, including: a first PMOS transistor MP1, the source of which receives the input voltage Vin, and the drain connected to the first The drain of the NMOS transistor MN1; the second PMOS transistor MP2, the source receives the input voltage Vin, and the drain is connected to the drain of the second NMOS transistor MN2; the first PMOS transistor MP1 and the second PMOS transistor MP2 The gate of the gate is also connected to a bias voltage source VB, and the bias voltage source VB provides bias voltages for the first PMOS transistor MP1 and the second PMOS transistor MP2.

In the embodiment shown in FIG. 5, the NOR gate circuit includes a first NOR gate NOR1 and an inverter INV1. The first NOR gate NOR1 has two input terminals, one of which is connected to the The output terminal of the comparison unit 1041, the other input terminal is connected to the output terminal of the pulse width modulation signal unit through the inverter INV1, and the output terminal of the first inverting OR gate NOR1 outputs the first control signal TFC.

When the sampling voltage SW is greater than the preset voltage, the comparison unit 1041 outputs a low level. At this time, the output signal of the NOR circuit is related to the pulse width modulation signal PWM. When the wide modulation signal PWM is at high level, the inverting OR gate Outputting a high level as the first control signal TFC, when the pulse width modulation signal PWM is at a low level, the NOR gate outputs a low level as the first control signal TFC. When the pulse width modulation signal PWM is at low level, the output signal of the NOR circuit is continuously at low level.

The shutdown control unit 105 includes a mirror current source, a charging capacitor C1, a resistor R and a switch unit.

The switch unit includes a third NMOS transistor MN3, the gate of the third NMOS transistor MN3 is connected to the output end of the conduction control unit 104, and is controlled by the first control signal TFC output by the conduction control unit 104. Turn on and turn off the third NMOS transistor MN3. The source and drain of the third NMOS transistor MN3 are respectively connected to the upper and lower plates of the charging capacitor C1, and are used to control the charging capacitor C1 to accept charging from the mirror current source according to the first control signal TFC, Or control the charging capacitor C1 to discharge.

The mirror current source includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4 whose gates are connected to each other, the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are used as output terminals, and the source receives the input voltage Vin.

The resistor R is connected to the output terminal of the mirror current source for controlling the magnitude of the charging current.

The charging capacitor C1 is connected to the drain of the third PMOS transistor MP3 through the resistor R, and the mirror current source provides a charging current to charge the charging capacitor C1. Under the control of the switch unit, the connection line between the mirror current source and the charging capacitor C1 is turned on or off, corresponding to the charging or discharging of the charging capacitor C1 by the charging current.

In this embodiment, the shutdown control unit 105 further includes a buffer unit BUF connected to one end of the charging capacitor C1 for shaping the terminal voltage VC of the charging capacitor C1, and the buffer unit BUF Has a flipping threshold Vth. When the terminal voltage VC is greater than or equal to the inversion threshold Vth, the terminal voltage VC is inverted and output, and the second control signal TOC set high is output. When the terminal voltage VC is smaller than the inversion threshold Vth, the buffer unit BUF outputs the second control signal TOC which is set low.

In fact, in some embodiments, the buffer unit BUF may not be provided. At this time, as long as the terminal voltage VC of the switch capacitor C1 is at a high level, the second control signal TOC that is set high will be output, and if the terminal voltage VC of the switch capacitor C1 is at a low level, the output will be set low. The second control signal TOC.

When the first control signal TFC is at a high level, the third NMOS transistor MN3 is turned on, and the charging capacitor C1 connected to the source and drain of the third NMOS transistor MN3 discharges the third NMOS transistor MN3, and the When the terminal voltage VC of the charging capacitor C1 decreases to less than the flipping threshold Vth, a buffer unit BUF in the shutdown control unit 105 outputs a low level as the second control signal TOC.

When the first control signal TFC is at a low level, the third NMOS transistor MN3 is turned off, and the charging capacitor C1 is charged by the mirror current source, so that the terminal voltage VC of the charging capacitor C1 increases; When the terminal voltage VC increases to be greater than or equal to the inversion threshold Vth, the buffer unit BUF outputs a high level as the second control signal TOC.

In this embodiment, the shutdown control unit 105 further includes a resistor R disposed under the mirror current source for controlling the magnitude of the charging current. in some real In an embodiment, the resistance value of the resistor R can be set as required to adjust the charging current, thereby adjusting the charging time for charging the terminal voltage VC of the charging capacitor C1 above the flipping threshold Vth. The larger the current, the shorter the charging time, and the shorter the time required for the second control signal TOC to change from low level to high level.

In this embodiment, the pulse width modulation signal unit 106 (see FIG. 4 for details) includes an RS latch 201 for outputting the pulse width modulation signal according to the first control signal TFC and the second control signal TOC PWM.

The RS latch 201 includes a second NOR gate NOR2 and a third NOR gate NOR3. One input terminal of the second NOR gate NOR2 is used as the R input terminal, which is connected to the output terminal of the shutdown control unit 105, and the other input terminal is connected to the output terminal of the third NOR gate NOR3. The output terminal of the inverse OR gate NOR2 is used as the Q output terminal.

One input terminal of the third NOR gate NOR3 is used as an S input terminal and connected to the output terminal of the conduction control unit 104 , and the other input terminal is connected to the output terminal of the second NOR gate NOR2 .

In the embodiment shown in FIG. 5, an inverter group INV2 is connected after the Q output terminal of the RS latch. When the driving unit has no inverting function, the inverter group INV2 includes An even number of sequentially connected inverters, otherwise, the inverter group INV2 includes an odd number of sequentially connected inverters. The inverter group INV2 can have the effect of shaping the waveform.

The RS latch 201 has a latching characteristic, specifically: (1) when both the R input terminal and the S input terminal are input at a low level, the signal output by the Q output terminal is compared with the previous state constant; (2) When the input of the R input terminal is a high level and the input of the S input terminal is a low level, the Q output terminal outputs a high level; (3) the input of the R input terminal is a low level When the input of the flat and S input terminals is a high level, the Q output terminal outputs a low level; (4) when both the R input terminal and the S input terminal are input at a high level, the Q output terminal outputs a low level level.

Here you can refer to FIG. 6 , which is a timing diagram of various signals in an embodiment.

In the embodiment shown in FIG. 6, during the time period (t0, t1), the charging capacitor C1 (see FIG. 5) is charged by the charging current, and its terminal voltage VC is greater than or equal to the flipping threshold Vth, so The second control signal TOC is at a high level, at this time, the sampling voltage SW is less than the preset voltage, the comparison unit outputs a high level, and the high level is input to one of the inverting OR gate circuits At the input end, the NOR circuit outputs the first control signal TFC which is set low. At this time, the pulse width modulation signal PWM is the reverse of the output terminal of the RS latch, and when the second control signal TOC is high, the Q output terminal outputs a low level, therefore, the pulse width modulation signal PWM for high.

Because in the time period (t0, t1), the low level of the first control signal TFC controls the terminal voltage VC of the capacitor C in the shutdown control circuit to continuously increase, therefore, the terminal voltage VC is at (t0, The time period t1) is always greater than the flipping threshold Vth, therefore, the second control signal TOC maintains a high level during the time period (t0, t1), and the pulse width modulation signal PWM also maintains a high level.

During the time period (t0, t1), under the action of the pulse width modulation signal PWM being high, the NMOS power transistor is turned on, IL gradually decreases, and the sampling voltage SW gradually increases. in mining When the sample voltage SW increases to be greater than or equal to the preset voltage, that is, at time t1, the output of the comparison unit is reversed and outputs a low level. At this time, the output of the first inverse OR gate NOR1 is modulated by the pulse width signal PWM decision.

Since at the previous moment of t1, the pulse width modulation signal PWM was at a high level, after being inverted by the inverter INV2 in the inverter circuit, it was input from the other input end of the first inverter NOR1 Therefore, at time t1, the first NOR gate NOR1 outputs a high level, and the first control signal TFC is at a high level.

At time t1, since the first control signal TFC turns to a high level, the capacitor C in the circuit of the second control signal TOC discharges instantaneously until the terminal voltage VC is lower than the flipping threshold Vth, and flips to a low level. Therefore, the second control signal TOC also inverts to a low level at the moment when the first control signal TFC inverts.

At this time, the content output from the Q output terminal of the RS latch 201 is related to the signal input from the S input terminal. Since the first control signal TFC is high, the third NOR gate NOR3 outputs a low level, and the two input terminals of NOR2 respectively input the second control signal TOC low level and the level output by the third NOR gate NOR3, so The Q output terminal outputs a high level, and the pulse width modulation signal PWM turns low. However, due to the existence of time delay, the pulse width modulation signal PWM still maintains a high level during the time period (t1, t2), and does not complete the inversion until the time t2, and converts to a low level.

At time t2, since the pulse width modulation signal PWM is turned low, the sampling voltage SW is still greater than the preset voltage, and the comparison unit still outputs a low level, therefore, the first inverting OR gate NOR1 outputs the first control signal TFC which is set low .

During the time period (t2, t3), since the first control signal TFC is set low, The capacitor C in the shutdown control module is charged again, and the terminal voltage VC rises again. At time t3, the terminal voltage VC rises to be greater than or equal to the flipping threshold Vth, and the second control signal TOC flips to a high level again. . Since the pulse width modulation signal PWM is continuously low during the time period (t2, t3), the first inverting OR gate NOR1 continuously outputs a low level.

Another embodiment of the present application provides a soft start method for a DCDC converter.

Please refer to FIG. 3 to FIG. 7 at the same time, wherein FIG. 7 is a schematic flowchart of the steps of the soft start method in an embodiment.

In this embodiment, the DCDC converter includes an output module 102 (see FIGS. 3, 4, and 5 for details), and the output module 102 includes an NMOS power transistor, a PMOS power transistor, and an LC filter circuit. The LC filter The first end of the circuit is connected to the connection point of the NMOS power transistor and the PMOS power transistor, and the second end is grounded; the method includes the following steps:

Step S401: Obtain a sampling voltage SW from the first terminal of the LC filter circuit (see Figures 3, 4, and 5 for details).

The sampling voltage SW is sampled from the first end of the LC filter circuit, and the sampling voltage SW follows the change of the inductance current of the inductance L (see Figures 3, 4, 5) in the LC filter circuit, specifically , the sampling voltage SW is negatively correlated with the magnitude of the inductor current of the inductor L. The inductor current of the inductor L changes with the alternate conduction of the NMOS power transistor and the PMOS power transistor.

Step S402: Provide a pulse width modulation signal PWM to sequentially drive the NMOS power transistor and the PMOS power transistor, and adjust the duty cycle of the pulse width modulation signal according to the change of the sampling voltage SW to control the PMOS power transistor and NMOS power transistors on-time.

When adjusting the duty ratio of the pulse width modulation signal according to the change of the sampling voltage to control the conduction time of the PMOS power transistor and the NMOS power transistor, the following steps are included: comparing the sampling voltage SW with a preset voltage, When the NMOS power transistor is turned on, if the sampling voltage SW is greater than a preset voltage, the PMOS power transistor is controlled to be turned on through the pulse width modulation signal PWM, and the conduction duration of the PMOS power transistor is controlled to be less than or equal to a preset voltage. Set duration.

When the NMOS power transistor is turned on, corresponding to the discharge of the capacitor C in the LC filter current, the inductor current of the inductor L decreases. The sampling voltage SW is greater than the preset voltage, corresponding to the inductor current L decreasing to a certain current. PWM controls the PMOS power transistor to be turned on, corresponding to the capacitor C in the LC filter current being charged, and the inductor current of the inductor L increases. Controlling the conduction duration of the PMOS power transistor to be less than or equal to a preset duration corresponds to limiting the increase of the inductor current of the inductor L.

Please refer to FIG. 8 at the same time, which is a schematic flow chart of the expanded step S402 in FIG. 7 in an embodiment.

In this embodiment, when adjusting the duty ratio of the pulse width modulation signal PWM according to the magnitude of the sampling voltage SW, the following steps are included:

Step S501: Obtain the first control signal TFC and the second control signal TOC according to the magnitude of the sampling voltage SW.

When obtaining the first control signal TFC, the following steps are included: obtaining the pulse width modulation signal PWM; when the sampling voltage SW is greater than the preset voltage, if the pulse width modulation signal PWM is at a high level, output setting the first control signal TFC high, If the pulse width modulation signal PWM is at a low level, output the first control signal TFC which is set low; and/or, when the sampling voltage SW is less than the preset voltage, the comparison unit outputs a high level, and output the first control signal TFC which is set low.

Step S502: Form the pulse width modulation signal PWM according to the first control signal TFC and the second control signal TOC.

Please refer to FIG. 9 , which is a schematic flow chart of the expanded step S502 in FIG. 8 in an embodiment.

In this embodiment, when acquiring the second control signal TOC according to the change of the sampling voltage SW, the following steps are included: Step S601: Provide a charging capacitor C1 (see Figures 4 and 5 for details), and provide a charging current to charge the Capacitor C1 is charged; Step S602: When the first control signal TFC is set high, cut off the connection between the charging current and the charging capacitor C1, and control the charging capacitor C1 to discharge; Step S603: Obtain the charging The terminal voltage VC of the capacitor C1 (see FIG. 5 for details), when the terminal voltage VC is higher than a flipping threshold Vth (see FIG. 5 for details), output the second control signal TOC that is set high, otherwise output the second control signal TOC that is set low The second control signal TOC. It should be noted that the flip threshold Vth here is provided by the buffer unit BUF. In fact, when the buffer unit BUF is not set, the level to be reached when the high level and the low level are flipped can also be used as The flipping threshold Vth.

When acquiring the second control signal TOC according to the change of the sampling voltage SW, the following steps are further included: changing the charging capacitor C1, the charging current and the flipping threshold Vth, thereby adjusting the high duration of the second control signal TOC.

其中Ton為導通時長，所述I為所述充電電流，C為所述充電電容C1的容值，翻轉閾值VTH為所述緩衝單元BUF的翻轉閾值，VGSP3為所述鏡像電流源的電晶體的等效電壓降，R為所述電阻R的阻值。 In this embodiment, the turn-on time Ton of the PMOS power transistor is related to the magnitude of the charging current, the capacitance of the charging capacitor C1 and the magnitude of the flipping threshold, and the relationship is as follows:

Wherein Ton is the conduction duration, the I is the charging current, C is the capacitance of the charging capacitor C1, the flipping threshold VTH is the flipping threshold of the buffer unit BUF, and VGSP3 is the transistor of the mirror current source The equivalent voltage drop, R is the resistance value of the resistor R.

Therefore, in some embodiments, it can be adjusted by adjusting the input voltage Vin connected to the mirror current source, the capacitance C of the charging capacitor C1, the resistance R of the resistor R, and the equivalent voltage drop VGSP3 of the transistor of the mirror current source. The on-time duration.

其中，Ipeak為所述電感電流的峰值，L為所述電感L的自感係數。 The relationship between the conduction duration Ton and the inductor current peak value Ipeak is as follows:

Wherein, Ipeak is the peak value of the inductor current, and L is the self-inductance of the inductor L.

In this embodiment, by controlling the on-time Ton of the PMOS power transistor, the peak value of the inductor current can be controlled to prevent the peak value from being too large, causing inductor saturation and burning out of the DCDC converter.

In this embodiment, the capacitance of the charging capacitor C1, the resistance of the resistor R, and the flipping threshold VTH of the buffer unit BUF can be changed to adjust the inductor current. Flow peak value Ipeak.

In this embodiment, an RS latch is used to process the first control signal TFC and the second control signal TOC, thereby forming the pulse width modulation signal PWM. Specifically, the R input terminal of the RS latch is connected to the output terminal of the shutdown control unit 105 (see FIG. 4 for details), and the S input terminal is connected to the output terminal of the conduction control unit 104 (see FIG. 4 for details). The output terminal, the Q output terminal is connected with an inverter, so as to output the pulse width modulation signal PWM.

In an embodiment of the present application, an electronic device is also provided, and the electronic device includes the DCDC converter in the embodiment shown in FIG. 4 . Due to the DCDC converter, the electronic device can adjust the duty cycle of the pulse width modulation signal according to the sampling voltage, thereby adjusting the conduction time of the PMOS power transistor and the NMOS power transistor, so that the inductor current is reduced to toggle between and increase. Moreover, by setting an appropriate preset voltage and preset duration, the inductor current can be increased from a lower initial point, and the duration of the inductor current increase within one cycle can be limited to prevent the output A large inductive current flows to the external load, causing damage to the external load.

The above is only an embodiment of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process conversion made by using the specification and accompanying drawings of the application, such as the mutual technical characteristics between the various embodiments Combination, or direct or indirect application in other related technical fields, are all included in the scope of patent protection of this application.

101:Oscillation module

102: Output module

103: Drive unit

104: Turn on the control unit

1041: comparison unit

1042: current mirror load

105:Shutdown control unit

201: RS latch

Claims (17)

A DCDC converter, characterized in that it includes: an oscillation module for outputting a pulse width modulation signal according to a sampling voltage; an output module including a PMOS power transistor, an NMOS power transistor and an LC filter circuit, wherein: the PMOS power transistor The source of the NMOS power transistor is used to receive the input voltage, and the gate is connected to the output terminal of the oscillation module; the source of the NMOS power transistor is grounded, the gate is connected to the output terminal of the oscillation module, and the drain is connected to the output terminal of the oscillation module. The drain of the PMOS power transistor; the first end of the LC filter circuit is connected to the drain of the PMOS power transistor, and the first end is connected to the oscillation module to provide the oscillation module with the Sampling voltage, the second terminal of the LC filter circuit is used to output an output voltage; the oscillation module controls the duty ratio of the pulse width modulation signal according to the size of the sampling voltage, and the pulse width modulation signal is When at a high level, if the sampling voltage is greater than a preset voltage, the pulse width modulation signal is reversed to a low level, and the duration of the low level is less than or equal to a preset duration. The DCDC converter according to claim 1, wherein when the oscillation module controls the duty ratio of the pulse width modulation signal according to the magnitude of the sampling voltage, it compares the sampling voltage with a preset voltage, and when the When the NMOS power transistor is turned on, if the sampling voltage is greater than the preset voltage, the PMOS power transistor is controlled to be turned on through the pulse width modulation signal, and the conduction duration of the PMOS power transistor is controlled to be less than or equal to the preset duration . The DCDC converter as described in claim 1, wherein the oscillation module includes: A conduction control unit, connected to the first end of the LC filter circuit, and receiving the pulse width modulation signal, the conduction control unit is used to compare the sampled voltage with the preset voltage, and according to the comparison result and the The pulse width modulation signal outputs a first control signal; the shutdown control unit is connected to the conduction control unit, and is used to output a second control signal according to the first control signal; the pulse width modulation signal unit is connected to the conduction control unit. a control unit and a shutdown control unit, configured to form the pulse width modulation signal according to the first control signal and the second control signal; a drive unit, connected to the pulse width modulation signal unit, for generating the pulse width modulation signal according to the pulse width The modulation signal outputs a driving signal to drive the PMOS power transistor and the NMOS power transistor. The DCDC converter according to claim 3, wherein the conduction control unit includes: a comparison unit having two input terminals, one of which is connected to the output terminal of the sampling voltage, and the other input terminal is used to receive The preset voltage, and output the comparison result; a current mirror load, used to provide a bias current for the comparison unit; an inverting or gate circuit, including a first inverting or gate and an inverter, the first inverter The OR gate has two input terminals, one of which is connected to the output terminal of the comparison unit, and the other input terminal is connected to the output terminal of the pulse width modulation signal unit through the inverter, and the first inverter The output terminal of the OR gate outputs the first control signal. The DCDC converter according to claim 4, wherein the comparison unit includes: a first NMOS transistor and a second NMOS transistor whose gates are connected to each other, and the gate and drain of the first NMOS transistor are connected, so The source of the first NMOS transistor is connected to the first end of the LC filter circuit, and the source of the second NMOS transistor receives the preset voltage; the current mirror load includes: The first PMOS transistor, the source receives the input voltage, and the drain is connected to the drain of the first NMOS transistor; the second PMOS transistor, the source receives the input voltage, and the drain is connected to the second NMOS transistor The drain of the first PMOS tube and the gate of the second PMOS tube are also connected to a bias voltage source, and the bias voltage source is provided for the first PMOS tube and the second PMOS tube. . The DCDC converter according to claim 1, wherein the preset voltage is 0V. The DCDC converter according to claim 3, wherein the shutdown control unit includes: a mirror current source for providing charging current, including a third PMOS transistor and a fourth PMOS transistor whose gates are connected to each other, and the The source electrodes of the third PMOS transistor and the fourth PMOS transistor receive the input voltage; the resistor, the resistor is connected to the output terminal of the mirror current source, and is used to control the magnitude of the charging current; the charging capacitor is passed through the The resistor is connected to the drain of the third PMOS transistor; the switch unit is connected to the output terminal of the conduction control unit, and is connected to the mirror current source and the charging capacitor, and is used to control the current according to the first control signal Controlling the charging capacitor to accept charging from the mirror current source, or controlling the charging capacitor to discharge. The DCDC converter according to claim 7, wherein the shutdown control unit further includes: a buffer unit connected to the charging capacitor for shaping the terminal voltage of the charging capacitor, and the buffer unit There is an inversion threshold, and when the terminal voltage is greater than or equal to the inversion threshold, the terminal voltage is inverted and output. The DCDC converter according to claim 3, wherein the pulse width modulation signal unit includes: an RS latch, including a second NOR gate and a third NOR gate, wherein: the second NOR gate One input terminal is used as the R input terminal, connected to the output terminal of the shutdown control unit, and the other input terminal is connected to the output terminal of the third NOR gate, and the output terminal of the second NOR gate is used as the Q output terminal; One input terminal of the third NOR gate serves as an S input terminal, which is connected to the output terminal of the conduction control unit, and the other input terminal is connected to the output terminal of the second NOR gate. A soft start method for a DCDC converter, characterized in that the DCDC converter includes an output module, the output module includes an NMOS power transistor, a PMOS power transistor, and an LC filter circuit, and the first end of the LC filter circuit is connected to To the connection point of the NMOS power transistor and the PMOS power transistor, the second end is grounded; the method includes the following steps: obtaining a sampling voltage from the first end of the LC filter circuit; providing a pulse width modulation signal to drive the NMOS power tube and PMOS power tube, and adjust the duty cycle of the pulse width modulation signal according to the change of the sampling voltage, so as to control the conduction time of the PMOS power tube and the NMOS power tube. The soft start method of the DCDC converter according to claim 10, wherein the duty cycle of the pulse width modulation signal is adjusted according to the change of the sampling voltage to control the conduction time of the PMOS power transistor and the NMOS power transistor , comprising the following steps: comparing the sampling voltage with a preset voltage, and when the NMOS power transistor is turned on, if the sampling voltage is greater than the preset voltage, controlling the PMOS power transistor to be turned on through the pulse width modulation signal , and control the conduction duration of the PMOS power transistor to be less than or equal to a preset duration. The soft-start method of the DCDC converter according to claim 11, wherein when adjusting the duty ratio of the pulse width modulation signal according to the change of the sampling voltage, the following steps are included: obtaining the first step according to the magnitude of the sampling voltage A control signal and a second control signal; forming the pulse width modulation signal according to the first control signal and the second control signal. The soft start method of the DCDC converter according to claim 12, wherein, when acquiring the first control signal according to the magnitude of the sampling voltage, the following steps are included: acquiring the pulse width modulation signal; when the sampling voltage is greater than the When the preset voltage is used, if the pulse width modulation signal is at a high level, then output the first control signal that is set high, and if the pulse width modulation signal is at a low level, then output the first control signal that is set low A control signal; and/or, when the sampling voltage is lower than the preset voltage, the comparison unit outputs a high level, and outputs the first control signal which is set low. The soft start method of the DCDC converter according to claim 12, wherein when acquiring the second control signal according to the change of the sampling voltage, the following steps are included: providing a charging capacitor, and providing a charging current to charge the charging capacitor; When the first control signal is set high, cut off the connection between the charging current and the charging capacitor, and control the charging capacitor to discharge; obtain the terminal voltage of the charging capacitor, when the terminal voltage is higher than a When the threshold value is reversed, output the second control signal that is set high, otherwise output the second control signal that is set low. The soft-start method of the DCDC converter according to claim 14, wherein when obtaining the second control signal according to the change of the sampling voltage, the following steps are further included: Adjusting the high duration of the second control signal by changing the charging capacitance, charging current and the flipping threshold. The soft start method for a DCDC converter according to claim 12, wherein an RS latch is used to process the first control signal and the second control signal to obtain the pulse width modulation signal. An electronic device, characterized by comprising the DCDC converter according to any one of claims 1 to 9.

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