JP2017529681A5 - - Google Patents

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Publication number
JP2017529681A5
JP2017529681A5 JP2016575021A JP2016575021A JP2017529681A5 JP 2017529681 A5 JP2017529681 A5 JP 2017529681A5 JP 2016575021 A JP2016575021 A JP 2016575021A JP 2016575021 A JP2016575021 A JP 2016575021A JP 2017529681 A5 JP2017529681 A5 JP 2017529681A5
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JP
Japan
Prior art keywords
wafer
flatness
measurement
surface height
error
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JP2016575021A
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English (en)
Japanese (ja)
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JP6650889B2 (ja
JP2017529681A (ja
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Priority claimed from US14/313,733 external-priority patent/US10576603B2/en
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Priority claimed from PCT/US2015/027182 external-priority patent/WO2015199801A1/en
Publication of JP2017529681A publication Critical patent/JP2017529681A/ja
Publication of JP2017529681A5 publication Critical patent/JP2017529681A5/ja
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JP2016575021A 2014-06-24 2015-04-23 半導体プロセス制御のためのパターン付ウェハ形状測定 Active JP6650889B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/313,733 US10576603B2 (en) 2014-04-22 2014-06-24 Patterned wafer geometry measurements for semiconductor process controls
US14/313,733 2014-06-24
PCT/US2015/027182 WO2015199801A1 (en) 2014-06-24 2015-04-23 Patterned wafer geometry measurements for semiconductor process controls

Publications (3)

Publication Number Publication Date
JP2017529681A JP2017529681A (ja) 2017-10-05
JP2017529681A5 true JP2017529681A5 (https=) 2018-06-07
JP6650889B2 JP6650889B2 (ja) 2020-02-19

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JP2016575021A Active JP6650889B2 (ja) 2014-06-24 2015-04-23 半導体プロセス制御のためのパターン付ウェハ形状測定

Country Status (4)

Country Link
EP (2) EP3117454B1 (https=)
JP (1) JP6650889B2 (https=)
KR (1) KR102184033B1 (https=)
WO (1) WO2015199801A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11556738B2 (en) * 2020-10-01 2023-01-17 Kla Corporation System and method for determining target feature focus in image-based overlay metrology
US12385850B2 (en) * 2021-08-16 2025-08-12 Globalwafers Co., Ltd. Semiconductor wafers using front-end processed wafer global geometry metrics
CN118092089B (zh) * 2024-04-23 2024-06-28 南京禄宪自动化科技有限公司 一种光刻晶片性能测试分析系统
CN121348674B (zh) * 2025-12-19 2026-04-10 合肥晶合集成电路股份有限公司 曝光机焦平面的补偿方法及装置、曝光方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3316833B2 (ja) * 1993-03-26 2002-08-19 株式会社ニコン 走査露光方法、面位置設定装置、走査型露光装置、及び前記方法を使用するデバイス製造方法
JP2000094301A (ja) * 1998-09-22 2000-04-04 Canon Inc 基板研磨方法および基板研磨装置
JP2002018701A (ja) * 2000-07-12 2002-01-22 Canon Inc 基板研磨方法および基板研磨装置
US6859260B2 (en) * 2001-04-25 2005-02-22 Asml Holding N.V. Method and system for improving focus accuracy in a lithography system
DE10314212B4 (de) * 2002-03-29 2010-06-02 Hoya Corp. Verfahren zur Herstellung eines Maskenrohlings, Verfahren zur Herstellung einer Transfermaske
JP2004029735A (ja) * 2002-03-29 2004-01-29 Hoya Corp 電子デバイス用基板、該基板を用いたマスクブランクおよび転写用マスク、並びにこれらの製造方法、研磨装置および研磨方法
JP4464033B2 (ja) * 2002-06-13 2010-05-19 信越半導体株式会社 半導体ウエーハの形状評価方法及び形状評価装置
JP3769262B2 (ja) 2002-12-20 2006-04-19 株式会社東芝 ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法
JP4652667B2 (ja) * 2003-02-13 2011-03-16 キヤノン株式会社 面位置計測方法及び走査型露光装置
SG123601A1 (en) * 2003-03-10 2006-07-26 Asml Netherlands Bv Focus spot monitoring in a lithographic projectionapparatus
JP4615225B2 (ja) * 2004-01-09 2011-01-19 株式会社ディスコ 板状物に形成された電極の加工装置,板状物に形成された電極の加工方法,及び板状物に形成された電極の加工装置のチャックテーブルの平面度測定方法
US20050255160A1 (en) 2004-05-11 2005-11-17 Stephen Bell Polymide resin dermal composition
JP2006300676A (ja) * 2005-04-19 2006-11-02 Nikon Corp 平坦度異常検出方法及び露光装置
US8111376B2 (en) * 2007-05-30 2012-02-07 Kla-Tencor Corporation Feedforward/feedback litho process control of stress and overlay
US8768665B2 (en) * 2010-01-08 2014-07-01 Kla-Tencor Technologies Corporation Site based quantification of substrate topography and its relation to lithography defocus and overlay
JP2011249627A (ja) * 2010-05-28 2011-12-08 Toshiba Corp 半導体ウェーハのパターン露光方法
US9087176B1 (en) * 2014-03-06 2015-07-21 Kla-Tencor Corporation Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

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