JP6650889B2 - 半導体プロセス制御のためのパターン付ウェハ形状測定 - Google Patents

半導体プロセス制御のためのパターン付ウェハ形状測定 Download PDF

Info

Publication number
JP6650889B2
JP6650889B2 JP2016575021A JP2016575021A JP6650889B2 JP 6650889 B2 JP6650889 B2 JP 6650889B2 JP 2016575021 A JP2016575021 A JP 2016575021A JP 2016575021 A JP2016575021 A JP 2016575021A JP 6650889 B2 JP6650889 B2 JP 6650889B2
Authority
JP
Japan
Prior art keywords
wafer
flatness
measurement
lithographic
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016575021A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017529681A5 (https=
JP2017529681A (ja
Inventor
プラディープ ブカダラ
プラディープ ブカダラ
ジェイディープ シンハ
ジェイディープ シンハ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KLA Corp
Original Assignee
KLA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/313,733 external-priority patent/US10576603B2/en
Application filed by KLA Corp filed Critical KLA Corp
Publication of JP2017529681A publication Critical patent/JP2017529681A/ja
Publication of JP2017529681A5 publication Critical patent/JP2017529681A5/ja
Application granted granted Critical
Publication of JP6650889B2 publication Critical patent/JP6650889B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
JP2016575021A 2014-06-24 2015-04-23 半導体プロセス制御のためのパターン付ウェハ形状測定 Active JP6650889B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/313,733 US10576603B2 (en) 2014-04-22 2014-06-24 Patterned wafer geometry measurements for semiconductor process controls
US14/313,733 2014-06-24
PCT/US2015/027182 WO2015199801A1 (en) 2014-06-24 2015-04-23 Patterned wafer geometry measurements for semiconductor process controls

Publications (3)

Publication Number Publication Date
JP2017529681A JP2017529681A (ja) 2017-10-05
JP2017529681A5 JP2017529681A5 (https=) 2018-06-07
JP6650889B2 true JP6650889B2 (ja) 2020-02-19

Family

ID=54979333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016575021A Active JP6650889B2 (ja) 2014-06-24 2015-04-23 半導体プロセス制御のためのパターン付ウェハ形状測定

Country Status (4)

Country Link
EP (2) EP3117454B1 (https=)
JP (1) JP6650889B2 (https=)
KR (1) KR102184033B1 (https=)
WO (1) WO2015199801A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11556738B2 (en) * 2020-10-01 2023-01-17 Kla Corporation System and method for determining target feature focus in image-based overlay metrology
US12385850B2 (en) * 2021-08-16 2025-08-12 Globalwafers Co., Ltd. Semiconductor wafers using front-end processed wafer global geometry metrics
CN118092089B (zh) * 2024-04-23 2024-06-28 南京禄宪自动化科技有限公司 一种光刻晶片性能测试分析系统
CN121348674B (zh) * 2025-12-19 2026-04-10 合肥晶合集成电路股份有限公司 曝光机焦平面的补偿方法及装置、曝光方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3316833B2 (ja) * 1993-03-26 2002-08-19 株式会社ニコン 走査露光方法、面位置設定装置、走査型露光装置、及び前記方法を使用するデバイス製造方法
JP2000094301A (ja) * 1998-09-22 2000-04-04 Canon Inc 基板研磨方法および基板研磨装置
JP2002018701A (ja) * 2000-07-12 2002-01-22 Canon Inc 基板研磨方法および基板研磨装置
US6859260B2 (en) * 2001-04-25 2005-02-22 Asml Holding N.V. Method and system for improving focus accuracy in a lithography system
DE10314212B4 (de) * 2002-03-29 2010-06-02 Hoya Corp. Verfahren zur Herstellung eines Maskenrohlings, Verfahren zur Herstellung einer Transfermaske
JP2004029735A (ja) * 2002-03-29 2004-01-29 Hoya Corp 電子デバイス用基板、該基板を用いたマスクブランクおよび転写用マスク、並びにこれらの製造方法、研磨装置および研磨方法
JP4464033B2 (ja) * 2002-06-13 2010-05-19 信越半導体株式会社 半導体ウエーハの形状評価方法及び形状評価装置
JP3769262B2 (ja) 2002-12-20 2006-04-19 株式会社東芝 ウェーハ平坦度評価方法、その評価方法を実行するウェーハ平坦度評価装置、その評価方法を用いたウェーハの製造方法、その評価方法を用いたウェーハ品質保証方法、その評価方法を用いた半導体デバイスの製造方法、およびその評価方法によって評価されたウェーハを用いた半導体デバイスの製造方法
JP4652667B2 (ja) * 2003-02-13 2011-03-16 キヤノン株式会社 面位置計測方法及び走査型露光装置
SG123601A1 (en) * 2003-03-10 2006-07-26 Asml Netherlands Bv Focus spot monitoring in a lithographic projectionapparatus
JP4615225B2 (ja) * 2004-01-09 2011-01-19 株式会社ディスコ 板状物に形成された電極の加工装置，板状物に形成された電極の加工方法，及び板状物に形成された電極の加工装置のチャックテーブルの平面度測定方法
US20050255160A1 (en) 2004-05-11 2005-11-17 Stephen Bell Polymide resin dermal composition
JP2006300676A (ja) * 2005-04-19 2006-11-02 Nikon Corp 平坦度異常検出方法及び露光装置
US8111376B2 (en) * 2007-05-30 2012-02-07 Kla-Tencor Corporation Feedforward/feedback litho process control of stress and overlay
US8768665B2 (en) * 2010-01-08 2014-07-01 Kla-Tencor Technologies Corporation Site based quantification of substrate topography and its relation to lithography defocus and overlay
JP2011249627A (ja) * 2010-05-28 2011-12-08 Toshiba Corp 半導体ウェーハのパターン露光方法
US9087176B1 (en) * 2014-03-06 2015-07-21 Kla-Tencor Corporation Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Also Published As

Publication number Publication date
EP3748669A1 (en) 2020-12-09
EP3117454B1 (en) 2020-06-03
EP3117454A4 (en) 2017-10-18
KR20170018313A (ko) 2017-02-17
JP2017529681A (ja) 2017-10-05
EP3117454A1 (en) 2017-01-18
KR102184033B1 (ko) 2020-11-27
WO2015199801A1 (en) 2015-12-30

Similar Documents

Publication Publication Date Title
TWI685906B (zh) 用於半導體製程控制之圖案化晶圓幾何量測之方法及系統
US9779202B2 (en) Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements
JP7227992B2 (ja) 表面形状由来のオーバーレイの分解分析および分解分析を用いたオーバーレイ制御の向上
KR102046192B1 (ko) 신규 웨이퍼 지오메트리 메트릭을 이용한 오버레이 및 반도체 처리 제어
KR101708078B1 (ko) 플라즈마 챔버의 검정을 위한 에칭 레이트 균일성을 예측하는 방법 및 장치
TWI604545B (zh) 使用晶圓尺寸幾何工具之晶圓高階形狀特徵化及晶圓分類之系統，方法及度量
JP6650889B2 (ja) 半導体プロセス制御のためのパターン付ウェハ形状測定
US9558545B2 (en) Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry
EP3457213A1 (en) Methods and apparatus for use in a device manufacturing method
JP2017529681A5 (https=)
TWI747875B (zh) 重疊方差穩定方法及系統
US10192794B2 (en) Wafer transfer device
Morgenfeld et al. Monitoring process-induced focus errors using high-resolution flatness metrology

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180418

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180418

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190305

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20190531

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190805

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200121

R150 Certificate of patent or registration of utility model

Ref document number: 6650889

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250