KR102184033B1 - 반도체 프로세스 제어를 위한 패터닝된 웨이퍼 지오메트리 측정 - Google Patents

반도체 프로세스 제어를 위한 패터닝된 웨이퍼 지오메트리 측정 Download PDF

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KR102184033B1
KR102184033B1 KR1020167033676A KR20167033676A KR102184033B1 KR 102184033 B1 KR102184033 B1 KR 102184033B1 KR 1020167033676 A KR1020167033676 A KR 1020167033676A KR 20167033676 A KR20167033676 A KR 20167033676A KR 102184033 B1 KR102184033 B1 KR 102184033B1
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Prior art keywords
wafer
flatness
lithographic
front surface
error
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Korean (ko)
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KR20170018313A (ko
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프라딥 부카달라
제이딥 신하
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케이엘에이 코포레이션
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Priority claimed from US14/313,733 external-priority patent/US10576603B2/en
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    • H01L22/12—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H01L21/304—
    • H01L21/30625—
    • H01L21/67242—
    • H01L22/20—
    • H01L22/34—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
KR1020167033676A 2014-06-24 2015-04-23 반도체 프로세스 제어를 위한 패터닝된 웨이퍼 지오메트리 측정 Active KR102184033B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/313,733 US10576603B2 (en) 2014-04-22 2014-06-24 Patterned wafer geometry measurements for semiconductor process controls
US14/313,733 2014-06-24
PCT/US2015/027182 WO2015199801A1 (en) 2014-06-24 2015-04-23 Patterned wafer geometry measurements for semiconductor process controls

Publications (2)

Publication Number Publication Date
KR20170018313A KR20170018313A (ko) 2017-02-17
KR102184033B1 true KR102184033B1 (ko) 2020-11-27

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KR1020167033676A Active KR102184033B1 (ko) 2014-06-24 2015-04-23 반도체 프로세스 제어를 위한 패터닝된 웨이퍼 지오메트리 측정

Country Status (4)

Country Link
EP (2) EP3117454B1 (https=)
JP (1) JP6650889B2 (https=)
KR (1) KR102184033B1 (https=)
WO (1) WO2015199801A1 (https=)

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* Cited by examiner, † Cited by third party
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US11556738B2 (en) * 2020-10-01 2023-01-17 Kla Corporation System and method for determining target feature focus in image-based overlay metrology
US12385850B2 (en) * 2021-08-16 2025-08-12 Globalwafers Co., Ltd. Semiconductor wafers using front-end processed wafer global geometry metrics
CN118092089B (zh) * 2024-04-23 2024-06-28 南京禄宪自动化科技有限公司 一种光刻晶片性能测试分析系统
CN121348674B (zh) * 2025-12-19 2026-04-10 合肥晶合集成电路股份有限公司 曝光机焦平面的补偿方法及装置、曝光方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185662A1 (en) 2002-12-20 2004-09-23 Tadahito Fujisawa Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method
US20050255160A1 (en) 2004-05-11 2005-11-17 Stephen Bell Polymide resin dermal composition

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JP3316833B2 (ja) * 1993-03-26 2002-08-19 株式会社ニコン 走査露光方法、面位置設定装置、走査型露光装置、及び前記方法を使用するデバイス製造方法
JP2000094301A (ja) * 1998-09-22 2000-04-04 Canon Inc 基板研磨方法および基板研磨装置
JP2002018701A (ja) * 2000-07-12 2002-01-22 Canon Inc 基板研磨方法および基板研磨装置
US6859260B2 (en) * 2001-04-25 2005-02-22 Asml Holding N.V. Method and system for improving focus accuracy in a lithography system
DE10314212B4 (de) * 2002-03-29 2010-06-02 Hoya Corp. Verfahren zur Herstellung eines Maskenrohlings, Verfahren zur Herstellung einer Transfermaske
JP2004029735A (ja) * 2002-03-29 2004-01-29 Hoya Corp 電子デバイス用基板、該基板を用いたマスクブランクおよび転写用マスク、並びにこれらの製造方法、研磨装置および研磨方法
JP4464033B2 (ja) * 2002-06-13 2010-05-19 信越半導体株式会社 半導体ウエーハの形状評価方法及び形状評価装置
JP4652667B2 (ja) * 2003-02-13 2011-03-16 キヤノン株式会社 面位置計測方法及び走査型露光装置
SG123601A1 (en) * 2003-03-10 2006-07-26 Asml Netherlands Bv Focus spot monitoring in a lithographic projectionapparatus
JP4615225B2 (ja) * 2004-01-09 2011-01-19 株式会社ディスコ 板状物に形成された電極の加工装置，板状物に形成された電極の加工方法，及び板状物に形成された電極の加工装置のチャックテーブルの平面度測定方法
JP2006300676A (ja) * 2005-04-19 2006-11-02 Nikon Corp 平坦度異常検出方法及び露光装置
US8111376B2 (en) * 2007-05-30 2012-02-07 Kla-Tencor Corporation Feedforward/feedback litho process control of stress and overlay
US8768665B2 (en) * 2010-01-08 2014-07-01 Kla-Tencor Technologies Corporation Site based quantification of substrate topography and its relation to lithography defocus and overlay
JP2011249627A (ja) * 2010-05-28 2011-12-08 Toshiba Corp 半導体ウェーハのパターン露光方法
US9087176B1 (en) * 2014-03-06 2015-07-21 Kla-Tencor Corporation Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185662A1 (en) 2002-12-20 2004-09-23 Tadahito Fujisawa Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method
US20050255160A1 (en) 2004-05-11 2005-11-17 Stephen Bell Polymide resin dermal composition

Also Published As

Publication number Publication date
JP6650889B2 (ja) 2020-02-19
EP3748669A1 (en) 2020-12-09
EP3117454B1 (en) 2020-06-03
EP3117454A4 (en) 2017-10-18
KR20170018313A (ko) 2017-02-17
JP2017529681A (ja) 2017-10-05
EP3117454A1 (en) 2017-01-18
WO2015199801A1 (en) 2015-12-30

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