JP2017523488A5 - - Google Patents

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Publication number
JP2017523488A5
JP2017523488A5 JP2016558772A JP2016558772A JP2017523488A5 JP 2017523488 A5 JP2017523488 A5 JP 2017523488A5 JP 2016558772 A JP2016558772 A JP 2016558772A JP 2016558772 A JP2016558772 A JP 2016558772A JP 2017523488 A5 JP2017523488 A5 JP 2017523488A5
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JP
Japan
Prior art keywords
training
memory
control signal
external memory
engine
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Pending
Application number
JP2016558772A
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English (en)
Japanese (ja)
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JP2017523488A (ja
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Publication date
Priority claimed from US14/318,114 external-priority patent/US9639495B2/en
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Publication of JP2017523488A publication Critical patent/JP2017523488A/ja
Publication of JP2017523488A5 publication Critical patent/JP2017523488A5/ja
Pending legal-status Critical Current

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JP2016558772A 2014-06-27 2015-06-23 メモリ物理層インタフェースのトレーニング用統合型コントローラ Pending JP2017523488A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/318,114 US9639495B2 (en) 2014-06-27 2014-06-27 Integrated controller for training memory physical layer interface
US14/318,114 2014-06-27
PCT/US2015/037210 WO2015200338A1 (en) 2014-06-27 2015-06-23 Integrated controller for training memory physical layer interface

Publications (2)

Publication Number Publication Date
JP2017523488A JP2017523488A (ja) 2017-08-17
JP2017523488A5 true JP2017523488A5 (enExample) 2018-08-02

Family

ID=54930483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016558772A Pending JP2017523488A (ja) 2014-06-27 2015-06-23 メモリ物理層インタフェースのトレーニング用統合型コントローラ

Country Status (6)

Country Link
US (1) US9639495B2 (enExample)
EP (1) EP3105682A4 (enExample)
JP (1) JP2017523488A (enExample)
KR (1) KR102222420B1 (enExample)
CN (1) CN106133710B (enExample)
WO (1) WO2015200338A1 (enExample)

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