CN106133710B - 用于训练存储器物理层接口的集成控制器 - Google Patents

用于训练存储器物理层接口的集成控制器 Download PDF

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Publication number
CN106133710B
CN106133710B CN201580016122.2A CN201580016122A CN106133710B CN 106133710 B CN106133710 B CN 106133710B CN 201580016122 A CN201580016122 A CN 201580016122A CN 106133710 B CN106133710 B CN 106133710B
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training
memory
engine
control signaling
training engine
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CN106133710A (zh
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格伦·A·戴斯
格里·塔尔博特
安瓦尔·卡谢穆
爱德华多·普莱特
布莱恩·布莱恩
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)
CN201580016122.2A 2014-06-27 2015-06-23 用于训练存储器物理层接口的集成控制器 Active CN106133710B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/318,114 2014-06-27
US14/318,114 US9639495B2 (en) 2014-06-27 2014-06-27 Integrated controller for training memory physical layer interface
PCT/US2015/037210 WO2015200338A1 (en) 2014-06-27 2015-06-23 Integrated controller for training memory physical layer interface

Publications (2)

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CN106133710A CN106133710A (zh) 2016-11-16
CN106133710B true CN106133710B (zh) 2019-10-11

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US (1) US9639495B2 (enExample)
EP (1) EP3105682A4 (enExample)
JP (1) JP2017523488A (enExample)
KR (1) KR102222420B1 (enExample)
CN (1) CN106133710B (enExample)
WO (1) WO2015200338A1 (enExample)

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KR20210136480A (ko) * 2020-05-07 2021-11-17 삼성전자주식회사 프로세싱 장치가 실장된 메모리 모듈을 포함하는 컴퓨팅 시스템의 부팅 방법
CN113867803A (zh) 2020-06-30 2021-12-31 华为技术有限公司 一种内存初始化装置、方法及计算机系统
CN113568848B (zh) * 2020-07-29 2023-07-11 华为技术有限公司 处理器、信号调整方法及计算机系统
CN112306775B (zh) * 2020-11-19 2023-03-14 山东云海国创云计算装备产业创新中心有限公司 双路cpu间通信链路的测试方法、装置、设备及介质
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Also Published As

Publication number Publication date
WO2015200338A1 (en) 2015-12-30
JP2017523488A (ja) 2017-08-17
US20150378603A1 (en) 2015-12-31
EP3105682A1 (en) 2016-12-21
EP3105682A4 (en) 2017-11-15
US9639495B2 (en) 2017-05-02
KR102222420B1 (ko) 2021-03-03
CN106133710A (zh) 2016-11-16
KR20170023775A (ko) 2017-03-06

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