JP2017523488A - メモリ物理層インタフェースのトレーニング用統合型コントローラ - Google Patents

メモリ物理層インタフェースのトレーニング用統合型コントローラ Download PDF

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Publication number
JP2017523488A
JP2017523488A JP2016558772A JP2016558772A JP2017523488A JP 2017523488 A JP2017523488 A JP 2017523488A JP 2016558772 A JP2016558772 A JP 2016558772A JP 2016558772 A JP2016558772 A JP 2016558772A JP 2017523488 A JP2017523488 A JP 2017523488A
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training
memory
phy
training engine
sequence
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Japanese (ja)
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JP2017523488A5 (enExample
Inventor
エイ． ダース グレン
エイ． ダース グレン
タルボット ジェリー
タルボット ジェリー
カシェム アンワー
カシェム アンワー
プレーテ エドアルド
プレーテ エドアルド
アミック ブライアン
アミック ブライアン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2017523488A publication Critical patent/JP2017523488A/ja
Publication of JP2017523488A5 publication Critical patent/JP2017523488A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Human Computer Interaction (AREA)
  • Logic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2016558772A 2014-06-27 2015-06-23 メモリ物理層インタフェースのトレーニング用統合型コントローラ Pending JP2017523488A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/318,114 US9639495B2 (en) 2014-06-27 2014-06-27 Integrated controller for training memory physical layer interface
US14/318,114 2014-06-27
PCT/US2015/037210 WO2015200338A1 (en) 2014-06-27 2015-06-23 Integrated controller for training memory physical layer interface

Publications (2)

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JP2017523488A true JP2017523488A (ja) 2017-08-17
JP2017523488A5 JP2017523488A5 (enExample) 2018-08-02

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JP2016558772A Pending JP2017523488A (ja) 2014-06-27 2015-06-23 メモリ物理層インタフェースのトレーニング用統合型コントローラ

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Country Link
US (1) US9639495B2 (enExample)
EP (1) EP3105682A4 (enExample)
JP (1) JP2017523488A (enExample)
KR (1) KR102222420B1 (enExample)
CN (1) CN106133710B (enExample)
WO (1) WO2015200338A1 (enExample)

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CN113867803A (zh) 2020-06-30 2021-12-31 华为技术有限公司 一种内存初始化装置、方法及计算机系统
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CN116795430A (zh) * 2023-06-27 2023-09-22 上海奎芯集成电路设计有限公司 存储器训练装置及存储器训练方法
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WO2015200338A1 (en) 2015-12-30
KR20170023775A (ko) 2017-03-06
KR102222420B1 (ko) 2021-03-03
US20150378603A1 (en) 2015-12-31
CN106133710B (zh) 2019-10-11
US9639495B2 (en) 2017-05-02
EP3105682A4 (en) 2017-11-15
CN106133710A (zh) 2016-11-16
EP3105682A1 (en) 2016-12-21

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