KR102222420B1 - 메모리 물리 계층 인터페이스를 훈련하기 위한 통합 제어기 - Google Patents

메모리 물리 계층 인터페이스를 훈련하기 위한 통합 제어기 Download PDF

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KR102222420B1
KR102222420B1 KR1020167026237A KR20167026237A KR102222420B1 KR 102222420 B1 KR102222420 B1 KR 102222420B1 KR 1020167026237 A KR1020167026237 A KR 1020167026237A KR 20167026237 A KR20167026237 A KR 20167026237A KR 102222420 B1 KR102222420 B1 KR 102222420B1
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training
memory
phy
control signaling
external memory
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KR20170023775A (ko
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글렌 에이. 디어쓰
게리 탈봇
안와르 카셈
에드아르도 프리테
브라이언 아믹
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)
KR1020167026237A 2014-06-27 2015-06-23 메모리 물리 계층 인터페이스를 훈련하기 위한 통합 제어기 Expired - Fee Related KR102222420B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/318,114 2014-06-27
US14/318,114 US9639495B2 (en) 2014-06-27 2014-06-27 Integrated controller for training memory physical layer interface
PCT/US2015/037210 WO2015200338A1 (en) 2014-06-27 2015-06-23 Integrated controller for training memory physical layer interface

Publications (2)

Publication Number Publication Date
KR20170023775A KR20170023775A (ko) 2017-03-06
KR102222420B1 true KR102222420B1 (ko) 2021-03-03

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KR1020167026237A Expired - Fee Related KR102222420B1 (ko) 2014-06-27 2015-06-23 메모리 물리 계층 인터페이스를 훈련하기 위한 통합 제어기

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US (1) US9639495B2 (enExample)
EP (1) EP3105682A4 (enExample)
JP (1) JP2017523488A (enExample)
KR (1) KR102222420B1 (enExample)
CN (1) CN106133710B (enExample)
WO (1) WO2015200338A1 (enExample)

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KR20210136480A (ko) * 2020-05-07 2021-11-17 삼성전자주식회사 프로세싱 장치가 실장된 메모리 모듈을 포함하는 컴퓨팅 시스템의 부팅 방법
CN113867803A (zh) 2020-06-30 2021-12-31 华为技术有限公司 一种内存初始化装置、方法及计算机系统
CN113568848B (zh) * 2020-07-29 2023-07-11 华为技术有限公司 处理器、信号调整方法及计算机系统
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CN115344215B (zh) * 2022-08-29 2025-03-18 深圳市紫光同创电子股份有限公司 存储器训练方法及系统
CN116795430A (zh) * 2023-06-27 2023-09-22 上海奎芯集成电路设计有限公司 存储器训练装置及存储器训练方法
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CN106133710B (zh) 2019-10-11
WO2015200338A1 (en) 2015-12-30
JP2017523488A (ja) 2017-08-17
US20150378603A1 (en) 2015-12-31
EP3105682A1 (en) 2016-12-21
EP3105682A4 (en) 2017-11-15
US9639495B2 (en) 2017-05-02
CN106133710A (zh) 2016-11-16
KR20170023775A (ko) 2017-03-06

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