JP2017511950A5 - - Google Patents

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Publication number
JP2017511950A5
JP2017511950A5 JP2016556945A JP2016556945A JP2017511950A5 JP 2017511950 A5 JP2017511950 A5 JP 2017511950A5 JP 2016556945 A JP2016556945 A JP 2016556945A JP 2016556945 A JP2016556945 A JP 2016556945A JP 2017511950 A5 JP2017511950 A5 JP 2017511950A5
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JP
Japan
Prior art keywords
coupled
memory cell
circuit
memory
transistors
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Application number
JP2016556945A
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English (en)
Japanese (ja)
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JP6773561B2 (ja
JP2017511950A (ja
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Priority claimed from US14/252,551 external-priority patent/US9361965B2/en
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Publication of JP2017511950A publication Critical patent/JP2017511950A/ja
Publication of JP2017511950A5 publication Critical patent/JP2017511950A5/ja
Application granted granted Critical
Publication of JP6773561B2 publication Critical patent/JP6773561B2/ja
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JP2016556945A 2014-03-10 2015-03-10 Ｆｒａｍメモリにおけるインプリント低減のための回路及び方法 Active JP6773561B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461950351P 2014-03-10 2014-03-10
US61/950,351 2014-03-10
US14/252,551 US9361965B2 (en) 2013-10-11 2014-04-14 Circuit and method for imprint reduction in FRAM memories
US14/252,551 2014-04-14
PCT/US2015/019734 WO2015138469A1 (en) 2014-03-10 2015-03-10 Circuit and method for imprint reduction in fram memories

Publications (3)

Publication Number Publication Date
JP2017511950A JP2017511950A (ja) 2017-04-27
JP2017511950A5 true JP2017511950A5 (enExample) 2018-04-12
JP6773561B2 JP6773561B2 (ja) 2020-10-21

Family

ID=54018003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016556945A Active JP6773561B2 (ja) 2014-03-10 2015-03-10 Ｆｒａｍメモリにおけるインプリント低減のための回路及び方法

Country Status (3)

Country Link
US (3) US9361965B2 (enExample)
JP (1) JP6773561B2 (enExample)
WO (1) WO2015138469A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754684B2 (en) * 2014-11-06 2017-09-05 Samsung Electronics Co., Ltd. Completely utilizing hamming distance for SECDED based ECC DIMMs
US10114984B2 (en) * 2015-09-04 2018-10-30 Xerox Corporation Symmetric bit coding for printed memory devices
US9734886B1 (en) * 2016-02-01 2017-08-15 Micron Technology, Inc Cell-based reference voltage generation
US9830979B1 (en) * 2016-05-26 2017-11-28 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for controlling a sense amplifier
US9721639B1 (en) * 2016-06-21 2017-08-01 Micron Technology, Inc. Memory cell imprint avoidance
FR3055062B1 (fr) * 2016-08-11 2018-08-31 Stmicroelectronics Sa Procede d'ecriture autocorrective d'un dispositif de memoire vive statique multiports, et dispositif correspondant
US10796729B2 (en) 2019-02-05 2020-10-06 Micron Technology, Inc. Dynamic allocation of a capacitive component in a memory device
US11194726B2 (en) 2019-02-25 2021-12-07 Micron Technology, Inc. Stacked memory dice for combined access operations
US12112821B2 (en) 2021-06-21 2024-10-08 Seagate Technology Llc Read destructive memory wear leveling system
CN115565566B (zh) * 2021-07-02 2024-09-13 长鑫存储技术有限公司 读出电路结构

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Publication number Priority date Publication date Assignee Title
JPH04286795A (ja) * 1991-03-18 1992-10-12 Fujitsu Ltd 半導体記憶装置
JP3191550B2 (ja) * 1994-02-15 2001-07-23 松下電器産業株式会社 半導体メモリ装置
JPH1011977A (ja) * 1996-06-26 1998-01-16 Hitachi Ltd 半導体記憶装置
US5745403A (en) * 1997-02-28 1998-04-28 Ramtron International Corporation System and method for mitigating imprint effect in ferroelectric random access memories utilizing a complementary data path
JP4421009B2 (ja) * 1999-06-02 2010-02-24 株式会社東芝 強誘電体メモリ
US6141237A (en) * 1999-07-12 2000-10-31 Ramtron International Corporation Ferroelectric non-volatile latch circuits
US6141276A (en) * 1999-09-02 2000-10-31 Micron Technology, Inc. Apparatus and method for increasing test flexibility of a memory device
JP2002184172A (ja) * 2000-10-04 2002-06-28 Rohm Co Ltd データ記憶装置
JP2002343078A (ja) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd 強誘電体メモリ装置
US6522570B1 (en) 2001-12-13 2003-02-18 Micron Technology, Inc. System and method for inhibiting imprinting of capacitor structures of a memory
US6590798B1 (en) 2002-05-08 2003-07-08 Texas Instruments Incorporated Apparatus and methods for imprint reduction for ferroelectric memory cell
US6785629B2 (en) * 2002-07-02 2004-08-31 Agilent Technologies, Inc. Accuracy determination in bit line voltage measurements
US6757206B2 (en) * 2002-09-17 2004-06-29 Texas Instruments Incorporated Sense amplifier with override write circuitry
US7231582B2 (en) * 2003-12-19 2007-06-12 Stmicroelectronics, Inc. Method and system to encode and decode wide data words
US7581154B2 (en) 2005-06-30 2009-08-25 Intel Corporation Method and apparatus to lower operating voltages for memory arrays using error correcting codes
US8495438B2 (en) * 2007-12-28 2013-07-23 Texas Instruments Incorporated Technique for memory imprint reliability improvement
US7729188B2 (en) * 2008-02-11 2010-06-01 International Business Machines Corporation Method and circuit for implementing enhanced eFuse sense circuit
US8300446B2 (en) * 2010-12-13 2012-10-30 Texas Instruments Incorporated Ferroelectric random access memory with single plate line pulse during read
US9230690B2 (en) * 2012-11-07 2016-01-05 Apple Inc. Register file write ring oscillator
US8811057B1 (en) 2013-03-04 2014-08-19 Texas Instruments Incorporated Power reduction circuit and method

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