JP2017511950A - Framメモリにおけるインプリント低減のための回路及び方法 - Google Patents
Framメモリにおけるインプリント低減のための回路及び方法 Download PDFInfo
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- JP2017511950A JP2017511950A JP2016556945A JP2016556945A JP2017511950A JP 2017511950 A JP2017511950 A JP 2017511950A JP 2016556945 A JP2016556945 A JP 2016556945A JP 2016556945 A JP2016556945 A JP 2016556945A JP 2017511950 A JP2017511950 A JP 2017511950A
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- memory cell
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- sense amplifier
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2945—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using at least three error correction codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Probability & Statistics with Applications (AREA)
- Dram (AREA)
Abstract
Description
Claims (20)
- メモリ回路を動作させる方法であって、前記方法が、
データを複数のビットに書き込むこと、
前記データを示す信号ビットに第1のデータ状態を書き込むこと、
前記複数のビットから前記データを読み出すこと、
前記複数のビットに相補データを書き込むこと、及び
前記相補データを示す信号ビットに第2のデータ状態を書き込むこと、
を含む、方法。 - 請求項1に記載の方法であって、前記書き込む工程が、メモリセルのローに書き込むことを含む、方法。
- 請求項1に記載の方法であって、前記複数のビットが、誤り検出訂正(ECC)ビット及びデータビットを含む、方法。
- 請求項3に記載の方法であって、前記ECCビットが、複数の有効コードワードCを含み、各コードワードCが有効相補コードワード~Cを有する、方法。
- 請求項4に記載の方法であって、前記ECCビットが、シングル誤り補正ダブル誤り検出(SECDED)、及びダブル誤り補正トリプル誤り検出(DECTED)符号の一方を含む、方法。
- 請求項1に記載の方法であって、
前記第1のデータ状態に応答して、前記データを複数の出力端子に印加すること、
前記第2のデータ状態に応答して、前記相補データを反転させること、及び
前記反転された相補データを前記出力端子に印加すること、
を含む、方法。 - 請求項1に記載の方法であって、前記読み出す工程に応答して、前記複数のビット及び前記信号ビットからデータをラッチすることを含む、方法。
- 請求項1に記載の方法であって、前記複数のビットの各ビットとの前記信号ビットの排他的ORを行なうことを含む、方法。
- 請求項1に記載の方法であって、前記複数のビットの各ビットとの前記信号ビットの排他的ORを行なうことを含む、方法。
- 反転感知増幅器回路であって、
メモリセル、
感知増幅器、
前記感知増幅器と前記メモリセルとの間に結合される第1のスイッチングトランジスタ、及び
前記感知増幅器に結合される入力端子を有し、前記メモリセルに結合される出力端子を有する、第1のインバータ、
を含む、回路。 - 請求項10に記載の回路であって、前記メモリセルが、1トランジスタ1キャパシタ(1T1C)メモリセルである、回路。
- 請求項10に記載の回路であって、前記メモリセルが、2トランジスタ2キャパシタ(2T2C)メモリセルである、回路。
- 請求項10に記載の回路であって、
前記感知増幅器に結合される第2のスイッチングトランジスタ、及び
前記感知増幅器に結合される入力端子を有し、前記第2のスイッチングトランジスタに結合される出力端子を有する、第2のインバータ、
を含む、回路。 - 請求項10に記載の回路であって、
前記メモリセルと前記感知増幅器との間に結合されるビットライン、及び
前記メモリセルに結合されるワードライン、
を含む、回路。 - 請求項10に記載の回路であって、前記メモリセルが強誘電性メモリセルである、回路。
- 請求項10に記載の回路であって、前記メモリセルが、スタティックランダムアクセスメモリ(SRAM)セル、磁気ランダムアクセスメモリ(MRAM)、及び抵抗性ランダムアクセスメモリ(RRAM)セルの一つである。回路。
- システムであって、
プロセッサ回路、
前記プロセッサ回路に結合される入力デバイス、
前記プロセッサ回路に結合される出力デバイス、及び
反転感知増幅器回路、
を含み、
前記反転感知増幅器回路が、メモリセル、感知増幅器、前記メモリセルと前記感知増幅器との間に結合されるスイッチングトランジスタ、及び、前記感知増幅器に結合される入力端子を有し且つ前記メモリセルに結合される出力端子を有するインバータ、を含む、
システム。 - 請求項17に記載のシステムであって、前記メモリセルが、1トランジスタ1キャパシタ(1T1C)メモリセルである、システム。
- 請求項17に記載のシステムであって、前記メモリセルが、2トランジスタ2キャパシタ(2T2C)メモリセルである、システム。
- 請求項17に記載のシステムであって、前記メモリセルが強誘電性メモリセルである、システム。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461950351P | 2014-03-10 | 2014-03-10 | |
US61/950,351 | 2014-03-10 | ||
US14/252,551 US9361965B2 (en) | 2013-10-11 | 2014-04-14 | Circuit and method for imprint reduction in FRAM memories |
US14/252,551 | 2014-04-14 | ||
PCT/US2015/019734 WO2015138469A1 (en) | 2014-03-10 | 2015-03-10 | Circuit and method for imprint reduction in fram memories |
Publications (3)
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JP2017511950A true JP2017511950A (ja) | 2017-04-27 |
JP2017511950A5 JP2017511950A5 (ja) | 2018-04-12 |
JP6773561B2 JP6773561B2 (ja) | 2020-10-21 |
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JP2016556945A Active JP6773561B2 (ja) | 2014-03-10 | 2015-03-10 | Framメモリにおけるインプリント低減のための回路及び方法 |
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US (3) | US9361965B2 (ja) |
JP (1) | JP6773561B2 (ja) |
WO (1) | WO2015138469A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160054395A (ko) * | 2014-11-06 | 2016-05-16 | 삼성전자주식회사 | 메모리 데이터 에러 정정 방법 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10114984B2 (en) * | 2015-09-04 | 2018-10-30 | Xerox Corporation | Symmetric bit coding for printed memory devices |
US9734886B1 (en) * | 2016-02-01 | 2017-08-15 | Micron Technology, Inc | Cell-based reference voltage generation |
US9830979B1 (en) * | 2016-05-26 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods for controlling a sense amplifier |
US9721639B1 (en) | 2016-06-21 | 2017-08-01 | Micron Technology, Inc. | Memory cell imprint avoidance |
FR3055062B1 (fr) * | 2016-08-11 | 2018-08-31 | Stmicroelectronics Sa | Procede d'ecriture autocorrective d'un dispositif de memoire vive statique multiports, et dispositif correspondant |
US10796729B2 (en) | 2019-02-05 | 2020-10-06 | Micron Technology, Inc. | Dynamic allocation of a capacitive component in a memory device |
US11194726B2 (en) | 2019-02-25 | 2021-12-07 | Micron Technology, Inc. | Stacked memory dice for combined access operations |
CN115565566A (zh) * | 2021-07-02 | 2023-01-03 | 长鑫存储技术有限公司 | 读出电路结构 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04286795A (ja) * | 1991-03-18 | 1992-10-12 | Fujitsu Ltd | 半導体記憶装置 |
JPH07226086A (ja) * | 1994-02-15 | 1995-08-22 | Matsushita Electric Ind Co Ltd | 半導体メモリ装置 |
JPH1011977A (ja) * | 1996-06-26 | 1998-01-16 | Hitachi Ltd | 半導体記憶装置 |
US20020039307A1 (en) * | 2000-10-04 | 2002-04-04 | Rohm Co., Ltd. | Data memory device |
JP2002343078A (ja) * | 2001-05-21 | 2002-11-29 | Matsushita Electric Ind Co Ltd | 強誘電体メモリ装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5745403A (en) * | 1997-02-28 | 1998-04-28 | Ramtron International Corporation | System and method for mitigating imprint effect in ferroelectric random access memories utilizing a complementary data path |
JP4421009B2 (ja) * | 1999-06-02 | 2010-02-24 | 株式会社東芝 | 強誘電体メモリ |
US6141237A (en) * | 1999-07-12 | 2000-10-31 | Ramtron International Corporation | Ferroelectric non-volatile latch circuits |
US6141276A (en) * | 1999-09-02 | 2000-10-31 | Micron Technology, Inc. | Apparatus and method for increasing test flexibility of a memory device |
US6522570B1 (en) | 2001-12-13 | 2003-02-18 | Micron Technology, Inc. | System and method for inhibiting imprinting of capacitor structures of a memory |
US6590798B1 (en) | 2002-05-08 | 2003-07-08 | Texas Instruments Incorporated | Apparatus and methods for imprint reduction for ferroelectric memory cell |
US6785629B2 (en) * | 2002-07-02 | 2004-08-31 | Agilent Technologies, Inc. | Accuracy determination in bit line voltage measurements |
US6757206B2 (en) * | 2002-09-17 | 2004-06-29 | Texas Instruments Incorporated | Sense amplifier with override write circuitry |
US7231582B2 (en) * | 2003-12-19 | 2007-06-12 | Stmicroelectronics, Inc. | Method and system to encode and decode wide data words |
US7581154B2 (en) | 2005-06-30 | 2009-08-25 | Intel Corporation | Method and apparatus to lower operating voltages for memory arrays using error correcting codes |
US8495438B2 (en) * | 2007-12-28 | 2013-07-23 | Texas Instruments Incorporated | Technique for memory imprint reliability improvement |
US7729188B2 (en) * | 2008-02-11 | 2010-06-01 | International Business Machines Corporation | Method and circuit for implementing enhanced eFuse sense circuit |
US8300446B2 (en) * | 2010-12-13 | 2012-10-30 | Texas Instruments Incorporated | Ferroelectric random access memory with single plate line pulse during read |
US9230690B2 (en) * | 2012-11-07 | 2016-01-05 | Apple Inc. | Register file write ring oscillator |
US8811057B1 (en) | 2013-03-04 | 2014-08-19 | Texas Instruments Incorporated | Power reduction circuit and method |
-
2014
- 2014-04-14 US US14/252,551 patent/US9361965B2/en active Active
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2015
- 2015-03-10 WO PCT/US2015/019734 patent/WO2015138469A1/en active Application Filing
- 2015-03-10 JP JP2016556945A patent/JP6773561B2/ja active Active
- 2015-09-04 US US14/846,350 patent/US9799389B2/en active Active
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2017
- 2017-09-21 US US15/710,971 patent/US10153025B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04286795A (ja) * | 1991-03-18 | 1992-10-12 | Fujitsu Ltd | 半導体記憶装置 |
JPH07226086A (ja) * | 1994-02-15 | 1995-08-22 | Matsushita Electric Ind Co Ltd | 半導体メモリ装置 |
JPH1011977A (ja) * | 1996-06-26 | 1998-01-16 | Hitachi Ltd | 半導体記憶装置 |
US20020039307A1 (en) * | 2000-10-04 | 2002-04-04 | Rohm Co., Ltd. | Data memory device |
JP2002184172A (ja) * | 2000-10-04 | 2002-06-28 | Rohm Co Ltd | データ記憶装置 |
JP2002343078A (ja) * | 2001-05-21 | 2002-11-29 | Matsushita Electric Ind Co Ltd | 強誘電体メモリ装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160054395A (ko) * | 2014-11-06 | 2016-05-16 | 삼성전자주식회사 | 메모리 데이터 에러 정정 방법 |
KR102190683B1 (ko) | 2014-11-06 | 2020-12-14 | 삼성전자주식회사 | 메모리 데이터 에러 정정 방법 |
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US20150380071A1 (en) | 2015-12-31 |
US9799389B2 (en) | 2017-10-24 |
US20180012642A1 (en) | 2018-01-11 |
JP6773561B2 (ja) | 2020-10-21 |
US20150255138A1 (en) | 2015-09-10 |
US9361965B2 (en) | 2016-06-07 |
US10153025B2 (en) | 2018-12-11 |
WO2015138469A1 (en) | 2015-09-17 |
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